Revert "imx: keep boot device info for partition reboot"
This reverts commit 8673a8e5abfea5de60680823467ac224526b530f.
SCFW already supported OCRAM retention, so no need to change
primary CPU's boot entry.
(cherry picked from commit e49e1c05893f1d6394361761ce462094796c9044)
diff --git a/plat/imx/imx8qm/imx8qm_bl31_setup.c b/plat/imx/imx8qm/imx8qm_bl31_setup.c
index ed5df85..11af036 100644
--- a/plat/imx/imx8qm/imx8qm_bl31_setup.c
+++ b/plat/imx/imx8qm/imx8qm_bl31_setup.c
@@ -405,9 +405,6 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- u_register_t mpidr = read_mpidr_el1();
- unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
- sc_rsrc_t boot_dev;
#if DEBUG_CONSOLE
static console_lpuart_t console;
@@ -416,11 +413,6 @@
if (sc_ipc_open(&ipc_handle, SC_IPC_BASE) != SC_ERR_NONE)
panic();
- /* set primary CPU boot entry to BL31_BASE for partition reboot */
- sc_misc_get_boot_dev(ipc_handle, &boot_dev);
- sc_pm_set_boot_parm(ipc_handle, cluster_id == 0 ? SC_R_A53_0 : SC_R_A72_0,
- BL31_BASE, SC_R_MU_0A, boot_dev);
-
#if DEBUG_CONSOLE_A53
sc_pm_set_resource_power_mode(ipc_handle, SC_R_UART_0, SC_PM_PW_MODE_ON);
sc_pm_clock_rate_t rate = 80000000;
diff --git a/plat/imx/imx8qm/imx8qm_psci.c b/plat/imx/imx8qm/imx8qm_psci.c
index 1536255..e41baf4 100644
--- a/plat/imx/imx8qm/imx8qm_psci.c
+++ b/plat/imx/imx8qm/imx8qm_psci.c
@@ -300,6 +300,9 @@
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
const plat_psci_ops_t **psci_ops)
{
+ u_register_t mpidr = read_mpidr_el1();
+ unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
+
imx_mailbox_init(sec_entrypoint);
*psci_ops = &imx_plat_psci_ops;
@@ -321,5 +324,12 @@
sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_INTERCONNECT,
SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
+ /*
+ * set partition reboot address for primary CPU, boot device is NOT owned
+ * by ATF, so pass 0 here
+ */
+ sc_pm_set_boot_parm(ipc_handle, cluster_id == 0 ? SC_R_A53_0 : SC_R_A72_0,
+ BL31_BASE, SC_R_MU_0A, 0);
+
return 0;
}
diff --git a/plat/imx/imx8qx/imx8qx_bl31_setup.c b/plat/imx/imx8qx/imx8qx_bl31_setup.c
index 259c683..ef81738 100644
--- a/plat/imx/imx8qx/imx8qx_bl31_setup.c
+++ b/plat/imx/imx8qx/imx8qx_bl31_setup.c
@@ -383,7 +383,6 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- sc_rsrc_t boot_dev;
#if DEBUG_CONSOLE
static console_lpuart_t console;
@@ -392,10 +391,6 @@
if (sc_ipc_open(&ipc_handle, SC_IPC_BASE) != SC_ERR_NONE)
panic();
- /* set primary CPU boot entry to BL31_BASE for partition reboot */
- sc_misc_get_boot_dev(ipc_handle, &boot_dev);
- sc_pm_set_boot_parm(ipc_handle, SC_R_A35_0, BL31_BASE, SC_R_MU_0A, boot_dev);
-
#if DEBUG_CONSOLE_A35
sc_pm_set_resource_power_mode(ipc_handle, SC_R_UART_0, SC_PM_PW_MODE_ON);
sc_pm_clock_rate_t rate = 80000000;
diff --git a/plat/imx/imx8qx/imx8qx_psci.c b/plat/imx/imx8qx/imx8qx_psci.c
index 69addd1..b6b3a95 100644
--- a/plat/imx/imx8qx/imx8qx_psci.c
+++ b/plat/imx/imx8qx/imx8qx_psci.c
@@ -238,5 +238,11 @@
sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_INTERCONNECT,
SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
+ /*
+ * set partition reboot address for primary CPU, boot device is NOT owned
+ * by ATF, so pass 0 here
+ */
+ sc_pm_set_boot_parm(ipc_handle, SC_R_A35_0, BL31_BASE, SC_R_MU_0A, 0);
+
return 0;
}
