| /* |
| * Copyright (c) 2005-2016 Freescale Semiconductor, Inc. |
| * Copyright 2017 NXP |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| /* Instance: IMXDPU */ |
| |
| #ifndef IMXDPUV1_REGISTERS_H |
| #define IMXDPUV1_REGISTERS_H |
| /* Register: IMXDPUV1_comctrl_IPIdentifier */ |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER ((uint32_t)(0)) |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_OFFSET ((uint32_t)(0)) |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_RESET_VALUE 0x21340400U |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNDELIVERYID_MASK 0xF0U |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNDELIVERYID_SHIFT 4U |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL_MASK 0xF00U |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL_SHIFT 8U |
| /* Field Value: DESIGNMATURITYLEVEL__PREFS, Pre feasibility study. */ |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__PREFS 0x1U |
| /* Field Value: DESIGNMATURITYLEVEL__FS, Feasibility study. */ |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__FS 0x2U |
| /* Field Value: DESIGNMATURITYLEVEL__R0, Functionality complete. */ |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__R0 0x3U |
| /* Field Value: DESIGNMATURITYLEVEL__R1, Verification complete. */ |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__R1 0x4U |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPEVOLUTION_MASK 0xF000U |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPEVOLUTION_SHIFT 12U |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET_MASK 0xF0000U |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET_SHIFT 16U |
| /* Field Value: IPFEATURESET__E, Minimal functionality (Eco). */ |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__E 0x1U |
| /* Field Value: IPFEATURESET__L, Reduced functionality (Light). */ |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__L 0x2U |
| /* Field Value: IPFEATURESET__P, Advanced functionality (Plus). */ |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__P 0x4U |
| /* Field Value: IPFEATURESET__X, Extensive functionality (eXtensive). */ |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__X 0x5U |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION_MASK 0xF00000U |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION_SHIFT 20U |
| /* Field Value: IPAPPLICATION__B, Blit Engine only. */ |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__B 0x1U |
| /* Field Value: IPAPPLICATION__D, Blit Engine and Display Controller. */ |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__D 0x2U |
| /* Field Value: IPAPPLICATION__V, Display Controller only (with direct capture). */ |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__V 0x3U |
| /* Field Value: IPAPPLICATION__G, Blit Engine, Display Controller (with direct |
| * capture), Capture Controller (buffered capture) and Drawing Engine. */ |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__G 0x4U |
| /* Field Value: IPAPPLICATION__C, Display Controller only. */ |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__C 0x5U |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION_MASK 0xF000000U |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION_SHIFT 24U |
| /* Field Value: IPCONFIGURATION__M, Graphics core only (Module). */ |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION__M 0x1U |
| /* Field Value: IPCONFIGURATION__S, Subsystem including a graphics core (System). */ |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION__S 0x2U |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY_MASK 0xF0000000U |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY_SHIFT 28U |
| /* Field Value: IPFAMILY__IMXDPU2010, IMXDPU building block generation 2010. */ |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY__IMXDPU2010 0U |
| /* Field Value: IPFAMILY__IMXDPU2012, IMXDPU building block generation 2012. */ |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY__IMXDPU2012 0x1U |
| /* Field Value: IPFAMILY__IMXDPU2013, IMXDPU building block generation 2013. */ |
| #define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY__IMXDPU2013 0x2U |
| |
| /* Register: IMXDPUV1_comctrl_LockUnlock */ |
| #define IMXDPUV1_COMCTRL_LOCKUNLOCK ((uint32_t)(0x40)) |
| #define IMXDPUV1_COMCTRL_LOCKUNLOCK_OFFSET ((uint32_t)(0x40)) |
| #define IMXDPUV1_COMCTRL_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_COMCTRL_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When |
| * the counter value is null, lock protection is active. Reset counter value |
| * is 1. */ |
| #define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max |
| * allowed value is 15. */ |
| #define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled |
| * after reset. */ |
| #define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ |
| #define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. |
| * Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_comctrl_LockStatus */ |
| #define IMXDPUV1_COMCTRL_LOCKSTATUS ((uint32_t)(0x44)) |
| #define IMXDPUV1_COMCTRL_LOCKSTATUS_OFFSET ((uint32_t)(0x44)) |
| #define IMXDPUV1_COMCTRL_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_COMCTRL_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_LOCKSTATUS_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_COMCTRL_LOCKSTATUS_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_COMCTRL_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_COMCTRL_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_COMCTRL_LOCKSTATUS_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_COMCTRL_LOCKSTATUS_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_comctrl_UserInterruptMask0 */ |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0 ((uint32_t)(0x48)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_OFFSET ((uint32_t)(0x48)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_RESET_VALUE 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_USERINTERRUPTMASK0_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_USERINTERRUPTMASK0_SHIFT 0U |
| |
| /* Register: IMXDPUV1_comctrl_UserInterruptMask1 */ |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1 ((uint32_t)(0x4C)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_OFFSET ((uint32_t)(0x4C)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_RESET_VALUE 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_USERINTERRUPTMASK1_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_USERINTERRUPTMASK1_SHIFT 0U |
| |
| /* Register: IMXDPUV1_comctrl_InterruptEnable0 */ |
| #define IMXDPUV1_COMCTRL_INTERRUPTENABLE0 ((uint32_t)(0x50)) |
| #define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_OFFSET ((uint32_t)(0x50)) |
| #define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_RESET_VALUE 0U |
| #define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_INTERRUPTENABLE0_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_INTERRUPTENABLE0_SHIFT 0U |
| |
| /* Register: IMXDPUV1_comctrl_InterruptEnable1 */ |
| #define IMXDPUV1_COMCTRL_INTERRUPTENABLE1 ((uint32_t)(0x54)) |
| #define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_OFFSET ((uint32_t)(0x54)) |
| #define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_RESET_VALUE 0U |
| #define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_INTERRUPTENABLE1_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_INTERRUPTENABLE1_SHIFT 0U |
| |
| /* Register: IMXDPUV1_comctrl_InterruptPreset0 */ |
| #define IMXDPUV1_COMCTRL_INTERRUPTPRESET0 ((uint32_t)(0x58)) |
| #define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_OFFSET ((uint32_t)(0x58)) |
| #define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_RESET_VALUE 0U |
| #define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_RESET_MASK 0U |
| #define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_INTERRUPTPRESET0_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_INTERRUPTPRESET0_SHIFT 0U |
| |
| /* Register: IMXDPUV1_comctrl_InterruptPreset1 */ |
| #define IMXDPUV1_COMCTRL_INTERRUPTPRESET1 ((uint32_t)(0x5C)) |
| #define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_OFFSET ((uint32_t)(0x5C)) |
| #define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_RESET_VALUE 0U |
| #define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_RESET_MASK 0U |
| #define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_INTERRUPTPRESET1_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_INTERRUPTPRESET1_SHIFT 0U |
| |
| /* Register: IMXDPUV1_comctrl_InterruptClear0 */ |
| #define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0 ((uint32_t)(0x60)) |
| #define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_OFFSET ((uint32_t)(0x60)) |
| #define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_RESET_VALUE 0U |
| #define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_RESET_MASK 0U |
| #define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_INTERRUPTCLEAR0_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_INTERRUPTCLEAR0_SHIFT 0U |
| |
| /* Register: IMXDPUV1_comctrl_InterruptClear1 */ |
| #define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1 ((uint32_t)(0x64)) |
| #define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_OFFSET ((uint32_t)(0x64)) |
| #define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_RESET_VALUE 0U |
| #define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_RESET_MASK 0U |
| #define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_INTERRUPTCLEAR1_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_INTERRUPTCLEAR1_SHIFT 0U |
| |
| /* Register: IMXDPUV1_comctrl_InterruptStatus0 */ |
| #define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0 ((uint32_t)(0x68)) |
| #define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_OFFSET ((uint32_t)(0x68)) |
| #define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_RESET_VALUE 0U |
| #define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_RESET_MASK 0U |
| #define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_INTERRUPTSTATUS0_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_INTERRUPTSTATUS0_SHIFT 0U |
| |
| /* Register: IMXDPUV1_comctrl_InterruptStatus1 */ |
| #define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1 ((uint32_t)(0x6C)) |
| #define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_OFFSET ((uint32_t)(0x6C)) |
| #define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_RESET_VALUE 0U |
| #define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_RESET_MASK 0U |
| #define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_INTERRUPTSTATUS1_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_INTERRUPTSTATUS1_SHIFT 0U |
| |
| /* Register: IMXDPUV1_comctrl_UserInterruptEnable0 */ |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0 ((uint32_t)(0x80)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_OFFSET ((uint32_t)(0x80)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_RESET_VALUE 0U |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_USERINTERRUPTENABLE0_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_USERINTERRUPTENABLE0_SHIFT 0U |
| |
| /* Register: IMXDPUV1_comctrl_UserInterruptEnable1 */ |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1 ((uint32_t)(0x84)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_OFFSET ((uint32_t)(0x84)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_RESET_VALUE 0U |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_USERINTERRUPTENABLE1_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_USERINTERRUPTENABLE1_SHIFT 0U |
| |
| /* Register: IMXDPUV1_comctrl_UserInterruptPreset0 */ |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0 ((uint32_t)(0x88)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_OFFSET ((uint32_t)(0x88)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_RESET_VALUE 0U |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_RESET_MASK 0U |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_USERINTERRUPTPRESET0_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_USERINTERRUPTPRESET0_SHIFT 0U |
| |
| /* Register: IMXDPUV1_comctrl_UserInterruptPreset1 */ |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1 ((uint32_t)(0x8C)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_OFFSET ((uint32_t)(0x8C)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_RESET_VALUE 0U |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_RESET_MASK 0U |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_USERINTERRUPTPRESET1_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_USERINTERRUPTPRESET1_SHIFT 0U |
| |
| /* Register: IMXDPUV1_comctrl_UserInterruptClear0 */ |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0 ((uint32_t)(0x90)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_OFFSET ((uint32_t)(0x90)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_RESET_VALUE 0U |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_RESET_MASK 0U |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_USERINTERRUPTCLEAR0_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_USERINTERRUPTCLEAR0_SHIFT 0U |
| |
| /* Register: IMXDPUV1_comctrl_UserInterruptClear1 */ |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1 ((uint32_t)(0x94)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_OFFSET ((uint32_t)(0x94)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_RESET_VALUE 0U |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_RESET_MASK 0U |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_USERINTERRUPTCLEAR1_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_USERINTERRUPTCLEAR1_SHIFT 0U |
| |
| /* Register: IMXDPUV1_comctrl_UserInterruptStatus0 */ |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0 ((uint32_t)(0x98)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_OFFSET ((uint32_t)(0x98)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_RESET_VALUE 0U |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_RESET_MASK 0U |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_USERINTERRUPTSTATUS0_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_USERINTERRUPTSTATUS0_SHIFT 0U |
| |
| /* Register: IMXDPUV1_comctrl_UserInterruptStatus1 */ |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1 ((uint32_t)(0xA8)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_OFFSET ((uint32_t)(0xA8)) |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_RESET_VALUE 0U |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_RESET_MASK 0U |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_USERINTERRUPTSTATUS1_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_USERINTERRUPTSTATUS1_SHIFT 0U |
| |
| /* Register: IMXDPUV1_comctrl_GeneralPurpose */ |
| #define IMXDPUV1_COMCTRL_GENERALPURPOSE ((uint32_t)(0x100)) |
| #define IMXDPUV1_COMCTRL_GENERALPURPOSE_OFFSET ((uint32_t)(0x100)) |
| #define IMXDPUV1_COMCTRL_GENERALPURPOSE_RESET_VALUE 0U |
| #define IMXDPUV1_COMCTRL_GENERALPURPOSE_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_GENERALPURPOSE_GENERALPURPOSE_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_COMCTRL_GENERALPURPOSE_GENERALPURPOSE_SHIFT 0U |
| |
| /* Register: IMXDPUV1_cmdseq_HIF */ |
| #define IMXDPUV1_CMDSEQ_HIF ((uint32_t)(0x400)) |
| #define IMXDPUV1_CMDSEQ_HIF_OFFSET ((uint32_t)(0)) |
| #define IMXDPUV1_CMDSEQ_HIF_RESET_VALUE 0U |
| #define IMXDPUV1_CMDSEQ_HIF_RESET_MASK 0U |
| #define IMXDPUV1_CMDSEQ_HIF_COMMANDFIFO_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_CMDSEQ_HIF_COMMANDFIFO_SHIFT 0U |
| |
| /* Register: IMXDPUV1_cmdseq_LockUnlockHIF */ |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF ((uint32_t)(0x500)) |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_OFFSET ((uint32_t)(0x100)) |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_RESET_VALUE 0U |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_RESET_MASK 0U |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF_SHIFT 0U |
| /* Field Value: LOCKUNLOCKHIF__LOCK_KEY, Decrements the unlock counter. When |
| * the counter value is null, lock protection is active. Reset counter |
| * value is 1. */ |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__LOCK_KEY 0x5651F763U |
| /* Field Value: LOCKUNLOCKHIF__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__UNLOCK_KEY 0x691DB936U |
| /* Field Value: LOCKUNLOCKHIF__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: LOCKUNLOCKHIF__UNPRIVILEGE_KEY, Disables privilege protection. */ |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: LOCKUNLOCKHIF__FREEZE_KEY, Freezes current protection status. |
| * Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_cmdseq_LockStatusHIF */ |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF ((uint32_t)(0x504)) |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_OFFSET ((uint32_t)(0x104)) |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_RESET_VALUE 0U |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_LOCKSTATUSHIF_MASK 0x1U |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_LOCKSTATUSHIF_SHIFT 0U |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_PRIVILEGESTATUSHIF_MASK 0x10U |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_PRIVILEGESTATUSHIF_SHIFT 4U |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_FREEZESTATUSHIF_MASK 0x100U |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_FREEZESTATUSHIF_SHIFT 8U |
| |
| /* Register: IMXDPUV1_cmdseq_LockUnlock */ |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCK ((uint32_t)(0x580)) |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCK_OFFSET ((uint32_t)(0x180)) |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When |
| * the counter value is null, lock protection is active. Reset counter value |
| * is 1. */ |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max |
| * allowed value is 15. */ |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled |
| * after reset. */ |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. |
| * Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_cmdseq_LockStatus */ |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUS ((uint32_t)(0x584)) |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUS_OFFSET ((uint32_t)(0x184)) |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUS_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUS_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUS_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_CMDSEQ_LOCKSTATUS_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_cmdseq_BufferAddress */ |
| #define IMXDPUV1_CMDSEQ_BUFFERADDRESS ((uint32_t)(0x588)) |
| #define IMXDPUV1_CMDSEQ_BUFFERADDRESS_OFFSET ((uint32_t)(0x188)) |
| #define IMXDPUV1_CMDSEQ_BUFFERADDRESS_RESET_VALUE 0U |
| #define IMXDPUV1_CMDSEQ_BUFFERADDRESS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_CMDSEQ_BUFFERADDRESS_LOCAL_MASK 0x1U |
| #define IMXDPUV1_CMDSEQ_BUFFERADDRESS_LOCAL_SHIFT 0U |
| #define IMXDPUV1_CMDSEQ_BUFFERADDRESS_ADDR_MASK 0xFFFFFFE0U |
| #define IMXDPUV1_CMDSEQ_BUFFERADDRESS_ADDR_SHIFT 5U |
| |
| /* Register: IMXDPUV1_cmdseq_BufferSize */ |
| #define IMXDPUV1_CMDSEQ_BUFFERSIZE ((uint32_t)(0x58C)) |
| #define IMXDPUV1_CMDSEQ_BUFFERSIZE_OFFSET ((uint32_t)(0x18C)) |
| #define IMXDPUV1_CMDSEQ_BUFFERSIZE_RESET_VALUE 0x80U |
| #define IMXDPUV1_CMDSEQ_BUFFERSIZE_RESET_MASK 0xFFF8U |
| #define IMXDPUV1_CMDSEQ_BUFFERSIZE_SIZE_MASK 0xFFF8U |
| #define IMXDPUV1_CMDSEQ_BUFFERSIZE_SIZE_SHIFT 3U |
| |
| /* Register: IMXDPUV1_cmdseq_WatermarkControl */ |
| #define IMXDPUV1_CMDSEQ_WATERMARKCONTROL ((uint32_t)(0x590)) |
| #define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_OFFSET ((uint32_t)(0x190)) |
| #define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_RESET_VALUE 0x600020U |
| #define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_LOWWM_MASK 0xFFFFU |
| #define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_LOWWM_SHIFT 0U |
| #define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_HIGHWM_MASK 0xFFFF0000U |
| #define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_HIGHWM_SHIFT 16U |
| |
| /* Register: IMXDPUV1_cmdseq_Control */ |
| #define IMXDPUV1_CMDSEQ_CONTROL ((uint32_t)(0x594)) |
| #define IMXDPUV1_CMDSEQ_CONTROL_OFFSET ((uint32_t)(0x194)) |
| #define IMXDPUV1_CMDSEQ_CONTROL_RESET_VALUE 0U |
| #define IMXDPUV1_CMDSEQ_CONTROL_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_CMDSEQ_CONTROL_CLRAXIW_MASK 0x1U |
| #define IMXDPUV1_CMDSEQ_CONTROL_CLRAXIW_SHIFT 0U |
| #define IMXDPUV1_CMDSEQ_CONTROL_CLRRBUF_MASK 0x4U |
| #define IMXDPUV1_CMDSEQ_CONTROL_CLRRBUF_SHIFT 2U |
| #define IMXDPUV1_CMDSEQ_CONTROL_CLRCMDBUF_MASK 0x8U |
| #define IMXDPUV1_CMDSEQ_CONTROL_CLRCMDBUF_SHIFT 3U |
| #define IMXDPUV1_CMDSEQ_CONTROL_CLEAR_MASK 0x80000000U |
| #define IMXDPUV1_CMDSEQ_CONTROL_CLEAR_SHIFT 31U |
| |
| /* Register: IMXDPUV1_cmdseq_Status */ |
| #define IMXDPUV1_CMDSEQ_STATUS ((uint32_t)(0x598)) |
| #define IMXDPUV1_CMDSEQ_STATUS_OFFSET ((uint32_t)(0x198)) |
| #define IMXDPUV1_CMDSEQ_STATUS_RESET_VALUE 0x41000080U |
| #define IMXDPUV1_CMDSEQ_STATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_CMDSEQ_STATUS_FIFOSPACE_MASK 0x1FFFFU |
| #define IMXDPUV1_CMDSEQ_STATUS_FIFOSPACE_SHIFT 0U |
| #define IMXDPUV1_CMDSEQ_STATUS_FIFOEMPTY_MASK 0x1000000U |
| #define IMXDPUV1_CMDSEQ_STATUS_FIFOEMPTY_SHIFT 24U |
| #define IMXDPUV1_CMDSEQ_STATUS_FIFOFULL_MASK 0x2000000U |
| #define IMXDPUV1_CMDSEQ_STATUS_FIFOFULL_SHIFT 25U |
| #define IMXDPUV1_CMDSEQ_STATUS_FIFOWMSTATE_MASK 0x4000000U |
| #define IMXDPUV1_CMDSEQ_STATUS_FIFOWMSTATE_SHIFT 26U |
| #define IMXDPUV1_CMDSEQ_STATUS_WATCHDOG_MASK 0x8000000U |
| #define IMXDPUV1_CMDSEQ_STATUS_WATCHDOG_SHIFT 27U |
| #define IMXDPUV1_CMDSEQ_STATUS_READBUSY_MASK 0x10000000U |
| #define IMXDPUV1_CMDSEQ_STATUS_READBUSY_SHIFT 28U |
| #define IMXDPUV1_CMDSEQ_STATUS_WRITEBUSY_MASK 0x20000000U |
| #define IMXDPUV1_CMDSEQ_STATUS_WRITEBUSY_SHIFT 29U |
| #define IMXDPUV1_CMDSEQ_STATUS_IDLE_MASK 0x40000000U |
| #define IMXDPUV1_CMDSEQ_STATUS_IDLE_SHIFT 30U |
| #define IMXDPUV1_CMDSEQ_STATUS_ERRORHALT_MASK 0x80000000U |
| #define IMXDPUV1_CMDSEQ_STATUS_ERRORHALT_SHIFT 31U |
| |
| /* Register: IMXDPUV1_cmdseq_PrefetchWindowStart */ |
| #define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART ((uint32_t)(0x59C)) |
| #define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_OFFSET ((uint32_t)(0x19C)) |
| #define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_RESET_VALUE 0U |
| #define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_RESET_MASK 0xFFFFFFFCU |
| #define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_PWSTART_MASK 0xFFFFFFFCU |
| #define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_PWSTART_SHIFT 2U |
| |
| /* Register: IMXDPUV1_cmdseq_PrefetchWindowEnd */ |
| #define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND ((uint32_t)(0x5A0)) |
| #define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_OFFSET ((uint32_t)(0x1A0)) |
| #define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_RESET_VALUE 0xFFFFFFFCU |
| #define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_RESET_MASK 0xFFFFFFFCU |
| #define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_PWEND_MASK 0xFFFFFFFCU |
| #define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_PWEND_SHIFT 2U |
| |
| /* Register: IMXDPUV1_pixengcfg_SafetyLockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK ((uint32_t)(0x800)) |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_OFFSET ((uint32_t)(0)) |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK_SHIFT 0U |
| /* Field Value: SAFETYLOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset counter |
| * value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: SAFETYLOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: SAFETYLOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: SAFETYLOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: SAFETYLOCKUNLOCK__FREEZE_KEY, Freezes current protection status. |
| * Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_SafetyLockStatus */ |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS ((uint32_t)(0x804)) |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_OFFSET ((uint32_t)(0x4)) |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYLOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYLOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYPRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYPRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYFREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYFREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_store9_SafetyMask */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK ((uint32_t)(0x808)) |
| #define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_OFFSET ((uint32_t)(0x8)) |
| #define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_RESET_VALUE 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_STORE9_SAFETYMASK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_STORE9_SAFETYMASK_SHIFT 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst0_SafetyMask */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK ((uint32_t)(0x80C)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_OFFSET ((uint32_t)(0xC)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_RESET_VALUE 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_EXTDST0_SAFETYMASK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_EXTDST0_SAFETYMASK_SHIFT 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst4_SafetyMask */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK ((uint32_t)(0x810)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_OFFSET ((uint32_t)(0x10)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_RESET_VALUE 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_EXTDST4_SAFETYMASK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_EXTDST4_SAFETYMASK_SHIFT 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst1_SafetyMask_0 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0 ((uint32_t)(0x814)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_OFFSET ((uint32_t)(0x14)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_RESET_VALUE 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_EXTDST1_SAFETYMASK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_EXTDST1_SAFETYMASK_SHIFT 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst5_SafetyMask */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK ((uint32_t)(0x818)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_OFFSET ((uint32_t)(0x18)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_RESET_VALUE 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_EXTDST5_SAFETYMASK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_EXTDST5_SAFETYMASK_SHIFT 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchdecode9_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK ((uint32_t)(0x820)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_OFFSET ((uint32_t)(0x20)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: FETCHDECODE9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset |
| * counter value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: FETCHDECODE9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock |
| * counter. Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: FETCHDECODE9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege |
| * protection. Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: FETCHDECODE9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege |
| * protection. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: FETCHDECODE9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchdecode9_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS ((uint32_t)(0x824)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_OFFSET ((uint32_t)(0x24)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchdecode9_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC ((uint32_t)(0x828)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_OFFSET ((uint32_t)(0x28)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL_SHIFT 0U |
| /* Field Value: FETCHDECODE9_SRC_SEL__DISABLE, Unit fetchdecode9 input port |
| * src is disabled */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL__DISABLE 0U |
| /* Field Value: FETCHDECODE9_SRC_SEL__FETCHECO9, Unit fetchdecode9 input port |
| * src is connected to output of unit fetcheco9 */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL__FETCHECO9 0x3U |
| /* Field Value: FETCHDECODE9_SRC_SEL__FETCHPERSP9, Unit fetchdecode9 input |
| * port src is connected to output of unit fetchpersp9 */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL__FETCHPERSP9 0x2U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchdecode9_Status */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS ((uint32_t)(0x82C)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_OFFSET ((uint32_t)(0x2C)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL_SHIFT 16U |
| /* Field Value: FETCHDECODE9_SEL__STORE9, fetchdecode9 module is used from |
| * store9 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__STORE9 0x1U |
| /* Field Value: FETCHDECODE9_SEL__EXTDST0, fetchdecode9 module is used from |
| * extdst0 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST0 0x2U |
| /* Field Value: FETCHDECODE9_SEL__EXTDST4, fetchdecode9 module is used from |
| * extdst4 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST4 0x3U |
| /* Field Value: FETCHDECODE9_SEL__EXTDST1, fetchdecode9 module is used from |
| * extdst1 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST1 0x4U |
| /* Field Value: FETCHDECODE9_SEL__EXTDST5, fetchdecode9 module is used from |
| * extdst5 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST5 0x5U |
| /* Field Value: FETCHDECODE9_SEL__STORE4, fetchdecode9 module is used from |
| * store4 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__STORE4 0x6U |
| /* Field Value: FETCHDECODE9_SEL__STORE5, fetchdecode9 module is used from |
| * store5 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__STORE5 0x7U |
| /* Field Value: FETCHDECODE9_SEL__DISABLE, fetchdecode9 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchwarp9_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK ((uint32_t)(0x840)) |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_OFFSET ((uint32_t)(0x40)) |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: FETCHWARP9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset |
| * counter value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: FETCHWARP9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: FETCHWARP9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: FETCHWARP9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege |
| * protection. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: FETCHWARP9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchwarp9_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS ((uint32_t)(0x844)) |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_OFFSET ((uint32_t)(0x44)) |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchwarp9_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC ((uint32_t)(0x848)) |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_OFFSET ((uint32_t)(0x48)) |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL_SHIFT 0U |
| /* Field Value: FETCHWARP9_SRC_SEL__DISABLE, Unit fetchpersp9 input port src |
| * is disabled */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL__DISABLE 0U |
| /* Field Value: FETCHWARP9_SRC_SEL__FETCHECO9, Unit fetchpersp9 input port |
| * src is connected to output of unit fetcheco9 */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL__FETCHECO9 0x3U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchwarp9_Status */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS ((uint32_t)(0x84C)) |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_OFFSET ((uint32_t)(0x4C)) |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL_SHIFT 16U |
| /* Field Value: FETCHWARP9_SEL__STORE9, fetchpersp9 module is used from store9 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__STORE9 0x1U |
| /* Field Value: FETCHWARP9_SEL__EXTDST0, fetchpersp9 module is used from extdst0 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST0 0x2U |
| /* Field Value: FETCHWARP9_SEL__EXTDST4, fetchpersp9 module is used from extdst4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST4 0x3U |
| /* Field Value: FETCHWARP9_SEL__EXTDST1, fetchpersp9 module is used from extdst1 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST1 0x4U |
| /* Field Value: FETCHWARP9_SEL__EXTDST5, fetchpersp9 module is used from extdst5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST5 0x5U |
| /* Field Value: FETCHWARP9_SEL__STORE4, fetchpersp9 module is used from store4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__STORE4 0x6U |
| /* Field Value: FETCHWARP9_SEL__STORE5, fetchpersp9 module is used from store5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__STORE5 0x7U |
| /* Field Value: FETCHWARP9_SEL__DISABLE, fetchpersp9 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetcheco9_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK ((uint32_t)(0x850)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_OFFSET ((uint32_t)(0x50)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: FETCHECO9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset |
| * counter value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: FETCHECO9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: FETCHECO9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: FETCHECO9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege |
| * protection. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: FETCHECO9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetcheco9_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS ((uint32_t)(0x854)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_OFFSET ((uint32_t)(0x54)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetcheco9_Status */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS ((uint32_t)(0x858)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_OFFSET ((uint32_t)(0x58)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL_SHIFT 16U |
| /* Field Value: FETCHECO9_SEL__STORE9, fetcheco9 module is used from store9 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__STORE9 0x1U |
| /* Field Value: FETCHECO9_SEL__EXTDST0, fetcheco9 module is used from extdst0 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST0 0x2U |
| /* Field Value: FETCHECO9_SEL__EXTDST4, fetcheco9 module is used from extdst4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST4 0x3U |
| /* Field Value: FETCHECO9_SEL__EXTDST1, fetcheco9 module is used from extdst1 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST1 0x4U |
| /* Field Value: FETCHECO9_SEL__EXTDST5, fetcheco9 module is used from extdst5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST5 0x5U |
| /* Field Value: FETCHECO9_SEL__STORE4, fetcheco9 module is used from store4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__STORE4 0x6U |
| /* Field Value: FETCHECO9_SEL__STORE5, fetcheco9 module is used from store5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__STORE5 0x7U |
| /* Field Value: FETCHECO9_SEL__DISABLE, fetcheco9 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_rop9_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK ((uint32_t)(0x860)) |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_OFFSET ((uint32_t)(0x60)) |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: ROP9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset counter |
| * value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: ROP9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: ROP9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: ROP9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: ROP9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. |
| * Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_rop9_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS ((uint32_t)(0x864)) |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_OFFSET ((uint32_t)(0x64)) |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_rop9_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC ((uint32_t)(0x868)) |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_OFFSET ((uint32_t)(0x68)) |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_RESET_VALUE 0x1000000U |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL_SHIFT 0U |
| /* Field Value: ROP9_PRIM_SEL__DISABLE, Unit rop9 input port prim is disabled */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL__DISABLE 0U |
| /* Field Value: ROP9_PRIM_SEL__FETCHDECODE9, Unit rop9 input port prim is |
| * connected to output of unit fetchdecode9 */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL__FETCHDECODE9 0x1U |
| /* Field Value: ROP9_PRIM_SEL__FETCHPERSP9, Unit rop9 input port prim is connected |
| * to output of unit fetchpersp9 */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL__FETCHPERSP9 0x2U |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL_MASK 0x3F00U |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL_SHIFT 8U |
| /* Field Value: ROP9_SEC_SEL__DISABLE, Unit rop9 input port sec is disabled */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL__DISABLE 0U |
| /* Field Value: ROP9_SEC_SEL__FETCHECO9, Unit rop9 input port sec is connected |
| * to output of unit fetcheco9 */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL__FETCHECO9 0x3U |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL_MASK 0x3F0000U |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL_SHIFT 16U |
| /* Field Value: ROP9_TERT_SEL__DISABLE, Unit rop9 input port tert is disabled */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL__DISABLE 0U |
| /* Field Value: ROP9_TERT_SEL__FETCHDECODE9, Unit rop9 input port tert is |
| * connected to output of unit fetchdecode9 */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL__FETCHDECODE9 0x1U |
| /* Field Value: ROP9_TERT_SEL__FETCHPERSP9, Unit rop9 input port tert is connected |
| * to output of unit fetchpersp9 */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL__FETCHPERSP9 0x2U |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN_MASK 0x3000000U |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN_SHIFT 24U |
| /* Field Value: ROP9_CLKEN__DISABLE, Clock for rop9 is disabled */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN__DISABLE 0U |
| /* Field Value: ROP9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, frequency |
| * is defined by the register setting for this pipeline (see [endpoint_name]_Static |
| * register) */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN__AUTOMATIC 0x1U |
| /* Field Value: ROP9_CLKEN__FULL, Clock for rop9 is without gating */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN__FULL 0x3U |
| |
| /* Register: IMXDPUV1_pixengcfg_rop9_Status */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_STATUS ((uint32_t)(0x86C)) |
| #define IMXDPUV1_PIXENGCFG_ROP9_STATUS_OFFSET ((uint32_t)(0x6C)) |
| #define IMXDPUV1_PIXENGCFG_ROP9_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_ROP9_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL_SHIFT 16U |
| /* Field Value: ROP9_SEL__STORE9, rop9 module is used from store9 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__STORE9 0x1U |
| /* Field Value: ROP9_SEL__EXTDST0, rop9 module is used from extdst0 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST0 0x2U |
| /* Field Value: ROP9_SEL__EXTDST4, rop9 module is used from extdst4 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST4 0x3U |
| /* Field Value: ROP9_SEL__EXTDST1, rop9 module is used from extdst1 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST1 0x4U |
| /* Field Value: ROP9_SEL__EXTDST5, rop9 module is used from extdst5 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST5 0x5U |
| /* Field Value: ROP9_SEL__STORE4, rop9 module is used from store4 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__STORE4 0x6U |
| /* Field Value: ROP9_SEL__STORE5, rop9 module is used from store5 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__STORE5 0x7U |
| /* Field Value: ROP9_SEL__DISABLE, rop9 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_clut9_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK ((uint32_t)(0x880)) |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_OFFSET ((uint32_t)(0x80)) |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: CLUT9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset counter |
| * value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: CLUT9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: CLUT9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: CLUT9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: CLUT9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. |
| * Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_clut9_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS ((uint32_t)(0x884)) |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_OFFSET ((uint32_t)(0x84)) |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_clut9_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC ((uint32_t)(0x888)) |
| #define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_OFFSET ((uint32_t)(0x88)) |
| #define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL_SHIFT 0U |
| /* Field Value: CLUT9_SRC_SEL__DISABLE, Unit clut9 input port src is disabled */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL__DISABLE 0U |
| /* Field Value: CLUT9_SRC_SEL__BLITBLEND9, Unit clut9 input port src is connected |
| * to output of unit blitblend9 */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL__BLITBLEND9 0xAU |
| /* Field Value: CLUT9_SRC_SEL__ROP9, Unit clut9 input port src is connected |
| * to output of unit rop9 */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL__ROP9 0x4U |
| |
| /* Register: IMXDPUV1_pixengcfg_clut9_Status */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_STATUS ((uint32_t)(0x88C)) |
| #define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_OFFSET ((uint32_t)(0x8C)) |
| #define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL_SHIFT 16U |
| /* Field Value: CLUT9_SEL__STORE9, clut9 module is used from store9 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__STORE9 0x1U |
| /* Field Value: CLUT9_SEL__EXTDST0, clut9 module is used from extdst0 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST0 0x2U |
| /* Field Value: CLUT9_SEL__EXTDST4, clut9 module is used from extdst4 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST4 0x3U |
| /* Field Value: CLUT9_SEL__EXTDST1, clut9 module is used from extdst1 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST1 0x4U |
| /* Field Value: CLUT9_SEL__EXTDST5, clut9 module is used from extdst5 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST5 0x5U |
| /* Field Value: CLUT9_SEL__STORE4, clut9 module is used from store4 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__STORE4 0x6U |
| /* Field Value: CLUT9_SEL__STORE5, clut9 module is used from store5 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__STORE5 0x7U |
| /* Field Value: CLUT9_SEL__DISABLE, clut9 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_matrix9_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK ((uint32_t)(0x8A0)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_OFFSET ((uint32_t)(0xA0)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: MATRIX9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset counter |
| * value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: MATRIX9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: MATRIX9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: MATRIX9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: MATRIX9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_matrix9_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS ((uint32_t)(0x8A4)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_OFFSET ((uint32_t)(0xA4)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_matrix9_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC ((uint32_t)(0x8A8)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_OFFSET ((uint32_t)(0xA8)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_RESET_VALUE 0x1000000U |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL_SHIFT 0U |
| /* Field Value: MATRIX9_SRC_SEL__DISABLE, Unit matrix9 input port src is disabled */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__DISABLE 0U |
| /* Field Value: MATRIX9_SRC_SEL__CLUT9, Unit matrix9 input port src is connected |
| * to output of unit clut9 */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__CLUT9 0x5U |
| /* Field Value: MATRIX9_SRC_SEL__BLITBLEND9, Unit matrix9 input port src is |
| * connected to output of unit blitblend9 */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__BLITBLEND9 0xAU |
| /* Field Value: MATRIX9_SRC_SEL__ROP9, Unit matrix9 input port src is connected |
| * to output of unit rop9 */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__ROP9 0x4U |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN_MASK 0x3000000U |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN_SHIFT 24U |
| /* Field Value: MATRIX9_CLKEN__DISABLE, Clock for matrix9 is disabled */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN__DISABLE 0U |
| /* Field Value: MATRIX9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, |
| * frequency is defined by the register setting for this pipeline (see |
| * [endpoint_name]_Static register) */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN__AUTOMATIC 0x1U |
| /* Field Value: MATRIX9_CLKEN__FULL, Clock for matrix9 is without gating */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN__FULL 0x3U |
| |
| /* Register: IMXDPUV1_pixengcfg_matrix9_Status */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS ((uint32_t)(0x8AC)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_OFFSET ((uint32_t)(0xAC)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL_SHIFT 16U |
| /* Field Value: MATRIX9_SEL__STORE9, matrix9 module is used from store9 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__STORE9 0x1U |
| /* Field Value: MATRIX9_SEL__EXTDST0, matrix9 module is used from extdst0 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST0 0x2U |
| /* Field Value: MATRIX9_SEL__EXTDST4, matrix9 module is used from extdst4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST4 0x3U |
| /* Field Value: MATRIX9_SEL__EXTDST1, matrix9 module is used from extdst1 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST1 0x4U |
| /* Field Value: MATRIX9_SEL__EXTDST5, matrix9 module is used from extdst5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST5 0x5U |
| /* Field Value: MATRIX9_SEL__STORE4, matrix9 module is used from store4 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__STORE4 0x6U |
| /* Field Value: MATRIX9_SEL__STORE5, matrix9 module is used from store5 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__STORE5 0x7U |
| /* Field Value: MATRIX9_SEL__DISABLE, matrix9 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_hscaler9_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK ((uint32_t)(0x8C0)) |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_OFFSET ((uint32_t)(0xC0)) |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: HSCALER9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset counter |
| * value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: HSCALER9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: HSCALER9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: HSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: HSCALER9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_hscaler9_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS ((uint32_t)(0x8C4)) |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_OFFSET ((uint32_t)(0xC4)) |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_hscaler9_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC ((uint32_t)(0x8C8)) |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_OFFSET ((uint32_t)(0xC8)) |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_RESET_VALUE 0x1000000U |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL_SHIFT 0U |
| /* Field Value: HSCALER9_SRC_SEL__DISABLE, Unit hscaler9 input port src is |
| * disabled */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__DISABLE 0U |
| /* Field Value: HSCALER9_SRC_SEL__VSCALER9, Unit hscaler9 input port src is |
| * connected to output of unit vscaler9 */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__VSCALER9 0x8U |
| /* Field Value: HSCALER9_SRC_SEL__FILTER9, Unit hscaler9 input port src is |
| * connected to output of unit filter9 */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__FILTER9 0x9U |
| /* Field Value: HSCALER9_SRC_SEL__MATRIX9, Unit hscaler9 input port src is |
| * connected to output of unit matrix9 */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__MATRIX9 0x6U |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN_MASK 0x3000000U |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN_SHIFT 24U |
| /* Field Value: HSCALER9_CLKEN__DISABLE, Clock for hscaler9 is disabled */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN__DISABLE 0U |
| /* Field Value: HSCALER9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, |
| * frequency is defined by the register setting for this pipeline (see |
| * [endpoint_name]_Static register) */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN__AUTOMATIC 0x1U |
| /* Field Value: HSCALER9_CLKEN__FULL, Clock for hscaler9 is without gating */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN__FULL 0x3U |
| |
| /* Register: IMXDPUV1_pixengcfg_hscaler9_Status */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS ((uint32_t)(0x8CC)) |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_OFFSET ((uint32_t)(0xCC)) |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL_SHIFT 16U |
| /* Field Value: HSCALER9_SEL__STORE9, hscaler9 module is used from store9 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__STORE9 0x1U |
| /* Field Value: HSCALER9_SEL__EXTDST0, hscaler9 module is used from extdst0 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST0 0x2U |
| /* Field Value: HSCALER9_SEL__EXTDST4, hscaler9 module is used from extdst4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST4 0x3U |
| /* Field Value: HSCALER9_SEL__EXTDST1, hscaler9 module is used from extdst1 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST1 0x4U |
| /* Field Value: HSCALER9_SEL__EXTDST5, hscaler9 module is used from extdst5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST5 0x5U |
| /* Field Value: HSCALER9_SEL__STORE4, hscaler9 module is used from store4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__STORE4 0x6U |
| /* Field Value: HSCALER9_SEL__STORE5, hscaler9 module is used from store5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__STORE5 0x7U |
| /* Field Value: HSCALER9_SEL__DISABLE, hscaler9 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_vscaler9_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK ((uint32_t)(0x8E0)) |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_OFFSET ((uint32_t)(0xE0)) |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: VSCALER9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset counter |
| * value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: VSCALER9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: VSCALER9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: VSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: VSCALER9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_vscaler9_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS ((uint32_t)(0x8E4)) |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_OFFSET ((uint32_t)(0xE4)) |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_vscaler9_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC ((uint32_t)(0x8E8)) |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_OFFSET ((uint32_t)(0xE8)) |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_RESET_VALUE 0x1000000U |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL_SHIFT 0U |
| /* Field Value: VSCALER9_SRC_SEL__DISABLE, Unit vscaler9 input port src is |
| * disabled */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL__DISABLE 0U |
| /* Field Value: VSCALER9_SRC_SEL__HSCALER9, Unit vscaler9 input port src is |
| * connected to output of unit hscaler9 */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL__HSCALER9 0x7U |
| /* Field Value: VSCALER9_SRC_SEL__MATRIX9, Unit vscaler9 input port src is |
| * connected to output of unit matrix9 */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL__MATRIX9 0x6U |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN_MASK 0x3000000U |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN_SHIFT 24U |
| /* Field Value: VSCALER9_CLKEN__DISABLE, Clock for vscaler9 is disabled */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN__DISABLE 0U |
| /* Field Value: VSCALER9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, |
| * frequency is defined by the register setting for this pipeline (see |
| * [endpoint_name]_Static register) */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN__AUTOMATIC 0x1U |
| /* Field Value: VSCALER9_CLKEN__FULL, Clock for vscaler9 is without gating */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN__FULL 0x3U |
| |
| /* Register: IMXDPUV1_pixengcfg_vscaler9_Status */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS ((uint32_t)(0x8EC)) |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_OFFSET ((uint32_t)(0xEC)) |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL_SHIFT 16U |
| /* Field Value: VSCALER9_SEL__STORE9, vscaler9 module is used from store9 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__STORE9 0x1U |
| /* Field Value: VSCALER9_SEL__EXTDST0, vscaler9 module is used from extdst0 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST0 0x2U |
| /* Field Value: VSCALER9_SEL__EXTDST4, vscaler9 module is used from extdst4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST4 0x3U |
| /* Field Value: VSCALER9_SEL__EXTDST1, vscaler9 module is used from extdst1 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST1 0x4U |
| /* Field Value: VSCALER9_SEL__EXTDST5, vscaler9 module is used from extdst5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST5 0x5U |
| /* Field Value: VSCALER9_SEL__STORE4, vscaler9 module is used from store4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__STORE4 0x6U |
| /* Field Value: VSCALER9_SEL__STORE5, vscaler9 module is used from store5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__STORE5 0x7U |
| /* Field Value: VSCALER9_SEL__DISABLE, vscaler9 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_filter9_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK ((uint32_t)(0x900)) |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_OFFSET ((uint32_t)(0x100)) |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: FILTER9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset counter |
| * value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: FILTER9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: FILTER9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: FILTER9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: FILTER9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_filter9_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS ((uint32_t)(0x904)) |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_OFFSET ((uint32_t)(0x104)) |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_filter9_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC ((uint32_t)(0x908)) |
| #define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_OFFSET ((uint32_t)(0x108)) |
| #define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_RESET_VALUE 0x1000000U |
| #define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL_SHIFT 0U |
| /* Field Value: FILTER9_SRC_SEL__DISABLE, Unit filter9 input port src is disabled */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL__DISABLE 0U |
| /* Field Value: FILTER9_SRC_SEL__HSCALER9, Unit filter9 input port src is |
| * connected to output of unit hscaler9 */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL__HSCALER9 0x7U |
| /* Field Value: FILTER9_SRC_SEL__MATRIX9, Unit filter9 input port src is connected |
| * to output of unit matrix9 */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL__MATRIX9 0x6U |
| #define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN_MASK 0x3000000U |
| #define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN_SHIFT 24U |
| /* Field Value: FILTER9_CLKEN__DISABLE, Clock for filter9 is disabled */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN__DISABLE 0U |
| /* Field Value: FILTER9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, |
| * frequency is defined by the register setting for this pipeline (see |
| * [endpoint_name]_Static register) */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN__AUTOMATIC 0x1U |
| /* Field Value: FILTER9_CLKEN__FULL, Clock for filter9 is without gating */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN__FULL 0x3U |
| |
| /* Register: IMXDPUV1_pixengcfg_filter9_Status */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_STATUS ((uint32_t)(0x90C)) |
| #define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_OFFSET ((uint32_t)(0x10C)) |
| #define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL_SHIFT 16U |
| /* Field Value: FILTER9_SEL__STORE9, filter9 module is used from store9 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__STORE9 0x1U |
| /* Field Value: FILTER9_SEL__EXTDST0, filter9 module is used from extdst0 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST0 0x2U |
| /* Field Value: FILTER9_SEL__EXTDST4, filter9 module is used from extdst4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST4 0x3U |
| /* Field Value: FILTER9_SEL__EXTDST1, filter9 module is used from extdst1 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST1 0x4U |
| /* Field Value: FILTER9_SEL__EXTDST5, filter9 module is used from extdst5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST5 0x5U |
| /* Field Value: FILTER9_SEL__STORE4, filter9 module is used from store4 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__STORE4 0x6U |
| /* Field Value: FILTER9_SEL__STORE5, filter9 module is used from store5 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__STORE5 0x7U |
| /* Field Value: FILTER9_SEL__DISABLE, filter9 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_blitblend9_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK ((uint32_t)(0x920)) |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_OFFSET ((uint32_t)(0x120)) |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: BLITBLEND9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset |
| * counter value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: BLITBLEND9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: BLITBLEND9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: BLITBLEND9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege |
| * protection. */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: BLITBLEND9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_blitblend9_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS ((uint32_t)(0x924)) |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_OFFSET ((uint32_t)(0x124)) |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_blitblend9_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC ((uint32_t)(0x928)) |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_OFFSET ((uint32_t)(0x128)) |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_RESET_VALUE 0x1000000U |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL_SHIFT 0U |
| /* Field Value: BLITBLEND9_PRIM_SEL__DISABLE, Unit blitblend9 input port prim |
| * is disabled */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__DISABLE 0U |
| /* Field Value: BLITBLEND9_PRIM_SEL__HSCALER9, Unit blitblend9 input port |
| * prim is connected to output of unit hscaler9 */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__HSCALER9 0x7U |
| /* Field Value: BLITBLEND9_PRIM_SEL__VSCALER9, Unit blitblend9 input port |
| * prim is connected to output of unit vscaler9 */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__VSCALER9 0x8U |
| /* Field Value: BLITBLEND9_PRIM_SEL__FILTER9, Unit blitblend9 input port prim |
| * is connected to output of unit filter9 */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__FILTER9 0x9U |
| /* Field Value: BLITBLEND9_PRIM_SEL__ROP9, Unit blitblend9 input port prim |
| * is connected to output of unit rop9 */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__ROP9 0x4U |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL_MASK 0x3F00U |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL_SHIFT 8U |
| /* Field Value: BLITBLEND9_SEC_SEL__DISABLE, Unit blitblend9 input port sec |
| * is disabled */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL__DISABLE 0U |
| /* Field Value: BLITBLEND9_SEC_SEL__FETCHDECODE9, Unit blitblend9 input port |
| * sec is connected to output of unit fetchdecode9 */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL__FETCHDECODE9 0x1U |
| /* Field Value: BLITBLEND9_SEC_SEL__FETCHPERSP9, Unit blitblend9 input port |
| * sec is connected to output of unit fetchpersp9 */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL__FETCHPERSP9 0x2U |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN_MASK 0x3000000U |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN_SHIFT 24U |
| /* Field Value: BLITBLEND9_CLKEN__DISABLE, Clock for blitblend9 is disabled */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN__DISABLE 0U |
| /* Field Value: BLITBLEND9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, |
| * frequency is defined by the register setting for this pipeline (see |
| * [endpoint_name]_Static register) */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN__AUTOMATIC 0x1U |
| /* Field Value: BLITBLEND9_CLKEN__FULL, Clock for blitblend9 is without gating */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN__FULL 0x3U |
| |
| /* Register: IMXDPUV1_pixengcfg_blitblend9_Status */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS ((uint32_t)(0x92C)) |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_OFFSET ((uint32_t)(0x12C)) |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL_SHIFT 16U |
| /* Field Value: BLITBLEND9_SEL__STORE9, blitblend9 module is used from store9 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__STORE9 0x1U |
| /* Field Value: BLITBLEND9_SEL__EXTDST0, blitblend9 module is used from extdst0 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST0 0x2U |
| /* Field Value: BLITBLEND9_SEL__EXTDST4, blitblend9 module is used from extdst4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST4 0x3U |
| /* Field Value: BLITBLEND9_SEL__EXTDST1, blitblend9 module is used from extdst1 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST1 0x4U |
| /* Field Value: BLITBLEND9_SEL__EXTDST5, blitblend9 module is used from extdst5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST5 0x5U |
| /* Field Value: BLITBLEND9_SEL__STORE4, blitblend9 module is used from store4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__STORE4 0x6U |
| /* Field Value: BLITBLEND9_SEL__STORE5, blitblend9 module is used from store5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__STORE5 0x7U |
| /* Field Value: BLITBLEND9_SEL__DISABLE, blitblend9 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_store9_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK ((uint32_t)(0x940)) |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_OFFSET ((uint32_t)(0x140)) |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: STORE9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset counter |
| * value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: STORE9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: STORE9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: STORE9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: STORE9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_store9_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS ((uint32_t)(0x944)) |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_OFFSET ((uint32_t)(0x144)) |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_store9_Static */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATIC ((uint32_t)(0x948)) |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATIC_OFFSET ((uint32_t)(0x148)) |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATIC_RESET_VALUE 0x800010U |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SHDEN_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SHDEN_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_POWERDOWN_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_POWERDOWN_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE_SHIFT 8U |
| /* Field Value: STORE9_SYNC_MODE__SINGLE, Reconfig pipeline after explicit |
| * trigger */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE__SINGLE 0U |
| /* Field Value: STORE9_SYNC_MODE__AUTO, Reconfig pipeline after every kick |
| * when idle */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE__AUTO 0x1U |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET_MASK 0x800U |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET_SHIFT 11U |
| /* Field Value: STORE9_SW_RESET__OPERATION, Normal Operation */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET__OPERATION 0U |
| /* Field Value: STORE9_SW_RESET__SWRESET, Software Reset */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET__SWRESET 0x1U |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_DIV_MASK 0xFF0000U |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_DIV_SHIFT 16U |
| |
| /* Register: IMXDPUV1_pixengcfg_store9_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC ((uint32_t)(0x94C)) |
| #define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_OFFSET ((uint32_t)(0x14C)) |
| #define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_RESET_VALUE 0x1U |
| #define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL_SHIFT 0U |
| /* Field Value: STORE9_SRC_SEL__DISABLE, Unit store9 input port src is disabled */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__DISABLE 0U |
| /* Field Value: STORE9_SRC_SEL__HSCALER9, Unit store9 input port src is connected |
| * to output of unit hscaler9 */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__HSCALER9 0x7U |
| /* Field Value: STORE9_SRC_SEL__VSCALER9, Unit store9 input port src is connected |
| * to output of unit vscaler9 */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__VSCALER9 0x8U |
| /* Field Value: STORE9_SRC_SEL__FILTER9, Unit store9 input port src is connected |
| * to output of unit filter9 */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__FILTER9 0x9U |
| /* Field Value: STORE9_SRC_SEL__BLITBLEND9, Unit store9 input port src is |
| * connected to output of unit blitblend9 */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__BLITBLEND9 0xAU |
| /* Field Value: STORE9_SRC_SEL__FETCHDECODE9, Unit store9 input port src is |
| * connected to output of unit fetchdecode9 */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__FETCHDECODE9 0x1U |
| /* Field Value: STORE9_SRC_SEL__FETCHPERSP9, Unit store9 input port src is |
| * connected to output of unit fetchpersp9 */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__FETCHPERSP9 0x2U |
| |
| /* Register: IMXDPUV1_pixengcfg_store9_Request */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_REQUEST ((uint32_t)(0x950)) |
| #define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_OFFSET ((uint32_t)(0x150)) |
| #define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SEL_SHDLDREQ_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SEL_SHDLDREQ_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SHDLDREQ_MASK 0x3FFFFEU |
| #define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SHDLDREQ_SHIFT 1U |
| |
| /* Register: IMXDPUV1_pixengcfg_store9_Trigger */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER ((uint32_t)(0x954)) |
| #define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_OFFSET ((uint32_t)(0x154)) |
| #define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_RESET_MASK 0xFFFFFFEEU |
| #define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_SYNC_TRIGGER_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_SYNC_TRIGGER_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U |
| |
| /* Register: IMXDPUV1_pixengcfg_store9_Status */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATUS ((uint32_t)(0x958)) |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATUS_OFFSET ((uint32_t)(0x158)) |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS_MASK 0x3U |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS_SHIFT 0U |
| /* Field Value: STORE9_PIPELINE_STATUS__EMPTY, Pipeline with endpoint store9 |
| * is empty */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__EMPTY 0U |
| /* Field Value: STORE9_PIPELINE_STATUS__RUNNING, Pipeline with endpoint store9 |
| * is currently processing one operation */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__RUNNING 0x1U |
| /* Field Value: STORE9_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with |
| * endpoint store9 is currently processing one operation with a second one |
| * already kicked to be processed afterwards */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U |
| /* Field Value: STORE9_PIPELINE_STATUS__RESERVED, reserved */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__RESERVED 0x3U |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY_SHIFT 8U |
| /* Field Value: STORE9_SYNC_BUSY__IDLE, store9 synchronizer is idle */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY__IDLE 0U |
| /* Field Value: STORE9_SYNC_BUSY__BUSY, store9 synchronizer is busy */ |
| #define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY__BUSY 0x1U |
| |
| /* Register: IMXDPUV1_pixengcfg_constframe0_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK ((uint32_t)(0x960)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_OFFSET ((uint32_t)(0x160)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: CONSTFRAME0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset |
| * counter value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: CONSTFRAME0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock |
| * counter. Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: CONSTFRAME0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: CONSTFRAME0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege |
| * protection. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: CONSTFRAME0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_constframe0_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS ((uint32_t)(0x964)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_OFFSET ((uint32_t)(0x164)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_constframe0_Status */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS ((uint32_t)(0x968)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_OFFSET ((uint32_t)(0x168)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL_SHIFT 16U |
| /* Field Value: CONSTFRAME0_SEL__STORE9, constframe0 module is used from store9 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__STORE9 0x1U |
| /* Field Value: CONSTFRAME0_SEL__EXTDST0, constframe0 module is used from |
| * extdst0 processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST0 0x2U |
| /* Field Value: CONSTFRAME0_SEL__EXTDST4, constframe0 module is used from |
| * extdst4 processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST4 0x3U |
| /* Field Value: CONSTFRAME0_SEL__EXTDST1, constframe0 module is used from |
| * extdst1 processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST1 0x4U |
| /* Field Value: CONSTFRAME0_SEL__EXTDST5, constframe0 module is used from |
| * extdst5 processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST5 0x5U |
| /* Field Value: CONSTFRAME0_SEL__STORE4, constframe0 module is used from store4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__STORE4 0x6U |
| /* Field Value: CONSTFRAME0_SEL__STORE5, constframe0 module is used from store5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__STORE5 0x7U |
| /* Field Value: CONSTFRAME0_SEL__DISABLE, constframe0 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst0_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK ((uint32_t)(0x980)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_OFFSET ((uint32_t)(0x180)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: EXTDST0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset counter |
| * value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: EXTDST0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: EXTDST0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: EXTDST0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: EXTDST0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst0_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS ((uint32_t)(0x984)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_OFFSET ((uint32_t)(0x184)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst0_Static */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC ((uint32_t)(0x988)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_OFFSET ((uint32_t)(0x188)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_RESET_VALUE 0x800010U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SHDEN_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SHDEN_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_POWERDOWN_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_POWERDOWN_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE_SHIFT 8U |
| /* Field Value: EXTDST0_SYNC_MODE__SINGLE, Reconfig pipeline after explicit |
| * trigger */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE__SINGLE 0U |
| /* Field Value: EXTDST0_SYNC_MODE__AUTO, Reconfig pipeline after every kick |
| * when idle */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE__AUTO 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET_MASK 0x800U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET_SHIFT 11U |
| /* Field Value: EXTDST0_SW_RESET__OPERATION, Normal Operation */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET__OPERATION 0U |
| /* Field Value: EXTDST0_SW_RESET__SWRESET, Software Reset */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET__SWRESET 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_DIV_MASK 0xFF0000U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_DIV_SHIFT 16U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst0_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC ((uint32_t)(0x98C)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_OFFSET ((uint32_t)(0x18C)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_RESET_VALUE 0x2CU |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL_SHIFT 0U |
| /* Field Value: EXTDST0_SRC_SEL__DISABLE, Unit extdst0 input port src is disabled */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__DISABLE 0U |
| /* Field Value: EXTDST0_SRC_SEL__BLITBLEND9, Unit extdst0 input port src is |
| * connected to output of unit blitblend9 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__BLITBLEND9 0xAU |
| /* Field Value: EXTDST0_SRC_SEL__CONSTFRAME0, Unit extdst0 input port src |
| * is connected to output of unit constframe0 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME0 0xCU |
| /* Field Value: EXTDST0_SRC_SEL__CONSTFRAME1, Unit extdst0 input port src |
| * is connected to output of unit constframe1 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME1 0x10U |
| /* Field Value: EXTDST0_SRC_SEL__CONSTFRAME4, Unit extdst0 input port src |
| * is connected to output of unit constframe4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME4 0xEU |
| /* Field Value: EXTDST0_SRC_SEL__CONSTFRAME5, Unit extdst0 input port src |
| * is connected to output of unit constframe5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME5 0x12U |
| /* Field Value: EXTDST0_SRC_SEL__MATRIX4, Unit extdst0 input port src is connected |
| * to output of unit matrix4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__MATRIX4 0x23U |
| /* Field Value: EXTDST0_SRC_SEL__HSCALER4, Unit extdst0 input port src is |
| * connected to output of unit hscaler4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__HSCALER4 0x24U |
| /* Field Value: EXTDST0_SRC_SEL__VSCALER4, Unit extdst0 input port src is |
| * connected to output of unit vscaler4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__VSCALER4 0x25U |
| /* Field Value: EXTDST0_SRC_SEL__EXTSRC4, Unit extdst0 input port src is connected |
| * to output of unit extsrc4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__EXTSRC4 0x14U |
| /* Field Value: EXTDST0_SRC_SEL__MATRIX5, Unit extdst0 input port src is connected |
| * to output of unit matrix5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__MATRIX5 0x28U |
| /* Field Value: EXTDST0_SRC_SEL__HSCALER5, Unit extdst0 input port src is |
| * connected to output of unit hscaler5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__HSCALER5 0x29U |
| /* Field Value: EXTDST0_SRC_SEL__VSCALER5, Unit extdst0 input port src is |
| * connected to output of unit vscaler5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__VSCALER5 0x2AU |
| /* Field Value: EXTDST0_SRC_SEL__EXTSRC5, Unit extdst0 input port src is connected |
| * to output of unit extsrc5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__EXTSRC5 0x16U |
| /* Field Value: EXTDST0_SRC_SEL__LAYERBLEND6, Unit extdst0 input port src |
| * is connected to output of unit layerblend6 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND6 0x32U |
| /* Field Value: EXTDST0_SRC_SEL__LAYERBLEND5, Unit extdst0 input port src |
| * is connected to output of unit layerblend5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND5 0x31U |
| /* Field Value: EXTDST0_SRC_SEL__LAYERBLEND4, Unit extdst0 input port src |
| * is connected to output of unit layerblend4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND4 0x30U |
| /* Field Value: EXTDST0_SRC_SEL__LAYERBLEND3, Unit extdst0 input port src |
| * is connected to output of unit layerblend3 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND3 0x2FU |
| /* Field Value: EXTDST0_SRC_SEL__LAYERBLEND2, Unit extdst0 input port src |
| * is connected to output of unit layerblend2 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND2 0x2EU |
| /* Field Value: EXTDST0_SRC_SEL__LAYERBLEND1, Unit extdst0 input port src |
| * is connected to output of unit layerblend1 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND1 0x2DU |
| /* Field Value: EXTDST0_SRC_SEL__LAYERBLEND0, Unit extdst0 input port src |
| * is connected to output of unit layerblend0 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND0 0x2CU |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst0_Request */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST ((uint32_t)(0x990)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_OFFSET ((uint32_t)(0x190)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SEL_SHDLDREQ_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SEL_SHDLDREQ_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SHDLDREQ_MASK 0x3FFFFEU |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SHDLDREQ_SHIFT 1U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst0_Trigger */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER ((uint32_t)(0x994)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_OFFSET ((uint32_t)(0x194)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_RESET_MASK 0xFFFFFFEEU |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_SYNC_TRIGGER_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_SYNC_TRIGGER_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst0_Status */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS ((uint32_t)(0x998)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_OFFSET ((uint32_t)(0x198)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS_MASK 0x3U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS_SHIFT 0U |
| /* Field Value: EXTDST0_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst0 |
| * is empty */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__EMPTY 0U |
| /* Field Value: EXTDST0_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst0 |
| * is currently processing one operation */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__RUNNING 0x1U |
| /* Field Value: EXTDST0_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with |
| * endpoint extdst0 is currently processing one operation with a second |
| * one already kicked to be processed afterwards */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U |
| /* Field Value: EXTDST0_PIPELINE_STATUS__RESERVED, reserved */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__RESERVED 0x3U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY_SHIFT 8U |
| /* Field Value: EXTDST0_SYNC_BUSY__IDLE, extdst0 synchronizer is idle */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY__IDLE 0U |
| /* Field Value: EXTDST0_SYNC_BUSY__BUSY, extdst0 synchronizer is busy */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY__BUSY 0x1U |
| |
| /* Register: IMXDPUV1_pixengcfg_constframe4_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK ((uint32_t)(0x9A0)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_OFFSET ((uint32_t)(0x1A0)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: CONSTFRAME4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset |
| * counter value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: CONSTFRAME4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock |
| * counter. Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: CONSTFRAME4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: CONSTFRAME4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege |
| * protection. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: CONSTFRAME4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_constframe4_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS ((uint32_t)(0x9A4)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_OFFSET ((uint32_t)(0x1A4)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_constframe4_Status */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS ((uint32_t)(0x9A8)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_OFFSET ((uint32_t)(0x1A8)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL_SHIFT 16U |
| /* Field Value: CONSTFRAME4_SEL__STORE9, constframe4 module is used from store9 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__STORE9 0x1U |
| /* Field Value: CONSTFRAME4_SEL__EXTDST0, constframe4 module is used from |
| * extdst0 processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST0 0x2U |
| /* Field Value: CONSTFRAME4_SEL__EXTDST4, constframe4 module is used from |
| * extdst4 processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST4 0x3U |
| /* Field Value: CONSTFRAME4_SEL__EXTDST1, constframe4 module is used from |
| * extdst1 processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST1 0x4U |
| /* Field Value: CONSTFRAME4_SEL__EXTDST5, constframe4 module is used from |
| * extdst5 processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST5 0x5U |
| /* Field Value: CONSTFRAME4_SEL__STORE4, constframe4 module is used from store4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__STORE4 0x6U |
| /* Field Value: CONSTFRAME4_SEL__STORE5, constframe4 module is used from store5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__STORE5 0x7U |
| /* Field Value: CONSTFRAME4_SEL__DISABLE, constframe4 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst4_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK ((uint32_t)(0x9C0)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_OFFSET ((uint32_t)(0x1C0)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: EXTDST4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset counter |
| * value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: EXTDST4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: EXTDST4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: EXTDST4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: EXTDST4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst4_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS ((uint32_t)(0x9C4)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_OFFSET ((uint32_t)(0x1C4)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst4_Static */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC ((uint32_t)(0x9C8)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_OFFSET ((uint32_t)(0x1C8)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_RESET_VALUE 0x800010U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SHDEN_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SHDEN_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_POWERDOWN_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_POWERDOWN_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE_SHIFT 8U |
| /* Field Value: EXTDST4_SYNC_MODE__SINGLE, Reconfig pipeline after explicit |
| * trigger */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE__SINGLE 0U |
| /* Field Value: EXTDST4_SYNC_MODE__AUTO, Reconfig pipeline after every kick |
| * when idle */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE__AUTO 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET_MASK 0x800U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET_SHIFT 11U |
| /* Field Value: EXTDST4_SW_RESET__OPERATION, Normal Operation */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET__OPERATION 0U |
| /* Field Value: EXTDST4_SW_RESET__SWRESET, Software Reset */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET__SWRESET 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_DIV_MASK 0xFF0000U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_DIV_SHIFT 16U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst4_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC ((uint32_t)(0x9CC)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_OFFSET ((uint32_t)(0x1CC)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_RESET_VALUE 0x30U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL_SHIFT 0U |
| /* Field Value: EXTDST4_SRC_SEL__DISABLE, Unit extdst4 input port src is disabled */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__DISABLE 0U |
| /* Field Value: EXTDST4_SRC_SEL__BLITBLEND9, Unit extdst4 input port src is |
| * connected to output of unit blitblend9 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__BLITBLEND9 0xAU |
| /* Field Value: EXTDST4_SRC_SEL__CONSTFRAME0, Unit extdst4 input port src |
| * is connected to output of unit constframe0 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME0 0xCU |
| /* Field Value: EXTDST4_SRC_SEL__CONSTFRAME1, Unit extdst4 input port src |
| * is connected to output of unit constframe1 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME1 0x10U |
| /* Field Value: EXTDST4_SRC_SEL__CONSTFRAME4, Unit extdst4 input port src |
| * is connected to output of unit constframe4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME4 0xEU |
| /* Field Value: EXTDST4_SRC_SEL__CONSTFRAME5, Unit extdst4 input port src |
| * is connected to output of unit constframe5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME5 0x12U |
| /* Field Value: EXTDST4_SRC_SEL__MATRIX4, Unit extdst4 input port src is connected |
| * to output of unit matrix4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__MATRIX4 0x23U |
| /* Field Value: EXTDST4_SRC_SEL__HSCALER4, Unit extdst4 input port src is |
| * connected to output of unit hscaler4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__HSCALER4 0x24U |
| /* Field Value: EXTDST4_SRC_SEL__VSCALER4, Unit extdst4 input port src is |
| * connected to output of unit vscaler4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__VSCALER4 0x25U |
| /* Field Value: EXTDST4_SRC_SEL__MATRIX5, Unit extdst4 input port src is connected |
| * to output of unit matrix5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__MATRIX5 0x28U |
| /* Field Value: EXTDST4_SRC_SEL__HSCALER5, Unit extdst4 input port src is |
| * connected to output of unit hscaler5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__HSCALER5 0x29U |
| /* Field Value: EXTDST4_SRC_SEL__VSCALER5, Unit extdst4 input port src is |
| * connected to output of unit vscaler5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__VSCALER5 0x2AU |
| /* Field Value: EXTDST4_SRC_SEL__LAYERBLEND6, Unit extdst4 input port src |
| * is connected to output of unit layerblend6 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND6 0x32U |
| /* Field Value: EXTDST4_SRC_SEL__LAYERBLEND5, Unit extdst4 input port src |
| * is connected to output of unit layerblend5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND5 0x31U |
| /* Field Value: EXTDST4_SRC_SEL__LAYERBLEND4, Unit extdst4 input port src |
| * is connected to output of unit layerblend4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND4 0x30U |
| /* Field Value: EXTDST4_SRC_SEL__LAYERBLEND3, Unit extdst4 input port src |
| * is connected to output of unit layerblend3 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND3 0x2FU |
| /* Field Value: EXTDST4_SRC_SEL__LAYERBLEND2, Unit extdst4 input port src |
| * is connected to output of unit layerblend2 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND2 0x2EU |
| /* Field Value: EXTDST4_SRC_SEL__LAYERBLEND1, Unit extdst4 input port src |
| * is connected to output of unit layerblend1 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND1 0x2DU |
| /* Field Value: EXTDST4_SRC_SEL__LAYERBLEND0, Unit extdst4 input port src |
| * is connected to output of unit layerblend0 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND0 0x2CU |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst4_Request */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST ((uint32_t)(0x9D0)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_OFFSET ((uint32_t)(0x1D0)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SEL_SHDLDREQ_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SEL_SHDLDREQ_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SHDLDREQ_MASK 0x3FFFFEU |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SHDLDREQ_SHIFT 1U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst4_Trigger */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER ((uint32_t)(0x9D4)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_OFFSET ((uint32_t)(0x1D4)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_RESET_MASK 0xFFFFFFEEU |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_SYNC_TRIGGER_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_SYNC_TRIGGER_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst4_Status */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS ((uint32_t)(0x9D8)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_OFFSET ((uint32_t)(0x1D8)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS_MASK 0x3U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS_SHIFT 0U |
| /* Field Value: EXTDST4_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst4 |
| * is empty */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__EMPTY 0U |
| /* Field Value: EXTDST4_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst4 |
| * is currently processing one operation */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__RUNNING 0x1U |
| /* Field Value: EXTDST4_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with |
| * endpoint extdst4 is currently processing one operation with a second |
| * one already kicked to be processed afterwards */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U |
| /* Field Value: EXTDST4_PIPELINE_STATUS__RESERVED, reserved */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__RESERVED 0x3U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY_SHIFT 8U |
| /* Field Value: EXTDST4_SYNC_BUSY__IDLE, extdst4 synchronizer is idle */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY__IDLE 0U |
| /* Field Value: EXTDST4_SYNC_BUSY__BUSY, extdst4 synchronizer is busy */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY__BUSY 0x1U |
| |
| /* Register: IMXDPUV1_pixengcfg_constframe1_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK ((uint32_t)(0x9E0)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_OFFSET ((uint32_t)(0x1E0)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: CONSTFRAME1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset |
| * counter value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: CONSTFRAME1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock |
| * counter. Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: CONSTFRAME1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: CONSTFRAME1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege |
| * protection. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: CONSTFRAME1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_constframe1_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS ((uint32_t)(0x9E4)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_OFFSET ((uint32_t)(0x1E4)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_constframe1_Status */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS ((uint32_t)(0x9E8)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_OFFSET ((uint32_t)(0x1E8)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL_SHIFT 16U |
| /* Field Value: CONSTFRAME1_SEL__STORE9, constframe1 module is used from store9 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__STORE9 0x1U |
| /* Field Value: CONSTFRAME1_SEL__EXTDST0, constframe1 module is used from |
| * extdst0 processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST0 0x2U |
| /* Field Value: CONSTFRAME1_SEL__EXTDST4, constframe1 module is used from |
| * extdst4 processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST4 0x3U |
| /* Field Value: CONSTFRAME1_SEL__EXTDST1, constframe1 module is used from |
| * extdst1 processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST1 0x4U |
| /* Field Value: CONSTFRAME1_SEL__EXTDST5, constframe1 module is used from |
| * extdst5 processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST5 0x5U |
| /* Field Value: CONSTFRAME1_SEL__STORE4, constframe1 module is used from store4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__STORE4 0x6U |
| /* Field Value: CONSTFRAME1_SEL__STORE5, constframe1 module is used from store5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__STORE5 0x7U |
| /* Field Value: CONSTFRAME1_SEL__DISABLE, constframe1 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst1_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK ((uint32_t)(0xA00)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_OFFSET ((uint32_t)(0x200)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: EXTDST1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset counter |
| * value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: EXTDST1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: EXTDST1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: EXTDST1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: EXTDST1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst1_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS ((uint32_t)(0xA04)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_OFFSET ((uint32_t)(0x204)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst1_Static */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC ((uint32_t)(0xA08)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_OFFSET ((uint32_t)(0x208)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_RESET_VALUE 0x800010U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SHDEN_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SHDEN_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_POWERDOWN_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_POWERDOWN_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE_SHIFT 8U |
| /* Field Value: EXTDST1_SYNC_MODE__SINGLE, Reconfig pipeline after explicit |
| * trigger */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE__SINGLE 0U |
| /* Field Value: EXTDST1_SYNC_MODE__AUTO, Reconfig pipeline after every kick |
| * when idle */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE__AUTO 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET_MASK 0x800U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET_SHIFT 11U |
| /* Field Value: EXTDST1_SW_RESET__OPERATION, Normal Operation */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET__OPERATION 0U |
| /* Field Value: EXTDST1_SW_RESET__SWRESET, Software Reset */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET__SWRESET 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_DIV_MASK 0xFF0000U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_DIV_SHIFT 16U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst1_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC ((uint32_t)(0xA0C)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_OFFSET ((uint32_t)(0x20C)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_RESET_VALUE 0x2DU |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL_SHIFT 0U |
| /* Field Value: EXTDST1_SRC_SEL__DISABLE, Unit extdst1 input port src is disabled */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__DISABLE 0U |
| /* Field Value: EXTDST1_SRC_SEL__BLITBLEND9, Unit extdst1 input port src is |
| * connected to output of unit blitblend9 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__BLITBLEND9 0xAU |
| /* Field Value: EXTDST1_SRC_SEL__CONSTFRAME0, Unit extdst1 input port src |
| * is connected to output of unit constframe0 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME0 0xCU |
| /* Field Value: EXTDST1_SRC_SEL__CONSTFRAME1, Unit extdst1 input port src |
| * is connected to output of unit constframe1 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME1 0x10U |
| /* Field Value: EXTDST1_SRC_SEL__CONSTFRAME4, Unit extdst1 input port src |
| * is connected to output of unit constframe4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME4 0xEU |
| /* Field Value: EXTDST1_SRC_SEL__CONSTFRAME5, Unit extdst1 input port src |
| * is connected to output of unit constframe5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME5 0x12U |
| /* Field Value: EXTDST1_SRC_SEL__MATRIX4, Unit extdst1 input port src is connected |
| * to output of unit matrix4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__MATRIX4 0x23U |
| /* Field Value: EXTDST1_SRC_SEL__HSCALER4, Unit extdst1 input port src is |
| * connected to output of unit hscaler4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__HSCALER4 0x24U |
| /* Field Value: EXTDST1_SRC_SEL__VSCALER4, Unit extdst1 input port src is |
| * connected to output of unit vscaler4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__VSCALER4 0x25U |
| /* Field Value: EXTDST1_SRC_SEL__EXTSRC4, Unit extdst1 input port src is connected |
| * to output of unit extsrc4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__EXTSRC4 0x14U |
| /* Field Value: EXTDST1_SRC_SEL__MATRIX5, Unit extdst1 input port src is connected |
| * to output of unit matrix5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__MATRIX5 0x28U |
| /* Field Value: EXTDST1_SRC_SEL__HSCALER5, Unit extdst1 input port src is |
| * connected to output of unit hscaler5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__HSCALER5 0x29U |
| /* Field Value: EXTDST1_SRC_SEL__VSCALER5, Unit extdst1 input port src is |
| * connected to output of unit vscaler5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__VSCALER5 0x2AU |
| /* Field Value: EXTDST1_SRC_SEL__EXTSRC5, Unit extdst1 input port src is connected |
| * to output of unit extsrc5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__EXTSRC5 0x16U |
| /* Field Value: EXTDST1_SRC_SEL__LAYERBLEND6, Unit extdst1 input port src |
| * is connected to output of unit layerblend6 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND6 0x32U |
| /* Field Value: EXTDST1_SRC_SEL__LAYERBLEND5, Unit extdst1 input port src |
| * is connected to output of unit layerblend5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND5 0x31U |
| /* Field Value: EXTDST1_SRC_SEL__LAYERBLEND4, Unit extdst1 input port src |
| * is connected to output of unit layerblend4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND4 0x30U |
| /* Field Value: EXTDST1_SRC_SEL__LAYERBLEND3, Unit extdst1 input port src |
| * is connected to output of unit layerblend3 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND3 0x2FU |
| /* Field Value: EXTDST1_SRC_SEL__LAYERBLEND2, Unit extdst1 input port src |
| * is connected to output of unit layerblend2 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND2 0x2EU |
| /* Field Value: EXTDST1_SRC_SEL__LAYERBLEND1, Unit extdst1 input port src |
| * is connected to output of unit layerblend1 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND1 0x2DU |
| /* Field Value: EXTDST1_SRC_SEL__LAYERBLEND0, Unit extdst1 input port src |
| * is connected to output of unit layerblend0 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND0 0x2CU |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst1_Request */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST ((uint32_t)(0xA10)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_OFFSET ((uint32_t)(0x210)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SEL_SHDLDREQ_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SEL_SHDLDREQ_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SHDLDREQ_MASK 0x3FFFFEU |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SHDLDREQ_SHIFT 1U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst1_Trigger */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER ((uint32_t)(0xA14)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_OFFSET ((uint32_t)(0x214)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_RESET_MASK 0xFFFFFFEEU |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_SYNC_TRIGGER_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_SYNC_TRIGGER_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst1_Status */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS ((uint32_t)(0xA18)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_OFFSET ((uint32_t)(0x218)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS_MASK 0x3U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS_SHIFT 0U |
| /* Field Value: EXTDST1_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst1 |
| * is empty */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__EMPTY 0U |
| /* Field Value: EXTDST1_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst1 |
| * is currently processing one operation */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__RUNNING 0x1U |
| /* Field Value: EXTDST1_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with |
| * endpoint extdst1 is currently processing one operation with a second |
| * one already kicked to be processed afterwards */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U |
| /* Field Value: EXTDST1_PIPELINE_STATUS__RESERVED, reserved */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__RESERVED 0x3U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY_SHIFT 8U |
| /* Field Value: EXTDST1_SYNC_BUSY__IDLE, extdst1 synchronizer is idle */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY__IDLE 0U |
| /* Field Value: EXTDST1_SYNC_BUSY__BUSY, extdst1 synchronizer is busy */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY__BUSY 0x1U |
| |
| /* Register: IMXDPUV1_pixengcfg_constframe5_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK ((uint32_t)(0xA20)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_OFFSET ((uint32_t)(0x220)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: CONSTFRAME5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset |
| * counter value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: CONSTFRAME5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock |
| * counter. Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: CONSTFRAME5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: CONSTFRAME5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege |
| * protection. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: CONSTFRAME5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_constframe5_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS ((uint32_t)(0xA24)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_OFFSET ((uint32_t)(0x224)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_constframe5_Status */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS ((uint32_t)(0xA28)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_OFFSET ((uint32_t)(0x228)) |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL_SHIFT 16U |
| /* Field Value: CONSTFRAME5_SEL__STORE9, constframe5 module is used from store9 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__STORE9 0x1U |
| /* Field Value: CONSTFRAME5_SEL__EXTDST0, constframe5 module is used from |
| * extdst0 processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST0 0x2U |
| /* Field Value: CONSTFRAME5_SEL__EXTDST4, constframe5 module is used from |
| * extdst4 processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST4 0x3U |
| /* Field Value: CONSTFRAME5_SEL__EXTDST1, constframe5 module is used from |
| * extdst1 processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST1 0x4U |
| /* Field Value: CONSTFRAME5_SEL__EXTDST5, constframe5 module is used from |
| * extdst5 processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST5 0x5U |
| /* Field Value: CONSTFRAME5_SEL__STORE4, constframe5 module is used from store4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__STORE4 0x6U |
| /* Field Value: CONSTFRAME5_SEL__STORE5, constframe5 module is used from store5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__STORE5 0x7U |
| /* Field Value: CONSTFRAME5_SEL__DISABLE, constframe5 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst5_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK ((uint32_t)(0xA40)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_OFFSET ((uint32_t)(0x240)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: EXTDST5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset counter |
| * value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: EXTDST5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: EXTDST5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: EXTDST5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: EXTDST5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst5_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS ((uint32_t)(0xA44)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_OFFSET ((uint32_t)(0x244)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst5_Static */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC ((uint32_t)(0xA48)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_OFFSET ((uint32_t)(0x248)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_RESET_VALUE 0x800010U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SHDEN_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SHDEN_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_POWERDOWN_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_POWERDOWN_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE_SHIFT 8U |
| /* Field Value: EXTDST5_SYNC_MODE__SINGLE, Reconfig pipeline after explicit |
| * trigger */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE__SINGLE 0U |
| /* Field Value: EXTDST5_SYNC_MODE__AUTO, Reconfig pipeline after every kick |
| * when idle */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE__AUTO 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET_MASK 0x800U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET_SHIFT 11U |
| /* Field Value: EXTDST5_SW_RESET__OPERATION, Normal Operation */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET__OPERATION 0U |
| /* Field Value: EXTDST5_SW_RESET__SWRESET, Software Reset */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET__SWRESET 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_DIV_MASK 0xFF0000U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_DIV_SHIFT 16U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst5_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC ((uint32_t)(0xA4C)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_OFFSET ((uint32_t)(0x24C)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_RESET_VALUE 0x31U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL_SHIFT 0U |
| /* Field Value: EXTDST5_SRC_SEL__DISABLE, Unit extdst5 input port src is disabled */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__DISABLE 0U |
| /* Field Value: EXTDST5_SRC_SEL__BLITBLEND9, Unit extdst5 input port src is |
| * connected to output of unit blitblend9 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__BLITBLEND9 0xAU |
| /* Field Value: EXTDST5_SRC_SEL__CONSTFRAME0, Unit extdst5 input port src |
| * is connected to output of unit constframe0 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME0 0xCU |
| /* Field Value: EXTDST5_SRC_SEL__CONSTFRAME1, Unit extdst5 input port src |
| * is connected to output of unit constframe1 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME1 0x10U |
| /* Field Value: EXTDST5_SRC_SEL__CONSTFRAME4, Unit extdst5 input port src |
| * is connected to output of unit constframe4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME4 0xEU |
| /* Field Value: EXTDST5_SRC_SEL__CONSTFRAME5, Unit extdst5 input port src |
| * is connected to output of unit constframe5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME5 0x12U |
| /* Field Value: EXTDST5_SRC_SEL__MATRIX4, Unit extdst5 input port src is connected |
| * to output of unit matrix4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__MATRIX4 0x23U |
| /* Field Value: EXTDST5_SRC_SEL__HSCALER4, Unit extdst5 input port src is |
| * connected to output of unit hscaler4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__HSCALER4 0x24U |
| /* Field Value: EXTDST5_SRC_SEL__VSCALER4, Unit extdst5 input port src is |
| * connected to output of unit vscaler4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__VSCALER4 0x25U |
| /* Field Value: EXTDST5_SRC_SEL__MATRIX5, Unit extdst5 input port src is connected |
| * to output of unit matrix5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__MATRIX5 0x28U |
| /* Field Value: EXTDST5_SRC_SEL__HSCALER5, Unit extdst5 input port src is |
| * connected to output of unit hscaler5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__HSCALER5 0x29U |
| /* Field Value: EXTDST5_SRC_SEL__VSCALER5, Unit extdst5 input port src is |
| * connected to output of unit vscaler5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__VSCALER5 0x2AU |
| /* Field Value: EXTDST5_SRC_SEL__LAYERBLEND6, Unit extdst5 input port src |
| * is connected to output of unit layerblend6 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND6 0x32U |
| /* Field Value: EXTDST5_SRC_SEL__LAYERBLEND5, Unit extdst5 input port src |
| * is connected to output of unit layerblend5 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND5 0x31U |
| /* Field Value: EXTDST5_SRC_SEL__LAYERBLEND4, Unit extdst5 input port src |
| * is connected to output of unit layerblend4 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND4 0x30U |
| /* Field Value: EXTDST5_SRC_SEL__LAYERBLEND3, Unit extdst5 input port src |
| * is connected to output of unit layerblend3 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND3 0x2FU |
| /* Field Value: EXTDST5_SRC_SEL__LAYERBLEND2, Unit extdst5 input port src |
| * is connected to output of unit layerblend2 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND2 0x2EU |
| /* Field Value: EXTDST5_SRC_SEL__LAYERBLEND1, Unit extdst5 input port src |
| * is connected to output of unit layerblend1 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND1 0x2DU |
| /* Field Value: EXTDST5_SRC_SEL__LAYERBLEND0, Unit extdst5 input port src |
| * is connected to output of unit layerblend0 */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND0 0x2CU |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst5_Request */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST ((uint32_t)(0xA50)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_OFFSET ((uint32_t)(0x250)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SEL_SHDLDREQ_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SEL_SHDLDREQ_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SHDLDREQ_MASK 0x3FFFFEU |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SHDLDREQ_SHIFT 1U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst5_Trigger */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER ((uint32_t)(0xA54)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_OFFSET ((uint32_t)(0x254)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_RESET_MASK 0xFFFFFFEEU |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_SYNC_TRIGGER_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_SYNC_TRIGGER_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U |
| |
| /* Register: IMXDPUV1_pixengcfg_extdst5_Status */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS ((uint32_t)(0xA58)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_OFFSET ((uint32_t)(0x258)) |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS_MASK 0x3U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS_SHIFT 0U |
| /* Field Value: EXTDST5_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst5 |
| * is empty */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__EMPTY 0U |
| /* Field Value: EXTDST5_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst5 |
| * is currently processing one operation */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__RUNNING 0x1U |
| /* Field Value: EXTDST5_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with |
| * endpoint extdst5 is currently processing one operation with a second |
| * one already kicked to be processed afterwards */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U |
| /* Field Value: EXTDST5_PIPELINE_STATUS__RESERVED, reserved */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__RESERVED 0x3U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY_SHIFT 8U |
| /* Field Value: EXTDST5_SYNC_BUSY__IDLE, extdst5 synchronizer is idle */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY__IDLE 0U |
| /* Field Value: EXTDST5_SYNC_BUSY__BUSY, extdst5 synchronizer is busy */ |
| #define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY__BUSY 0x1U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchwarp2_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK ((uint32_t)(0xA60)) |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_OFFSET ((uint32_t)(0x260)) |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: FETCHWARP2_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset |
| * counter value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: FETCHWARP2_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: FETCHWARP2_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: FETCHWARP2_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege |
| * protection. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: FETCHWARP2_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchwarp2_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS ((uint32_t)(0xA64)) |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_OFFSET ((uint32_t)(0x264)) |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchwarp2_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC ((uint32_t)(0xA68)) |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_OFFSET ((uint32_t)(0x268)) |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL_SHIFT 0U |
| /* Field Value: FETCHWARP2_SRC_SEL__DISABLE, Unit fetchwarp2 input port src |
| * is disabled */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL__DISABLE 0U |
| /* Field Value: FETCHWARP2_SRC_SEL__FETCHECO2, Unit fetchwarp2 input port |
| * src is connected to output of unit fetcheco2 */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL__FETCHECO2 0x1BU |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchwarp2_Status */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS ((uint32_t)(0xA6C)) |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_OFFSET ((uint32_t)(0x26C)) |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL_SHIFT 16U |
| /* Field Value: FETCHWARP2_SEL__STORE9, fetchwarp2 module is used from store9 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__STORE9 0x1U |
| /* Field Value: FETCHWARP2_SEL__EXTDST0, fetchwarp2 module is used from extdst0 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST0 0x2U |
| /* Field Value: FETCHWARP2_SEL__EXTDST4, fetchwarp2 module is used from extdst4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST4 0x3U |
| /* Field Value: FETCHWARP2_SEL__EXTDST1, fetchwarp2 module is used from extdst1 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST1 0x4U |
| /* Field Value: FETCHWARP2_SEL__EXTDST5, fetchwarp2 module is used from extdst5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST5 0x5U |
| /* Field Value: FETCHWARP2_SEL__STORE4, fetchwarp2 module is used from store4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__STORE4 0x6U |
| /* Field Value: FETCHWARP2_SEL__STORE5, fetchwarp2 module is used from store5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__STORE5 0x7U |
| /* Field Value: FETCHWARP2_SEL__DISABLE, fetchwarp2 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetcheco2_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK ((uint32_t)(0xA70)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_OFFSET ((uint32_t)(0x270)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: FETCHECO2_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset |
| * counter value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: FETCHECO2_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: FETCHECO2_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: FETCHECO2_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege |
| * protection. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: FETCHECO2_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetcheco2_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS ((uint32_t)(0xA74)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_OFFSET ((uint32_t)(0x274)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetcheco2_Status */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS ((uint32_t)(0xA78)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_OFFSET ((uint32_t)(0x278)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL_SHIFT 16U |
| /* Field Value: FETCHECO2_SEL__STORE9, fetcheco2 module is used from store9 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__STORE9 0x1U |
| /* Field Value: FETCHECO2_SEL__EXTDST0, fetcheco2 module is used from extdst0 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST0 0x2U |
| /* Field Value: FETCHECO2_SEL__EXTDST4, fetcheco2 module is used from extdst4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST4 0x3U |
| /* Field Value: FETCHECO2_SEL__EXTDST1, fetcheco2 module is used from extdst1 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST1 0x4U |
| /* Field Value: FETCHECO2_SEL__EXTDST5, fetcheco2 module is used from extdst5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST5 0x5U |
| /* Field Value: FETCHECO2_SEL__STORE4, fetcheco2 module is used from store4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__STORE4 0x6U |
| /* Field Value: FETCHECO2_SEL__STORE5, fetcheco2 module is used from store5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__STORE5 0x7U |
| /* Field Value: FETCHECO2_SEL__DISABLE, fetcheco2 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchdecode0_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK ((uint32_t)(0xA80)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_OFFSET ((uint32_t)(0x280)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: FETCHDECODE0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset |
| * counter value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: FETCHDECODE0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock |
| * counter. Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: FETCHDECODE0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege |
| * protection. Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: FETCHDECODE0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege |
| * protection. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: FETCHDECODE0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchdecode0_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS ((uint32_t)(0xA84)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_OFFSET ((uint32_t)(0x284)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchdecode0_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC ((uint32_t)(0xA88)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_OFFSET ((uint32_t)(0x288)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL_SHIFT 0U |
| /* Field Value: FETCHDECODE0_SRC_SEL__DISABLE, Unit fetchdecode0 input port |
| * src is disabled */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL__DISABLE 0U |
| /* Field Value: FETCHDECODE0_SRC_SEL__FETCHECO0, Unit fetchdecode0 input port |
| * src is connected to output of unit fetcheco0 */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL__FETCHECO0 0x1DU |
| /* Field Value: FETCHDECODE0_SRC_SEL__FETCHDECODE2, Unit fetchdecode0 input |
| * port src is connected to output of unit fetchdecode2 */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL__FETCHDECODE2 0x18U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchdecode0_Status */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS ((uint32_t)(0xA8C)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_OFFSET ((uint32_t)(0x28C)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL_SHIFT 16U |
| /* Field Value: FETCHDECODE0_SEL__STORE9, fetchdecode0 module is used from |
| * store9 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__STORE9 0x1U |
| /* Field Value: FETCHDECODE0_SEL__EXTDST0, fetchdecode0 module is used from |
| * extdst0 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST0 0x2U |
| /* Field Value: FETCHDECODE0_SEL__EXTDST4, fetchdecode0 module is used from |
| * extdst4 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST4 0x3U |
| /* Field Value: FETCHDECODE0_SEL__EXTDST1, fetchdecode0 module is used from |
| * extdst1 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST1 0x4U |
| /* Field Value: FETCHDECODE0_SEL__EXTDST5, fetchdecode0 module is used from |
| * extdst5 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST5 0x5U |
| /* Field Value: FETCHDECODE0_SEL__STORE4, fetchdecode0 module is used from |
| * store4 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__STORE4 0x6U |
| /* Field Value: FETCHDECODE0_SEL__STORE5, fetchdecode0 module is used from |
| * store5 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__STORE5 0x7U |
| /* Field Value: FETCHDECODE0_SEL__DISABLE, fetchdecode0 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetcheco0_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK ((uint32_t)(0xA90)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_OFFSET ((uint32_t)(0x290)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: FETCHECO0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset |
| * counter value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: FETCHECO0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: FETCHECO0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: FETCHECO0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege |
| * protection. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: FETCHECO0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetcheco0_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS ((uint32_t)(0xA94)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_OFFSET ((uint32_t)(0x294)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetcheco0_Status */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS ((uint32_t)(0xA98)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_OFFSET ((uint32_t)(0x298)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL_SHIFT 16U |
| /* Field Value: FETCHECO0_SEL__STORE9, fetcheco0 module is used from store9 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__STORE9 0x1U |
| /* Field Value: FETCHECO0_SEL__EXTDST0, fetcheco0 module is used from extdst0 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST0 0x2U |
| /* Field Value: FETCHECO0_SEL__EXTDST4, fetcheco0 module is used from extdst4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST4 0x3U |
| /* Field Value: FETCHECO0_SEL__EXTDST1, fetcheco0 module is used from extdst1 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST1 0x4U |
| /* Field Value: FETCHECO0_SEL__EXTDST5, fetcheco0 module is used from extdst5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST5 0x5U |
| /* Field Value: FETCHECO0_SEL__STORE4, fetcheco0 module is used from store4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__STORE4 0x6U |
| /* Field Value: FETCHECO0_SEL__STORE5, fetcheco0 module is used from store5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__STORE5 0x7U |
| /* Field Value: FETCHECO0_SEL__DISABLE, fetcheco0 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchdecode1_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK ((uint32_t)(0xAA0)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_OFFSET ((uint32_t)(0x2A0)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: FETCHDECODE1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset |
| * counter value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: FETCHDECODE1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock |
| * counter. Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: FETCHDECODE1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege |
| * protection. Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: FETCHDECODE1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege |
| * protection. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: FETCHDECODE1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchdecode1_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS ((uint32_t)(0xAA4)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_OFFSET ((uint32_t)(0x2A4)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchdecode1_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC ((uint32_t)(0xAA8)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_OFFSET ((uint32_t)(0x2A8)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL_SHIFT 0U |
| /* Field Value: FETCHDECODE1_SRC_SEL__DISABLE, Unit fetchdecode1 input port |
| * src is disabled */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL__DISABLE 0U |
| /* Field Value: FETCHDECODE1_SRC_SEL__FETCHECO1, Unit fetchdecode1 input port |
| * src is connected to output of unit fetcheco1 */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL__FETCHECO1 0x1FU |
| /* Field Value: FETCHDECODE1_SRC_SEL__FETCHDECODE3, Unit fetchdecode1 input |
| * port src is connected to output of unit fetchdecode3 */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL__FETCHDECODE3 0x19U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchdecode1_Status */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS ((uint32_t)(0xAAC)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_OFFSET ((uint32_t)(0x2AC)) |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL_SHIFT 16U |
| /* Field Value: FETCHDECODE1_SEL__STORE9, fetchdecode1 module is used from |
| * store9 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__STORE9 0x1U |
| /* Field Value: FETCHDECODE1_SEL__EXTDST0, fetchdecode1 module is used from |
| * extdst0 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST0 0x2U |
| /* Field Value: FETCHDECODE1_SEL__EXTDST4, fetchdecode1 module is used from |
| * extdst4 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST4 0x3U |
| /* Field Value: FETCHDECODE1_SEL__EXTDST1, fetchdecode1 module is used from |
| * extdst1 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST1 0x4U |
| /* Field Value: FETCHDECODE1_SEL__EXTDST5, fetchdecode1 module is used from |
| * extdst5 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST5 0x5U |
| /* Field Value: FETCHDECODE1_SEL__STORE4, fetchdecode1 module is used from |
| * store4 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__STORE4 0x6U |
| /* Field Value: FETCHDECODE1_SEL__STORE5, fetchdecode1 module is used from |
| * store5 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__STORE5 0x7U |
| /* Field Value: FETCHDECODE1_SEL__DISABLE, fetchdecode1 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetcheco1_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK ((uint32_t)(0xAB0)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_OFFSET ((uint32_t)(0x2B0)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: FETCHECO1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset |
| * counter value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: FETCHECO1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: FETCHECO1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: FETCHECO1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege |
| * protection. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: FETCHECO1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetcheco1_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS ((uint32_t)(0xAB4)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_OFFSET ((uint32_t)(0x2B4)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetcheco1_Status */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS ((uint32_t)(0xAB8)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_OFFSET ((uint32_t)(0x2B8)) |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL_SHIFT 16U |
| /* Field Value: FETCHECO1_SEL__STORE9, fetcheco1 module is used from store9 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__STORE9 0x1U |
| /* Field Value: FETCHECO1_SEL__EXTDST0, fetcheco1 module is used from extdst0 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST0 0x2U |
| /* Field Value: FETCHECO1_SEL__EXTDST4, fetcheco1 module is used from extdst4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST4 0x3U |
| /* Field Value: FETCHECO1_SEL__EXTDST1, fetcheco1 module is used from extdst1 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST1 0x4U |
| /* Field Value: FETCHECO1_SEL__EXTDST5, fetcheco1 module is used from extdst5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST5 0x5U |
| /* Field Value: FETCHECO1_SEL__STORE4, fetcheco1 module is used from store4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__STORE4 0x6U |
| /* Field Value: FETCHECO1_SEL__STORE5, fetcheco1 module is used from store5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__STORE5 0x7U |
| /* Field Value: FETCHECO1_SEL__DISABLE, fetcheco1 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchlayer0_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK ((uint32_t)(0xAC0)) |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_OFFSET ((uint32_t)(0x2C0)) |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: FETCHLAYER0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset |
| * counter value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: FETCHLAYER0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock |
| * counter. Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: FETCHLAYER0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: FETCHLAYER0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege |
| * protection. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: FETCHLAYER0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchlayer0_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS ((uint32_t)(0xAC4)) |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_OFFSET ((uint32_t)(0x2C4)) |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_fetchlayer0_Status */ |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS ((uint32_t)(0xAC8)) |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_OFFSET ((uint32_t)(0x2C8)) |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL_SHIFT 16U |
| /* Field Value: FETCHLAYER0_SEL__STORE9, fetchlayer0 module is used from store9 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__STORE9 0x1U |
| /* Field Value: FETCHLAYER0_SEL__EXTDST0, fetchlayer0 module is used from |
| * extdst0 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST0 0x2U |
| /* Field Value: FETCHLAYER0_SEL__EXTDST4, fetchlayer0 module is used from |
| * extdst4 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST4 0x3U |
| /* Field Value: FETCHLAYER0_SEL__EXTDST1, fetchlayer0 module is used from |
| * extdst1 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST1 0x4U |
| /* Field Value: FETCHLAYER0_SEL__EXTDST5, fetchlayer0 module is used from |
| * extdst5 processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST5 0x5U |
| /* Field Value: FETCHLAYER0_SEL__STORE4, fetchlayer0 module is used from store4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__STORE4 0x6U |
| /* Field Value: FETCHLAYER0_SEL__STORE5, fetchlayer0 module is used from store5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__STORE5 0x7U |
| /* Field Value: FETCHLAYER0_SEL__DISABLE, fetchlayer0 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_matrix4_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK ((uint32_t)(0xAE0)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_OFFSET ((uint32_t)(0x2E0)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: MATRIX4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset counter |
| * value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: MATRIX4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: MATRIX4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: MATRIX4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: MATRIX4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_matrix4_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS ((uint32_t)(0xAE4)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_OFFSET ((uint32_t)(0x2E4)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_matrix4_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC ((uint32_t)(0xAE8)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_OFFSET ((uint32_t)(0x2E8)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_RESET_VALUE 0x1000000U |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL_SHIFT 0U |
| /* Field Value: MATRIX4_SRC_SEL__DISABLE, Unit matrix4 input port src is disabled */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL__DISABLE 0U |
| /* Field Value: MATRIX4_SRC_SEL__GAMMACOR4, Unit matrix4 input port src is |
| * connected to output of unit gammacor4 */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL__GAMMACOR4 0x22U |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN_MASK 0x3000000U |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN_SHIFT 24U |
| /* Field Value: MATRIX4_CLKEN__DISABLE, Clock for matrix4 is disabled */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN__DISABLE 0U |
| /* Field Value: MATRIX4_CLKEN__AUTOMATIC, Clock is enabled if unit is used, |
| * frequency is defined by the register setting for this pipeline (see |
| * [endpoint_name]_Static register) */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN__AUTOMATIC 0x1U |
| /* Field Value: MATRIX4_CLKEN__FULL, Clock for matrix4 is without gating */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN__FULL 0x3U |
| |
| /* Register: IMXDPUV1_pixengcfg_matrix4_Status */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS ((uint32_t)(0xAEC)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_OFFSET ((uint32_t)(0x2EC)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL_SHIFT 16U |
| /* Field Value: MATRIX4_SEL__STORE9, matrix4 module is used from store9 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__STORE9 0x1U |
| /* Field Value: MATRIX4_SEL__EXTDST0, matrix4 module is used from extdst0 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST0 0x2U |
| /* Field Value: MATRIX4_SEL__EXTDST4, matrix4 module is used from extdst4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST4 0x3U |
| /* Field Value: MATRIX4_SEL__EXTDST1, matrix4 module is used from extdst1 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST1 0x4U |
| /* Field Value: MATRIX4_SEL__EXTDST5, matrix4 module is used from extdst5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST5 0x5U |
| /* Field Value: MATRIX4_SEL__STORE4, matrix4 module is used from store4 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__STORE4 0x6U |
| /* Field Value: MATRIX4_SEL__STORE5, matrix4 module is used from store5 processing |
| * path */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__STORE5 0x7U |
| /* Field Value: MATRIX4_SEL__DISABLE, matrix4 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_hscaler4_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK ((uint32_t)(0xB00)) |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_OFFSET ((uint32_t)(0x300)) |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: HSCALER4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset counter |
| * value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: HSCALER4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: HSCALER4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: HSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: HSCALER4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_hscaler4_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS ((uint32_t)(0xB04)) |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_OFFSET ((uint32_t)(0x304)) |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_hscaler4_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC ((uint32_t)(0xB08)) |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_OFFSET ((uint32_t)(0x308)) |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_RESET_VALUE 0x1000000U |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL_SHIFT 0U |
| /* Field Value: HSCALER4_SRC_SEL__DISABLE, Unit hscaler4 input port src is |
| * disabled */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__DISABLE 0U |
| /* Field Value: HSCALER4_SRC_SEL__EXTSRC4, Unit hscaler4 input port src is |
| * connected to output of unit extsrc4 */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__EXTSRC4 0x14U |
| /* Field Value: HSCALER4_SRC_SEL__FETCHDECODE0, Unit hscaler4 input port src |
| * is connected to output of unit fetchdecode0 */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__FETCHDECODE0 0x1CU |
| /* Field Value: HSCALER4_SRC_SEL__FETCHDECODE2, Unit hscaler4 input port src |
| * is connected to output of unit fetchdecode2 */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__FETCHDECODE2 0x18U |
| /* Field Value: HSCALER4_SRC_SEL__MATRIX4, Unit hscaler4 input port src is |
| * connected to output of unit matrix4 */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__MATRIX4 0x23U |
| /* Field Value: HSCALER4_SRC_SEL__VSCALER4, Unit hscaler4 input port src is |
| * connected to output of unit vscaler4 */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__VSCALER4 0x25U |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN_MASK 0x3000000U |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN_SHIFT 24U |
| /* Field Value: HSCALER4_CLKEN__DISABLE, Clock for hscaler4 is disabled */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN__DISABLE 0U |
| /* Field Value: HSCALER4_CLKEN__AUTOMATIC, Clock is enabled if unit is used, |
| * frequency is defined by the register setting for this pipeline (see |
| * [endpoint_name]_Static register) */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN__AUTOMATIC 0x1U |
| /* Field Value: HSCALER4_CLKEN__FULL, Clock for hscaler4 is without gating */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN__FULL 0x3U |
| |
| /* Register: IMXDPUV1_pixengcfg_hscaler4_Status */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS ((uint32_t)(0xB0C)) |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_OFFSET ((uint32_t)(0x30C)) |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL_SHIFT 16U |
| /* Field Value: HSCALER4_SEL__STORE9, hscaler4 module is used from store9 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__STORE9 0x1U |
| /* Field Value: HSCALER4_SEL__EXTDST0, hscaler4 module is used from extdst0 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST0 0x2U |
| /* Field Value: HSCALER4_SEL__EXTDST4, hscaler4 module is used from extdst4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST4 0x3U |
| /* Field Value: HSCALER4_SEL__EXTDST1, hscaler4 module is used from extdst1 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST1 0x4U |
| /* Field Value: HSCALER4_SEL__EXTDST5, hscaler4 module is used from extdst5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST5 0x5U |
| /* Field Value: HSCALER4_SEL__STORE4, hscaler4 module is used from store4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__STORE4 0x6U |
| /* Field Value: HSCALER4_SEL__STORE5, hscaler4 module is used from store5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__STORE5 0x7U |
| /* Field Value: HSCALER4_SEL__DISABLE, hscaler4 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_vscaler4_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK ((uint32_t)(0xB20)) |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_OFFSET ((uint32_t)(0x320)) |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: VSCALER4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset counter |
| * value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: VSCALER4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: VSCALER4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: VSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: VSCALER4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_vscaler4_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS ((uint32_t)(0xB24)) |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_OFFSET ((uint32_t)(0x324)) |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_LOCKSTATUS_MASK 0x1U |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_LOCKSTATUS_SHIFT 0U |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_PRIVILEGESTATUS_MASK 0x10U |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_PRIVILEGESTATUS_SHIFT 4U |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_FREEZESTATUS_MASK 0x100U |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_FREEZESTATUS_SHIFT 8U |
| |
| /* Register: IMXDPUV1_pixengcfg_vscaler4_Dynamic */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC ((uint32_t)(0xB28)) |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_OFFSET ((uint32_t)(0x328)) |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_RESET_VALUE 0x1000000U |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_RESET_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL_MASK 0x3FU |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL_SHIFT 0U |
| /* Field Value: VSCALER4_SRC_SEL__DISABLE, Unit vscaler4 input port src is |
| * disabled */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__DISABLE 0U |
| /* Field Value: VSCALER4_SRC_SEL__EXTSRC4, Unit vscaler4 input port src is |
| * connected to output of unit extsrc4 */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__EXTSRC4 0x14U |
| /* Field Value: VSCALER4_SRC_SEL__FETCHDECODE0, Unit vscaler4 input port src |
| * is connected to output of unit fetchdecode0 */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__FETCHDECODE0 0x1CU |
| /* Field Value: VSCALER4_SRC_SEL__FETCHDECODE2, Unit vscaler4 input port src |
| * is connected to output of unit fetchdecode2 */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__FETCHDECODE2 0x18U |
| /* Field Value: VSCALER4_SRC_SEL__HSCALER4, Unit vscaler4 input port src is |
| * connected to output of unit hscaler4 */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__HSCALER4 0x24U |
| /* Field Value: VSCALER4_SRC_SEL__MATRIX4, Unit vscaler4 input port src is |
| * connected to output of unit matrix4 */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__MATRIX4 0x23U |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN_MASK 0x3000000U |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN_SHIFT 24U |
| /* Field Value: VSCALER4_CLKEN__DISABLE, Clock for vscaler4 is disabled */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN__DISABLE 0U |
| /* Field Value: VSCALER4_CLKEN__AUTOMATIC, Clock is enabled if unit is used, |
| * frequency is defined by the register setting for this pipeline (see |
| * [endpoint_name]_Static register) */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN__AUTOMATIC 0x1U |
| /* Field Value: VSCALER4_CLKEN__FULL, Clock for vscaler4 is without gating */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN__FULL 0x3U |
| |
| /* Register: IMXDPUV1_pixengcfg_vscaler4_Status */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS ((uint32_t)(0xB2C)) |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_OFFSET ((uint32_t)(0x32C)) |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_RESET_MASK 0xFFF8FFFFU |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL_MASK 0x70000U |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL_SHIFT 16U |
| /* Field Value: VSCALER4_SEL__STORE9, vscaler4 module is used from store9 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__STORE9 0x1U |
| /* Field Value: VSCALER4_SEL__EXTDST0, vscaler4 module is used from extdst0 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST0 0x2U |
| /* Field Value: VSCALER4_SEL__EXTDST4, vscaler4 module is used from extdst4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST4 0x3U |
| /* Field Value: VSCALER4_SEL__EXTDST1, vscaler4 module is used from extdst1 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST1 0x4U |
| /* Field Value: VSCALER4_SEL__EXTDST5, vscaler4 module is used from extdst5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST5 0x5U |
| /* Field Value: VSCALER4_SEL__STORE4, vscaler4 module is used from store4 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__STORE4 0x6U |
| /* Field Value: VSCALER4_SEL__STORE5, vscaler4 module is used from store5 |
| * processing path */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__STORE5 0x7U |
| /* Field Value: VSCALER4_SEL__DISABLE, vscaler4 module is not used */ |
| #define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__DISABLE 0U |
| |
| /* Register: IMXDPUV1_pixengcfg_matrix5_LockUnlock */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK ((uint32_t)(0xB40)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_OFFSET ((uint32_t)(0x340)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_RESET_MASK 0U |
| #define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK_MASK 0xFFFFFFFFU |
| #define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK_SHIFT 0U |
| /* Field Value: MATRIX5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. |
| * When the counter value is null, lock protection is active. Reset counter |
| * value is 1. */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__LOCK_KEY 0x5651F763U |
| /* Field Value: MATRIX5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. |
| * Max allowed value is 15. */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U |
| /* Field Value: MATRIX5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. |
| * Disabled after reset. */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU |
| /* Field Value: MATRIX5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU |
| /* Field Value: MATRIX5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection |
| * status. Writing keys to this register has no more effect until reset. */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U |
| |
| /* Register: IMXDPUV1_pixengcfg_matrix5_LockStatus */ |
| #define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS ((uint32_t)(0xB44)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_OFFSET ((uint32_t)(0x344)) |
| #define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_RESET_VALUE 0U |
| #define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU |
|
