| /* |
| * Copyright 2015 Freescale Semiconductor |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #ifndef __LS1043ARDB_H__ |
| #define __LS1043ARDB_H__ |
| |
| #include "ls1043a_common.h" |
| |
| #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) |
| #define CONFIG_SYS_TEXT_BASE 0x82000000 |
| #else |
| #define CONFIG_SYS_TEXT_BASE 0x60100000 |
| #endif |
| |
| #define CONFIG_SYS_CLK_FREQ 100000000 |
| #define CONFIG_DDR_CLK_FREQ 100000000 |
| |
| #define CONFIG_LAYERSCAPE_NS_ACCESS |
| #define CONFIG_MISC_INIT_R |
| |
| #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| /* Physical Memory Map */ |
| #define CONFIG_CHIP_SELECTS_PER_CTRL 4 |
| #define CONFIG_NR_DRAM_BANKS 2 |
| |
| #define CONFIG_SYS_SPD_BUS_NUM 0 |
| |
| #define CONFIG_FSL_DDR_BIST |
| #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ |
| #define CONFIG_SYS_DDR_RAW_TIMING |
| #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
| #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
| |
| #ifdef CONFIG_RAMBOOT_PBL |
| #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg |
| #endif |
| |
| #ifdef CONFIG_NAND_BOOT |
| #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg |
| #endif |
| |
| #ifdef CONFIG_SD_BOOT |
| #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg |
| #endif |
| |
| /* |
| * NOR Flash Definitions |
| */ |
| #define CONFIG_SYS_NOR_CSPR_EXT (0x0) |
| #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
| #define CONFIG_SYS_NOR_CSPR \ |
| (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ |
| CSPR_PORT_SIZE_16 | \ |
| CSPR_MSEL_NOR | \ |
| CSPR_V) |
| |
| /* NOR Flash Timing Params */ |
| #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ |
| CSOR_NOR_TRHZ_80) |
| #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ |
| FTIM0_NOR_TEADC(0x1) | \ |
| FTIM0_NOR_TAVDS(0x0) | \ |
| FTIM0_NOR_TEAHC(0xc)) |
| #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ |
| FTIM1_NOR_TRAD_NOR(0xb) | \ |
| FTIM1_NOR_TSEQRAD_NOR(0x9)) |
| #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ |
| FTIM2_NOR_TCH(0x4) | \ |
| FTIM2_NOR_TWPH(0x8) | \ |
| FTIM2_NOR_TWP(0x10)) |
| #define CONFIG_SYS_NOR_FTIM3 0 |
| #define CONFIG_SYS_IFC_CCR 0x01000000 |
| |
| #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
| #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| |
| #define CONFIG_SYS_FLASH_EMPTY_INFO |
| #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } |
| |
| #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
| #define CONFIG_SYS_WRITE_SWAPPED_DATA |
| |
| /* |
| * NAND Flash Definitions |
| */ |
| #define CONFIG_NAND_FSL_IFC |
| |
| #define CONFIG_SYS_NAND_BASE 0x7e800000 |
| #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| |
| #define CONFIG_SYS_NAND_CSPR_EXT (0x0) |
| #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| | CSPR_PORT_SIZE_8 \ |
| | CSPR_MSEL_NAND \ |
| | CSPR_V) |
| #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) |
| #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
| | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ |
| | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ |
| | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ |
| | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ |
| | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ |
| | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ |
| |
| #define CONFIG_SYS_NAND_ONFI_DETECTION |
| |
| #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ |
| FTIM0_NAND_TWP(0x18) | \ |
| FTIM0_NAND_TWCHT(0x7) | \ |
| FTIM0_NAND_TWH(0xa)) |
| #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
| FTIM1_NAND_TWBE(0x39) | \ |
| FTIM1_NAND_TRR(0xe) | \ |
| FTIM1_NAND_TRP(0x18)) |
| #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ |
| FTIM2_NAND_TREH(0xa) | \ |
| FTIM2_NAND_TWHRE(0x1e)) |
| #define CONFIG_SYS_NAND_FTIM3 0x0 |
| |
| #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
| #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| #define CONFIG_MTD_NAND_VERIFY_WRITE |
| #define CONFIG_CMD_NAND |
| |
| #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
| |
| #ifdef CONFIG_NAND_BOOT |
| #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ |
| #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO |
| #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) |
| #endif |
| |
| /* |
| * CPLD |
| */ |
| #define CONFIG_SYS_CPLD_BASE 0x7fb00000 |
| #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE |
| |
| #define CONFIG_SYS_CPLD_CSPR_EXT (0x0) |
| #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ |
| CSPR_PORT_SIZE_8 | \ |
| CSPR_MSEL_GPCM | \ |
| CSPR_V) |
| #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) |
| #define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ |
| CSOR_NOR_NOR_MODE_AVD_NOR | \ |
| CSOR_NOR_TRHZ_80) |
| |
| /* CPLD Timing parameters for IFC GPCM */ |
| #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ |
| FTIM0_GPCM_TEADC(0xf) | \ |
| FTIM0_GPCM_TEAHC(0xf)) |
| #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ |
| FTIM1_GPCM_TRAD(0x3f)) |
| #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ |
| FTIM2_GPCM_TCH(0xf) | \ |
| FTIM2_GPCM_TWP(0xff)) |
| #define CONFIG_SYS_CPLD_FTIM3 0x0 |
| |
| /* IFC Timing Params */ |
| #ifdef CONFIG_NAND_BOOT |
| #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
| #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
| #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK |
| #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR |
| #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| |
| #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT |
| #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR |
| #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK |
| #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR |
| #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| #else |
| #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT |
| #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR |
| #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
| #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
| #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| |
| #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT |
| #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR |
| #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK |
| #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR |
| #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| #endif |
| |
| #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT |
| #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR |
| #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK |
| #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR |
| #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 |
| #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 |
| #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 |
| #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 |
| |
| /* EEPROM */ |
| #define CONFIG_ID_EEPROM |
| #define CONFIG_SYS_I2C_EEPROM_NXID |
| #define CONFIG_SYS_EEPROM_BUS_NUM 0 |
| #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 |
| #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
| #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 |
| |
| /* |
| * Environment |
| */ |
| #define CONFIG_ENV_OVERWRITE |
| |
| #if defined(CONFIG_NAND_BOOT) |
| #define CONFIG_ENV_IS_IN_NAND |
| #define CONFIG_ENV_SIZE 0x2000 |
| #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) |
| #elif defined(CONFIG_SD_BOOT) |
| #define CONFIG_ENV_OFFSET (1024 * 1024) |
| #define CONFIG_ENV_IS_IN_MMC |
| #define CONFIG_SYS_MMC_ENV_DEV 0 |
| #define CONFIG_ENV_SIZE 0x2000 |
| #else |
| #define CONFIG_ENV_IS_IN_FLASH |
| #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) |
| #define CONFIG_ENV_SECT_SIZE 0x20000 |
| #define CONFIG_ENV_SIZE 0x20000 |
| #endif |
| |
| /* FMan */ |
| #ifdef CONFIG_SYS_DPAA_FMAN |
| #define CONFIG_FMAN_ENET |
| #define CONFIG_PHYLIB |
| #define CONFIG_PHYLIB_10G |
| #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ |
| |
| #define CONFIG_PHY_VITESSE |
| #define CONFIG_PHY_REALTEK |
| #define CONFIG_PHY_AQUANTIA |
| #define AQR105_IRQ_MASK 0x40000000 |
| |
| #define RGMII_PHY1_ADDR 0x1 |
| #define RGMII_PHY2_ADDR 0x2 |
| |
| #define QSGMII_PORT1_PHY_ADDR 0x4 |
| #define QSGMII_PORT2_PHY_ADDR 0x5 |
| #define QSGMII_PORT3_PHY_ADDR 0x6 |
| #define QSGMII_PORT4_PHY_ADDR 0x7 |
| |
| #define FM1_10GEC1_PHY_ADDR 0x1 |
| |
| #define CONFIG_ETHPRIME "FM1@DTSEC3" |
| #endif |
| |
| /* QE */ |
| #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ |
| !defined(CONFIG_QSPI_BOOT) |
| #define CONFIG_U_QE |
| #endif |
| #define CONFIG_SYS_QE_FW_ADDR 0x60600000 |
| |
| /* USB */ |
| #define CONFIG_HAS_FSL_XHCI_USB |
| #ifdef CONFIG_HAS_FSL_XHCI_USB |
| #define CONFIG_USB_XHCI_FSL |
| #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 |
| #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 |
| #endif |
| |
| /* SATA */ |
| #define CONFIG_LIBATA |
| #define CONFIG_SCSI_AHCI |
| #define CONFIG_CMD_SCSI |
| #ifndef CONFIG_CMD_FAT |
| #define CONFIG_CMD_FAT |
| #endif |
| #ifndef CONFIG_CMD_EXT2 |
| #define CONFIG_CMD_EXT2 |
| #endif |
| #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 |
| #define CONFIG_SYS_SCSI_MAX_LUN 2 |
| #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ |
| CONFIG_SYS_SCSI_MAX_LUN) |
| #define SCSI_VEND_ID 0x1b4b |
| #define SCSI_DEV_ID 0x9170 |
| #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} |
| |
| #include <asm/fsl_secure_boot.h> |
| |
| #endif /* __LS1043ARDB_H__ */ |
