| /* |
| * Copyright (C) 2015 Technexion Ltd. |
| * |
| * Author: Richard Hu <richard.hu@technexion.com> |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #include <asm/arch/clock.h> |
| #include <asm/arch/iomux.h> |
| #include <asm/arch/imx-regs.h> |
| #include <asm/arch/crm_regs.h> |
| #include <asm/arch/mx6-pins.h> |
| #include <asm/arch/sys_proto.h> |
| #include <asm/gpio.h> |
| #include <asm/imx-common/iomux-v3.h> |
| #include <asm/imx-common/boot_mode.h> |
| #include <asm/imx-common/mxc_i2c.h> |
| #include <asm/io.h> |
| #include <common.h> |
| #include <fsl_esdhc.h> |
| #include <i2c.h> |
| #include <linux/sizes.h> |
| #include <linux/fb.h> |
| #include <miiphy.h> |
| #include <mmc.h> |
| #include <mxsfb.h> |
| #include <netdev.h> |
| #include <usb.h> |
| #include <usb/ehci-ci.h> |
| |
| #ifdef CONFIG_POWER |
| #include <power/pmic.h> |
| #include <power/pfuze3000_pmic.h> |
| #include "../../freescale/common/pfuze.h" |
| #endif |
| |
| #ifdef CONFIG_FSL_FASTBOOT |
| #include <fsl_fastboot.h> |
| #ifdef CONFIG_ANDROID_RECOVERY |
| #include <recovery.h> |
| #endif |
| #endif /*CONFIG_FSL_FASTBOOT*/ |
| |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ |
| PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| #define USDHC_SD_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ |
| PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| |
| #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ |
| PAD_CTL_SPEED_HIGH | \ |
| PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) |
| |
| #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ |
| PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) |
| |
| |
| #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) |
| |
| #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) |
| |
| #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ |
| PAD_CTL_ODE) |
| |
| #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ |
| PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) |
| |
| #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) |
| #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_SRE_FAST) |
| #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) |
| |
| #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) |
| |
| #define SPI_PAD_CTRL (PAD_CTL_HYS | \ |
| PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) |
| |
| #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ |
| PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| #define VERSION_DET_DDR_SIZE IMX_GPIO_NR(5, 1) |
| |
| #ifdef CONFIG_SYS_I2C_MXC |
| #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) |
| /* I2C2 for PMIC */ |
| struct i2c_pads_info i2c_pad_info1 = { |
| .scl = { |
| .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, |
| .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, |
| .gp = IMX_GPIO_NR(1, 2), |
| }, |
| .sda = { |
| .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, |
| .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, |
| .gp = IMX_GPIO_NR(1, 3), |
| }, |
| }; |
| #endif |
| |
| int dram_init(void) |
| { |
| #ifdef CONFIG_IMX_TRUSTY_OS |
| gd->ram_size = PHYS_SDRAM_SIZE - TRUSTY_OS_RAM_SIZE; |
| #else |
| gd->ram_size = PHYS_SDRAM_SIZE; |
| #endif |
| |
| return 0; |
| } |
| |
| static iomux_v3_cfg_t const uart6_pads[] = { |
| MX6_PAD_CSI_MCLK__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const usdhc1_pads[] = { |
| MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| #ifndef CONFIG_SYS_USE_NAND |
| MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| #endif |
| /* CD */ |
| MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const version_detection_pads[] = { |
| /* dram size detection */ |
| MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| #ifdef CONFIG_SYS_USE_NAND |
| static iomux_v3_cfg_t const nand_pads[] = { |
| MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| }; |
| |
| static void setup_gpmi_nand(void) |
| { |
| struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| |
| /* config gpmi nand iomux */ |
| imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); |
| |
| clrbits_le32(&mxc_ccm->CCGR4, |
| MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | |
| MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | |
| MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | |
| MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | |
| MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); |
| |
| /* |
| * config gpmi and bch clock to 100 MHz |
| * bch/gpmi select PLL2 PFD2 400M |
| * 100M = 400M / 4 |
| */ |
| clrbits_le32(&mxc_ccm->cscmr1, |
| MXC_CCM_CSCMR1_BCH_CLK_SEL | |
| MXC_CCM_CSCMR1_GPMI_CLK_SEL); |
| clrsetbits_le32(&mxc_ccm->cscdr1, |
| MXC_CCM_CSCDR1_BCH_PODF_MASK | |
| MXC_CCM_CSCDR1_GPMI_PODF_MASK, |
| (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | |
| (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); |
| |
| /* enable gpmi and bch clock gating */ |
| setbits_le32(&mxc_ccm->CCGR4, |
| MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | |
| MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | |
| MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | |
| MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | |
| MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); |
| |
| /* enable apbh clock gating */ |
| setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); |
| } |
| #endif |
| |
| #ifdef CONFIG_FEC_MXC |
| static iomux_v3_cfg_t const fec_pads[] = { |
| MX6_PAD_ENET1_TX_EN__ENET2_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL), |
| MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), |
| |
| MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), |
| MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| |
| MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| |
| MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| #define RMII_PHY_RESET IMX_GPIO_NR(1, 28) |
| |
| static void setup_iomux_fec(int fec_id) |
| { |
| imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); |
| } |
| #endif |
| |
| static void setup_iomux_version_detection(void) |
| { |
| SETUP_IOMUX_PADS(version_detection_pads); |
| } |
| static void setup_iomux_uart(void) |
| { |
| imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads)); |
| } |
| |
| #ifdef CONFIG_FSL_ESDHC |
| static struct fsl_esdhc_cfg usdhc_cfg[2] = { |
| #ifdef CONFIG_SYS_USE_NAND |
| { USDHC1_BASE_ADDR, 0, 4 }, |
| #else |
| { USDHC1_BASE_ADDR, 0, 8 }, /* 8-bit emmc */ |
| #endif /* CONFIG_SYS_USE_NAND */ |
| }; |
| |
| #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) |
| |
| int board_mmc_get_env_dev(int devno) |
| { |
| return devno; |
| } |
| |
| int mmc_map_to_kernel_blk(int dev_no) |
| { |
| return dev_no; |
| } |
| |
| int board_mmc_getcd(struct mmc *mmc) |
| { |
| struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| int ret = 0; |
| |
| switch (cfg->esdhc_base) { |
| case USDHC1_BASE_ADDR: |
| #ifdef CONFIG_SYS_USE_NAND |
| ret = !gpio_get_value(USDHC1_CD_GPIO); |
| #else |
| ret = 1; |
| #endif |
| break; |
| } |
| |
| return ret; |
| |
| } |
| |
| int board_mmc_init(bd_t *bis) |
| { |
| int i, ret; |
| |
| /* |
| * According to the board_mmc_init() the following map is done: |
| * (U-boot device node) (Physical Port) |
| * mmc0 USDHC1 |
| */ |
| for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
| switch (i) { |
| case 0: |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); |
| usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
| break; |
| default: |
| printf("Warning: you configured more USDHC controllers" |
| "(%d) than supported by the board\n", i + 1); |
| return -EINVAL; |
| } |
| |
| ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
| if (ret) { |
| printf("Warning: failed to initialize mmc dev %d\n", i); |
| return ret; |
| } |
| } |
| |
| return 0; |
| } |
| |
| int check_mmc_autodetect(void) |
| { |
| char *autodetect_str = getenv("mmcautodetect"); |
| |
| if ((autodetect_str != NULL) && |
| (strcmp(autodetect_str, "yes") == 0)) { |
| return 1; |
| } |
| |
| return 0; |
| } |
| |
| void board_late_mmc_init(void) |
| { |
| char cmd[32]; |
| char mmcblk[32]; |
| u32 dev_no = mmc_get_env_dev(); |
| |
| if (!check_mmc_autodetect()) |
| return; |
| |
| setenv_ulong("mmcdev", dev_no); |
| |
| /* Set mmcblk env */ |
| sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", |
| mmc_map_to_kernel_blk(dev_no)); |
| setenv("mmcroot", mmcblk); |
| |
| sprintf(cmd, "mmc dev %d", dev_no); |
| run_command(cmd, 0); |
| } |
| #endif |
| |
| #ifdef CONFIG_VIDEO_MXS |
| static iomux_v3_cfg_t const lcd_pads[] = { |
| MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| |
| /* LCD_RST */ |
| MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| |
| /* |
| * Use GPIO for Brightness adjustment, duty cycle = period. |
| */ |
| MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| void do_enable_parallel_lcd(struct display_info_t const *dev) |
| { |
| enable_lcdif_clock(dev->bus, 1); |
| |
| imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); |
| |
| /* Reset the LCD */ |
| gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); |
| udelay(500); |
| gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); |
| |
| /* Set Brightness to high */ |
| gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); |
| } |
| |
| static struct display_info_t const displays[] = {{ |
| .lcdif_base_addr = MX6UL_LCDIF1_BASE_ADDR, |
| .addr = 0, |
| .pixfmt = 24, |
| .enable = do_enable_parallel_lcd, |
| .mode = { |
| .name = "TFT43AB", |
| .xres = 480, |
| .yres = 272, |
| .pixclock = 108695, |
| .left_margin = 8, |
| .right_margin = 4, |
| .upper_margin = 2, |
| .lower_margin = 4, |
| .hsync_len = 41, |
| .vsync_len = 10, |
| .sync = 0, |
| .vmode = FB_VMODE_NONINTERLACED |
| } } }; |
| size_t display_count = ARRAY_SIZE(displays); |
| #endif |
| |
| #ifdef CONFIG_FEC_MXC |
| int board_eth_init(bd_t *bis) |
| { |
| int ret; |
| |
| setup_iomux_fec(CONFIG_FEC_ENET_DEV); |
| |
| gpio_direction_output(RMII_PHY_RESET, 0); |
| udelay(500); |
| gpio_direction_output(RMII_PHY_RESET, 1); |
| |
| ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, |
| CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); |
| if (ret) |
| printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__); |
| |
| return 0; |
| } |
| |
| static int setup_fec(int fec_id) |
| { |
| struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs |
| = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; |
| int ret; |
| |
| if (0 == fec_id) { |
| /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/ |
| clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, |
| IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); |
| } else { |
| /* Use 50M anatop loopback REF_CLK2 for ENET2, clear gpr1[14], set gpr1[18]*/ |
| clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, |
| IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); |
| } |
| |
| ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); |
| if (ret) |
| return ret; |
| |
| enable_enet_clk(1); |
| |
| return 0; |
| } |
| |
| int board_phy_config(struct phy_device *phydev) |
| { |
| |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); |
| |
| if (phydev->drv->config) |
| phydev->drv->config(phydev); |
| |
| return 0; |
| } |
| #endif |
| |
| #ifdef CONFIG_USB_EHCI_MX6 |
| #define USB_OTHERREGS_OFFSET 0x800 |
| #define UCTRL_PWR_POL (1 << 9) |
| |
| static iomux_v3_cfg_t const usb_otg_pads[] = { |
| MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), |
| }; |
| |
| /* At default the 3v3 enables the MIC2026 for VBUS power */ |
| static void setup_usb(void) |
| { |
| imx_iomux_v3_setup_multiple_pads(usb_otg_pads, |
| ARRAY_SIZE(usb_otg_pads)); |
| } |
| |
| int board_usb_phy_mode(int port) |
| { |
| if (port == 1) |
| return USB_INIT_HOST; |
| else |
| return usb_phy_mode(port); |
| } |
| |
| int board_ehci_hcd_init(int port) |
| { |
| u32 *usbnc_usb_ctrl; |
| |
| if (port > 1) |
| return -EINVAL; |
| |
| usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + |
| port * 4); |
| |
| /* Set Power polarity */ |
| setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); |
| |
| return 0; |
| } |
| #endif |
| |
| int board_early_init_f(void) |
| { |
| setup_iomux_uart(); |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_POWER |
| #define I2C_PMIC 0 |
| static struct pmic *pfuze; |
| int power_init_board(void) |
| { |
| int ret; |
| unsigned int reg, rev_id; |
| |
| ret = power_pfuze3000_init(I2C_PMIC); |
| if (ret) |
| return ret; |
| |
| pfuze = pmic_get("PFUZE3000"); |
| ret = pmic_probe(pfuze); |
| if (ret) |
| return ret; |
| |
| pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); |
| pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); |
| printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); |
| |
| /* disable Low Power Mode during standby mode */ |
| pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, ®); |
| reg |= 0x1; |
| pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg); |
| |
| /* SW1B step ramp up time from 2us to 4us/25mV */ |
| reg = 0x40; |
| pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg); |
| |
| /* SW1B mode to APS/PFM */ |
| reg = 0xc; |
| pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg); |
| |
| /* SW1B standby voltage set to 0.975V */ |
| reg = 0xb; |
| pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg); |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_LDO_BYPASS_CHECK |
| void ldo_mode_set(int ldo_bypass) |
| { |
| unsigned int value; |
| u32 vddarm; |
| |
| struct pmic *p = pfuze; |
| |
| if (!p) { |
| printf("No PMIC found!\n"); |
| return; |
| } |
| |
| /* switch to ldo_bypass mode */ |
| if (ldo_bypass) { |
| prep_anatop_bypass(); |
| /* decrease VDDARM to 1.275V */ |
| pmic_reg_read(pfuze, PFUZE3000_SW1BVOLT, &value); |
| value &= ~0x1f; |
| value |= PFUZE3000_SW1AB_SETP(12750); |
| pmic_reg_write(pfuze, PFUZE3000_SW1BVOLT, value); |
| |
| set_anatop_bypass(1); |
| vddarm = PFUZE3000_SW1AB_SETP(11750); |
| |
| pmic_reg_read(pfuze, PFUZE3000_SW1BVOLT, &value); |
| value &= ~0x1f; |
| value |= vddarm; |
| pmic_reg_write(pfuze, PFUZE3000_SW1BVOLT, value); |
| |
| finish_anatop_bypass(); |
| |
| printf("switch to ldo_bypass mode!\n"); |
| } |
| } |
| #endif |
| #endif |
| |
| int board_init(void) |
| { |
| /* Address of boot parameters */ |
| gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| |
| #ifdef CONFIG_SYS_I2C_MXC |
| setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); |
| #endif |
| |
| #ifdef CONFIG_FEC_MXC |
| setup_fec(CONFIG_FEC_ENET_DEV); |
| #endif |
| |
| #ifdef CONFIG_SYS_USE_NAND |
| setup_gpmi_nand(); |
| #endif |
| |
| #ifdef CONFIG_USB_EHCI_MX6 |
| setup_usb(); |
| #endif |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_CMD_BMODE |
| static const struct boot_mode board_boot_modes[] = { |
| /* 4 bit bus width */ |
| {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, |
| {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, |
| {NULL, 0}, |
| }; |
| #endif |
| |
| int board_late_init(void) |
| { |
| #ifdef CONFIG_CMD_BMODE |
| add_board_boot_modes(board_boot_modes); |
| #endif |
| |
| #ifdef CONFIG_ENV_IS_IN_MMC |
| board_late_mmc_init(); |
| #endif |
| |
| set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); |
| |
| return 0; |
| } |
| |
| u32 get_board_rev(void) |
| { |
| return get_cpu_rev(); |
| } |
| |
| void version_detection(void) |
| { |
| setup_iomux_version_detection(); |
| gpio_direction_input(VERSION_DET_DDR_SIZE); |
| if (gpio_get_value(VERSION_DET_DDR_SIZE)) |
| printf("DRAM size is 512MB \r\n"); |
| else |
| printf("DRAM size is 256MB \r\n"); |
| } |
| int checkboard(void) |
| { |
| version_detection(); |
| puts("Board: PicoSOM i.mx6UL\n"); |
| return 0; |
| } |
| |
| #ifdef CONFIG_FSL_FASTBOOT |
| #ifdef CONFIG_ANDROID_RECOVERY |
| int is_recovery_key_pressing(void) |
| { |
| /* No key defined for this board */ |
| return 0; |
| } |
| #endif /*CONFIG_ANDROID_RECOVERY*/ |
| #endif /*CONFIG_FSL_FASTBOOT*/ |