diff --git a/board/freescale/imx8mq_phanbell/spl.c b/board/freescale/imx8mq_phanbell/spl.c
index da7c21e..e8c3b8b 100644
--- a/board/freescale/imx8mq_phanbell/spl.c
+++ b/board/freescale/imx8mq_phanbell/spl.c
@@ -174,8 +174,32 @@
 	p = pmic_get("BD71837");
 	pmic_probe(p);
 
-	/* Set BUCK5 output for DRAM to 1.1V */
-	pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x5);
+	/* Unlock reg */
+	pmic_reg_write(p, BD71837_REGLOCK, 0x1);
+
+	/* Set BUCK5 output for DRAM to 1.0V */
+	/* 0.70,0.80,0.90,1.00, 1.05,1.10,1.20,1.35 */
+	pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x3);
+
+	/* Set BUCK3 output for VDD_GPU_0V9 to 0.90V */
+	/* 0.7-1.3 (10mVstep) */
+	pmic_reg_write(p, BD71837_BUCK3_VOLT_RUN, 0x14);
+
+	/* Set BUCK4 output for VDD_VPU_0V9 to 0.90V */
+	/* 0.7-1.3 (10mVstep) */
+	pmic_reg_write(p, BD71837_BUCK4_VOLT_RUN, 0x14);
+
+	/* Set BUCK2 output for VDD_ARM_0V9 to 0.90V */
+	/* 0.7-1.3 (10mVstep) */
+	pmic_reg_write(p, BD71837_BUCK2_VOLT_RUN, 0x14);
+
+	/* Set BUCK1 output for VDD_SOC_0V9 to 0.90V */
+	/* 0.7-1.3 (10mVstep) */
+	pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x14);
+
+	/* lock the PMIC regs */
+	pmic_reg_write(p, BD71837_REGLOCK, 0x11);
+
 	return 0;
 }
 #endif