| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright 2018 NXP |
| */ |
| |
| /dts-v1/; |
| |
| /* First 128KB is for PSCI ATF. */ |
| /memreserve/ 0x40000000 0x00020000; |
| |
| #include "fsl-imx8mq.dtsi" |
| |
| / { |
| model = "Freescale i.MX8MQ EVK"; |
| compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; |
| |
| chosen { |
| bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; |
| stdout-path = &uart1; |
| }; |
| |
| regulators { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| reg_usdhc2_vmmc: usdhc2_vmmc { |
| compatible = "regulator-fixed"; |
| regulator-name = "VSD_3V3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| }; |
| |
| pwmleds { |
| compatible = "pwm-leds"; |
| |
| ledpwm2 { |
| label = "PWM2"; |
| pwms = <&pwm2 0 50000>; |
| max-brightness = <255>; |
| }; |
| }; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| |
| imx8mq-evk { |
| pinctrl_fec1: fec1grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 |
| MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 |
| MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f |
| MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f |
| MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f |
| MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f |
| MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 |
| MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 |
| MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 |
| MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 |
| MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f |
| MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 |
| MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 |
| MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f |
| MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f |
| MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f |
| >; |
| }; |
| |
| pinctrl_i2c2: i2c2grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067 |
| MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067 |
| >; |
| }; |
| |
| pinctrl_i2c1_gpio: i2c1grp-gpio { |
| fsl,pins = < |
| MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x7f |
| MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x7f |
| >; |
| }; |
| |
| pinctrl_i2c2_gpio: i2c2grp-gpio { |
| fsl,pins = < |
| MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x7f |
| MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x7f |
| >; |
| }; |
| |
| pinctrl_pwm2: pwm2grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 |
| >; |
| }; |
| |
| pinctrl_qspi: qspigrp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 |
| MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 |
| MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 |
| MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 |
| MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 |
| MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 |
| |
| >; |
| }; |
| |
| pinctrl_uart1: uart1grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 |
| MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 |
| >; |
| }; |
| |
| pinctrl_uart3: uart3grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 |
| MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 |
| MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 |
| MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 |
| MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x49 |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 |
| MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 |
| MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 |
| MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc1_100mhz: usdhc1grp100mhz { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d |
| MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd |
| MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd |
| MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd |
| MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd |
| MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd |
| MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd |
| MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd |
| MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd |
| MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd |
| MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d |
| MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc1_200mhz: usdhc1grp200mhz { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f |
| MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf |
| MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf |
| MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf |
| MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf |
| MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf |
| MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf |
| MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf |
| MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf |
| MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf |
| MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f |
| MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc2_gpio: usdhc2grpgpio { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 |
| MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 |
| MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 |
| MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 |
| MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 |
| MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 |
| MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 |
| MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2grp100mhz { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d |
| MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd |
| MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd |
| MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd |
| MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd |
| MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd |
| MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2grp200mhz { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f |
| MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf |
| MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf |
| MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf |
| MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf |
| MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf |
| MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 |
| >; |
| }; |
| |
| pinctrl_sai2: sai2grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 |
| MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 |
| MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 |
| MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 |
| MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 |
| >; |
| }; |
| |
| pinctrl_wdog: wdoggrp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 |
| >; |
| }; |
| }; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec1>; |
| phy-mode = "rgmii-id"; |
| phy-handle = <ðphy0>; |
| fsl,magic-packet; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <0>; |
| at803x,led-act-blind-workaround; |
| at803x,eee-disabled; |
| }; |
| }; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| pinctrl-1 = <&pinctrl_i2c1_gpio>; |
| scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; |
| sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| |
| pmic: pfuze100@08 { |
| compatible = "fsl,pfuze100"; |
| reg = <0x08>; |
| |
| regulators { |
| sw1a_reg: sw1ab { |
| regulator-min-microvolt = <300000>; |
| regulator-max-microvolt = <1875000>; |
| regulator-always-on; |
| }; |
| |
| sw1c_reg: sw1c { |
| regulator-min-microvolt = <300000>; |
| regulator-max-microvolt = <1875000>; |
| regulator-always-on; |
| }; |
| |
| sw2_reg: sw2 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| sw3a_reg: sw3ab { |
| regulator-min-microvolt = <400000>; |
| regulator-max-microvolt = <1975000>; |
| regulator-always-on; |
| }; |
| |
| sw4_reg: sw4 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| swbst_reg: swbst { |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5150000>; |
| }; |
| |
| snvs_reg: vsnvs { |
| regulator-min-microvolt = <1000000>; |
| regulator-max-microvolt = <3000000>; |
| regulator-always-on; |
| }; |
| |
| vref_reg: vrefddr { |
| regulator-always-on; |
| }; |
| |
| vgen1_reg: vgen1 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1550000>; |
| }; |
| |
| vgen2_reg: vgen2 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1550000>; |
| regulator-always-on; |
| }; |
| |
| vgen3_reg: vgen3 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen4_reg: vgen4 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen5_reg: vgen5 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen6_reg: vgen6 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| }; |
| }; |
| }; |
| |
| &i2c2 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c2>; |
| pinctrl-1 = <&pinctrl_i2c2_gpio>; |
| scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; |
| sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; |
| status = "disabled"; |
| }; |
| |
| &pwm2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pwm2>; |
| status = "okay"; |
| }; |
| |
| &uart1 { /* console */ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>; |
| assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; |
| status = "okay"; |
| }; |
| |
| &lcdif { |
| status = "okay"; |
| disp-dev = "mipi_dsi_northwest"; |
| display = <&display0>; |
| |
| display0: display@0 { |
| bits-per-pixel = <24>; |
| bus-width = <24>; |
| |
| display-timings { |
| native-mode = <&timing0>; |
| timing0: timing0 { |
| clock-frequency = <9200000>; |
| hactive = <480>; |
| vactive = <272>; |
| hfront-porch = <8>; |
| hback-porch = <4>; |
| hsync-len = <41>; |
| vback-porch = <2>; |
| vfront-porch = <4>; |
| vsync-len = <10>; |
| |
| hsync-active = <0>; |
| vsync-active = <0>; |
| de-active = <1>; |
| pixelclk-active = <0>; |
| }; |
| }; |
| }; |
| }; |
| |
| &qspi { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_qspi>; |
| status = "okay"; |
| |
| flash0: n25q256a@0 { |
| reg = <0>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "spi-flash"; |
| spi-max-frequency = <29000000>; |
| spi-nor,ddr-quad-read-dummy = <6>; |
| }; |
| }; |
| |
| &usdhc1 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| pinctrl-1 = <&pinctrl_usdhc1_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc1_200mhz>; |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; |
| bus-width = <4>; |
| cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; |
| vmmc-supply = <®_usdhc2_vmmc>; |
| status = "okay"; |
| }; |
| |
| &usb3_phy0 { |
| status = "okay"; |
| }; |
| |
| &usb3_0 { |
| status = "okay"; |
| }; |
| |
| &usb_dwc3_0 { |
| status = "okay"; |
| dr_mode = "peripheral"; |
| }; |
| |
| &usb3_phy1 { |
| status = "okay"; |
| }; |
| |
| &usb3_1 { |
| status = "okay"; |
| }; |
| |
| &usb_dwc3_1 { |
| status = "okay"; |
| dr_mode = "host"; |
| }; |
| |
| &wdog1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wdog>; |
| fsl,ext-reset-output; |
| status = "okay"; |
| }; |
