commit c00d0012f5d6aa3987f5465caf8b6ead5ac919ff
author Bin Meng <bmeng.cn@gmail.com> Mon Oct 08 06:55:56 2018 -0700
committer York Sun <york.sun@nxp.com> Mon Oct 29 13:13:33 2018 -0700
tree b6adcba67c2bf5b7173d63025a6a9ee504fa2b91
parent 4eaf7f525a0874a1eff0f5666004896cc5c89fa3

powerpc: t1040: Correct RCW MAC2_GMII_SEL value

Per T1040RM (Rev. 1, 08/2015), the value of
FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT is wrong
and should be 0x00000080 (bit 440 in the RCW).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

arch/powerpc/include/asm/immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 7995093..8ec2a38 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1789,7 +1789,7 @@
 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII	0x20000000
 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL	0x00000080
 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH	0x00000000
-#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT	0x80000000
+#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT	0x00000080
 #define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET	0x28
 #define PXCKEN_MASK	0x80000000
 #define PXCK_MASK	0x00FF0000