diff --git a/CHANGELOG b/CHANGELOG
index b77eec7..08f625a 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,162 @@
+commit b3f9ec86e388207fd03dcdf7b145b9ed080bf024
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Jun 19 17:22:44 2007 +0200
+
+    ppc4xx: Add bootstrap command for AMCC Sequoia (440EPx) eval board
+
+    This patch adds a board command to configure the I2C bootstrap EEPROM
+    values. Right now 533 and 667MHz are supported for booting either via NOR
+    or NAND FLASH. Here the usage:
+
+    => bootstrap 533 nor	;to configure the board for 533MHz NOR booting
+    => bootstrap 667 nand	;to configure the board for 667MHz NNAND booting
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit df8a24cdd30151505cf57bbee5289e91bf53bd1b
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Jun 19 16:42:31 2007 +0200
+
+    [ppc4xx] Fix problem with NAND booting on AMCC Acadia
+
+    The latest changes showed a problem with the location of the NAND-SPL
+    image in the OCM and the init-data area (incl. cache). This patch
+    fixes this problem.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 86ba99e34194394052d24c04dc40d1263d29a26f
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Jun 19 16:40:58 2007 +0200
+
+    [ppc4xx] Change board/amcc/acadia/cpr.c to pll.c
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit e73846b7cf1e29ae635bf9bb5570269663df2ee5
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Jun 15 11:33:41 2007 +0200
+
+    [ppc4xx] Change lwmon5 port to work with recent 440 exception rework
+
+    Now CONFIG_440 has to be defined in all PPC440 board config files.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit efa35cf12d914d4caba942acd5a6c45f217de302
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date:	Fri Jun 15 11:19:28 2007 +0200
+
+    ppc4xx: Clean up 440 exceptions handling
+
+    - Introduced dedicated switches for building 440 and 405 images required
+      for 440-specific machine instructions like 'rfmci' etc.
+
+    - Exception vectors moved to the proper location (_start moved away from
+      the critical exception handler space, which it occupied)
+
+    - CriticalInput now serviced (with default handler)
+
+    - MachineCheck properly serviced (added a dedicated handler and return
+      subroutine)
+
+    - Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused,
+      unhandled and those not relevant for 4xx were eliminated)
+
+    - Eliminated Linux leftovers, removed dead code
+
+    Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+    Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit b765ffb773f5a3cd5aa94ec76b6a05276b8cd5b2
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Jun 15 08:18:01 2007 +0200
+
+    [ppc4xx] Add initial lwmon5 board support
+
+    This patch adds initial support for the Liebherr lwmon5 board euqipped
+    with an AMCC 440EPx PowerPC.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 85f737376d5ff3d5f0d45a8b657686326d175307
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Jun 15 07:39:43 2007 +0200
+
+    [ppc4xx] Extend 44x GPIO setup with default output state
+
+    The board config array CFG_440_GPIO_TABLE for the ppc440 GPIO setup
+    is extended with the default GPIO output state (level).
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit dbca208518e5e7f01a6420588d1cd6e60db74c2b
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Jun 14 11:14:32 2007 +0200
+
+    [ppc4xx] Extend program_tlb() with virtual & physical addresses
+
+    Now program_tlb() allows to program a TLB (or multiple) with
+    different virtual and physical addresses. With this change, now one
+    physical region (e.g. SDRAM) can be mapped 2 times, once with caches
+    diabled and once with caches enabled.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 9912121f7ed804ea58fd62f3f230b5dcfc357d88
+Author: Detlev Zundel <dzu@denx.de>
+Date:	Wed May 23 19:02:41 2007 +0200
+
+    Change 'repeatable' attribute of some commands to sensible values.
+
+    Most prominently this changes 'erase' to be non-repeatable.
+
+    Signed-off-by: Detlev Zundel <dzu@denx.de>
+
+commit 5afb202093f6a001797db92cf695b93a70ea9ab4
+Author: Detlev Zundel <dzu@denx.de>
+Date:	Wed May 23 18:47:48 2007 +0200
+
+    Fix 'run' not to continue after interrupted command
+
+    Signed-off-by: Detlev Zundel <dzu@denx.de>
+
+commit 8f8416fada9faf94b9a92f21fe6000643cb521d5
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Fri Jun 8 14:52:22 2007 +0200
+
+    TQM5200: Add Flat Device Tree support, update default env. accordingly.
+
+    Signed-off-by: Jan Wrobel <wrr@semihalf.com>
+    Acked-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit 9045f33c023f698660a2e45d1b2194c0711abebc
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Fri Jun 8 10:24:58 2007 +0200
+
+    Fix config problems on SC3 board; make ide_reset_timeout work.
+
+commit fba3fb0449b8a54542aed1e729de76e7f5a2ff1b
+Author: Benoît Monin <bmonin@adeneo.eu>
+Date:	Fri Jun 8 09:55:24 2007 +0200
+
+    [PATCH] fix gpio setting when using CFG_440_GPIO_TABLE
+
+    Set the correct value in GPIOx_TCR when configuring the gpio
+    with CFG_440_GPIO_TABLE.
+
+    Signed-off-by: Benoit Monin <bmonin@adeneo.eu>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 725671ccd2cd04c9ebc50c9e5a94dd8cbade66b7
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Jun 6 16:26:56 2007 +0200
+
+    Coding Style cleanup; generate new CHANGELOG file.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit c440bfe6d6d92d66478a7e84402b31f48413617b
 Author: Stefan Roese <sr@denx.de>
 Date:	Wed Jun 6 11:42:13 2007 +0200
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index 69b45ac..b303ec7 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -34,9 +34,9 @@
 	u32 sdr0_pfc1, sdr0_pfc2;
 	u32 reg;
 
-        /* PLB Write pipelining disabled. Denali Core workaround */
-      	mtdcr(plb0_acr, 0xDE000000);
-      	mtdcr(plb1_acr, 0xDE000000);
+	/* PLB Write pipelining disabled. Denali Core workaround */
+	mtdcr(plb0_acr, 0xDE000000);
+	mtdcr(plb1_acr, 0xDE000000);
 
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
@@ -86,9 +86,9 @@
 	mtsdr(SDR0_PFC4, 0x80000000);
 
 	/* PCI arbiter disabled */
-        /* PCI Host Configuration disbaled */
+	/* PCI Host Configuration disbaled */
 	mfsdr(sdr_pci0, reg);
-        reg = 0;
+	reg = 0;
 	mtsdr(sdr_pci0, 0x00000000 | reg);
 
 	gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
index d2eb5bd..85811ad 100644
--- a/board/lwmon5/sdram.c
+++ b/board/lwmon5/sdram.c
@@ -1,10 +1,10 @@
 /*
  * (C) Copyright 2006
- * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Sylvie Gohl,		    AMCC/IBM, gohl.sylvie@fr.ibm.com
  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
+ * Thierry Roman,	    AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder,	    AMCC/IBM, rob.snyder@fr.ibm.com
  *
  * (C) Copyright 2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
@@ -49,9 +49,9 @@
  * everything correctly.
  */
 #ifdef CFG_ENABLE_SDRAM_CACHE
-#define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
+#define MY_TLB_WORD2_I_ENABLE	0			/* enable caching on SDRAM */
 #else
-#define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
+#define MY_TLB_WORD2_I_ENABLE	TLB_WORD2_I_ENABLE	/* disable caching on SDRAM */
 #endif
 
 void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
@@ -325,8 +325,8 @@
 
 	debug("DQS calibration - Window detected:\n");
 	debug("max_passing_cases = %d\n", max_passing_cases);
-	debug("wr_dqs_shift      = %d\n", wr_dqs_shift);
-	debug("dll_dqs_delay_X   = %d\n", dll_dqs_delay_X);
+	debug("wr_dqs_shift	 = %d\n", wr_dqs_shift);
+	debug("dll_dqs_delay_X	 = %d\n", dll_dqs_delay_X);
 	debug("dll_dqs_delay_X window = %d - %d\n",
 	      dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
 
@@ -561,16 +561,16 @@
 
 	wait_for_dlllock();
 
-        /*
+	/*
 	 * Program tlb entries for this size (dynamic)
 	 */
-        program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE);
+	program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE);
 
 	/*
 	 * Setup 2nd TLB with same physical address but different virtual address
 	 * with cache enabled. This is done for fast ECC generation.
 	 */
-        program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
+	program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
 
 #ifdef CONFIG_DDR_DATA_EYE
 	/*
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 16df1e7..a46197d 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -22,26 +22,27 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
-/*------------------------------------------------------------------------------+ */
-/* */
-/*	 This source code has been made available to you by IBM on an AS-IS */
-/*	 basis.	 Anyone receiving this source is licensed under IBM */
-/*	 copyrights to use it in any way he or she deems fit, including */
-/*	 copying it, modifying it, compiling it, and redistributing it either */
-/*	 with or without modifications.	 No license under IBM patents or */
-/*	 patent applications is to be implied by the copyright license. */
-/* */
-/*	 Any user of this software should understand that IBM cannot provide */
-/*	 technical support for this software and will not be responsible for */
-/*	 any consequences resulting from the use of this software. */
-/* */
-/*	 Any person who transfers this source code or any derivative work */
-/*	 must include the IBM copyright notice, this paragraph, and the */
-/*	 preceding two paragraphs in the transferred software. */
-/* */
-/*	 COPYRIGHT   I B M   CORPORATION 1995 */
-/*	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
-/*------------------------------------------------------------------------------- */
+/*------------------------------------------------------------------------------+
+ *
+ *	 This source code has been made available to you by IBM on an AS-IS
+ *	 basis.	 Anyone receiving this source is licensed under IBM
+ *	 copyrights to use it in any way he or she deems fit, including
+ *	 copying it, modifying it, compiling it, and redistributing it either
+ *	 with or without modifications.	 No license under IBM patents or
+ *	 patent applications is to be implied by the copyright license.
+ *
+ *	 Any user of this software should understand that IBM cannot provide
+ *	 technical support for this software and will not be responsible for
+ *	 any consequences resulting from the use of this software.
+ *
+ *	 Any person who transfers this source code or any derivative work
+ *	 must include the IBM copyright notice, this paragraph, and the
+ *	 preceding two paragraphs in the transferred software.
+ *
+ *	 COPYRIGHT   I B M   CORPORATION 1995
+ *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *-------------------------------------------------------------------------------
+ */
 
 /*  U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
  *
@@ -110,11 +111,11 @@
 # endif
 #endif /* CFG_INIT_DCACHE_CS */
 
-#define function_prolog(func_name)      .text; \
+#define function_prolog(func_name)	.text; \
 					.align 2; \
 					.globl func_name; \
 					func_name:
-#define function_epilog(func_name)      .type func_name,@function; \
+#define function_epilog(func_name)	.type func_name,@function; \
 					.size func_name,.-func_name
 
 /* We don't want the  MMU yet.
@@ -295,7 +296,7 @@
 	li	r1,0x0c00
 	mtspr	ivor8,r1	/* System call */
 	li	r1,0x0a00
-	mtspr   ivor9,r1	/* Auxiliary Processor unavailable */
+	mtspr	ivor9,r1	/* Auxiliary Processor unavailable */
 	li	r1,0x0900
 	mtspr	ivor10,r1	/* Decrementer */
 	li	r1,0x1300
@@ -514,9 +515,9 @@
 
 #ifdef CONFIG_440
 /* Machine check */
-        MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+	MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 #else
-        CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+	CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 #endif /* CONFIG_440 */
 
 /* Data Storage exception. */
@@ -895,15 +896,15 @@
 	mtdcr	ocmplb3cr2,r3		/* Set PLB Access */
 	isync
 
-	lis	r3,CFG_OCM_DATA_ADDR@h  /* OCM location */
+	lis	r3,CFG_OCM_DATA_ADDR@h	/* OCM location */
 	ori	r3,r3,CFG_OCM_DATA_ADDR@l
-	ori	r3,r3,0x0270            /* 16K for Bank 1, R/W/Enable */
-	mtdcr	ocmdscr1, r3            /* Set Data Side */
-	mtdcr	ocmiscr1, r3            /* Set Instruction Side */
+	ori	r3,r3,0x0270		/* 16K for Bank 1, R/W/Enable */
+	mtdcr	ocmdscr1, r3		/* Set Data Side */
+	mtdcr	ocmiscr1, r3		/* Set Instruction Side */
 	ori	r3,r3,0x4000		/* Add 0x4000 for bank 2 */
-	mtdcr	ocmdscr2, r3            /* Set Data Side */
-	mtdcr	ocmiscr2, r3            /* Set Instruction Side */
-	addis	r3,0,0x0800             /* OCM Data Parity Disable - 1 Wait State */
+	mtdcr	ocmdscr2, r3		/* Set Data Side */
+	mtdcr	ocmiscr2, r3		/* Set Instruction Side */
+	addis	r3,0,0x0800		/* OCM Data Parity Disable - 1 Wait State */
 	mtdcr	ocmdsisdpc,r3
 
 	isync
@@ -922,7 +923,7 @@
 	mtdcr	ocmdscntl, r4		/* set data-side IRAM config */
 	isync
 
-	lis	r3,CFG_OCM_DATA_ADDR@h  /* OCM location */
+	lis	r3,CFG_OCM_DATA_ADDR@h	/* OCM location */
 	ori	r3,r3,CFG_OCM_DATA_ADDR@l
 	mtdcr	ocmdsarc, r3
 	addis	r4, 0, 0xC000		/* OCM data area enabled */
@@ -1170,8 +1171,8 @@
 	REST_GPR(31, r1)
 	lwz	r2,_NIP(r1)	/* Restore environment */
 	lwz	r0,_MSR(r1)
-        mtspr   csrr0,r2
-        mtspr   csrr1,r0
+	mtspr	csrr0,r2
+	mtspr	csrr1,r0
 	lwz	r0,GPR0(r1)
 	lwz	r2,GPR2(r1)
 	lwz	r1,GPR1(r1)
@@ -1180,34 +1181,34 @@
 
 #ifdef CONFIG_440
 mck_return:
-        mfmsr   r28             /* Disable interrupts */
-        li      r4,0
-        ori     r4,r4,MSR_EE
-        andc    r28,r28,r4
-        SYNC                    /* Some chip revs need this... */
-        mtmsr   r28
-        SYNC
-        lwz     r2,_CTR(r1)
-        lwz     r0,_LINK(r1)
-        mtctr   r2
-        mtlr    r0
-        lwz     r2,_XER(r1)
-        lwz     r0,_CCR(r1)
-        mtspr   XER,r2
-        mtcrf   0xFF,r0
-        REST_10GPRS(3, r1)
-        REST_10GPRS(13, r1)
-        REST_8GPRS(23, r1)
-        REST_GPR(31, r1)
-        lwz     r2,_NIP(r1)     /* Restore environment */
-        lwz     r0,_MSR(r1)
-        mtspr   mcsrr0,r2
-        mtspr   mcsrr1,r0
-        lwz     r0,GPR0(r1)
-        lwz     r2,GPR2(r1)
-        lwz     r1,GPR1(r1)
-        SYNC
-        rfmci
+	mfmsr	r28		/* Disable interrupts */
+	li	r4,0
+	ori	r4,r4,MSR_EE
+	andc	r28,r28,r4
+	SYNC			/* Some chip revs need this... */
+	mtmsr	r28
+	SYNC
+	lwz	r2,_CTR(r1)
+	lwz	r0,_LINK(r1)
+	mtctr	r2
+	mtlr	r0
+	lwz	r2,_XER(r1)
+	lwz	r0,_CCR(r1)
+	mtspr	XER,r2
+	mtcrf	0xFF,r0
+	REST_10GPRS(3, r1)
+	REST_10GPRS(13, r1)
+	REST_8GPRS(23, r1)
+	REST_GPR(31, r1)
+	lwz	r2,_NIP(r1)	/* Restore environment */
+	lwz	r0,_MSR(r1)
+	mtspr	mcsrr0,r2
+	mtspr	mcsrr1,r0
+	lwz	r0,GPR0(r1)
+	lwz	r2,GPR2(r1)
+	lwz	r1,GPR1(r1)
+	SYNC
+	rfmci
 #endif /* CONFIG_440 */
 
 
@@ -1222,11 +1223,11 @@
 #ifdef CONFIG_440
        .globl  dcache_disable
 dcache_disable:
-        blr
+	blr
 
-        .globl  dcache_status
+	.globl	dcache_status
 dcache_status:
-        blr
+	blr
 #else
 flush_dcache:
 	addis	r9,r0,0x0002		/* set mask for EE and CE msr bits */
@@ -1616,32 +1617,32 @@
 
 #ifdef CONFIG_440
 	li	r7, .L_FPUnavailable - _start + _START_OFFSET
-        bl      trap_reloc
+	bl	trap_reloc
 
 	li	r7, .L_Decrementer - _start + _START_OFFSET
-        bl      trap_reloc
+	bl	trap_reloc
 
 	li	r7, .L_APU - _start + _START_OFFSET
-        bl      trap_reloc
+	bl	trap_reloc
 
-	li      r7, .L_InstructionTLBError - _start + _START_OFFSET
-        bl      trap_reloc
+	li	r7, .L_InstructionTLBError - _start + _START_OFFSET
+	bl	trap_reloc
 
-        li      r7, .L_DataTLBError - _start + _START_OFFSET
-        bl      trap_reloc
+	li	r7, .L_DataTLBError - _start + _START_OFFSET
+	bl	trap_reloc
 #else /* CONFIG_440 */
 	li	r7, .L_PIT - _start + _START_OFFSET
-        bl      trap_reloc
+	bl	trap_reloc
 
 	li	r7, .L_InstructionTLBMiss - _start + _START_OFFSET
-        bl      trap_reloc
+	bl	trap_reloc
 
 	li	r7, .L_DataTLBMiss - _start + _START_OFFSET
-        bl      trap_reloc
+	bl	trap_reloc
 #endif /* CONFIG_440 */
 
-        li      r7, .L_DebugBreakpoint - _start + _START_OFFSET
-        bl      trap_reloc
+	li	r7, .L_DebugBreakpoint - _start + _START_OFFSET
+	bl	trap_reloc
 
 #if !defined(CONFIG_440)
 	addi	r7,r0,0x1000		/* set ME bit (Machine Exceptions) */
@@ -1684,13 +1685,13 @@
 +----------------------------------------------------------------------------*/
 	function_prolog(dcbz_area)
 	rlwinm. r5,r4,0,27,31
-	rlwinm  r5,r4,27,5,31
-	beq     ..d_ra2
-	addi    r5,r5,0x0001
-..d_ra2:mtctr   r5
-..d_ag2:dcbz    r0,r3
-	addi    r3,r3,32
-	bdnz    ..d_ag2
+	rlwinm	r5,r4,27,5,31
+	beq	..d_ra2
+	addi	r5,r5,0x0001
+..d_ra2:mtctr	r5
+..d_ag2:dcbz	r0,r3
+	addi	r3,r3,32
+	bdnz	..d_ag2
 	sync
 	blr
 	function_epilog(dcbz_area)
@@ -1699,26 +1700,26 @@
 | dflush.  Assume 32K at vector address is cachable.
 +----------------------------------------------------------------------------*/
 	function_prolog(dflush)
-	mfmsr   r9
-	rlwinm  r8,r9,0,15,13
-	rlwinm  r8,r8,0,17,15
-	mtmsr   r8
-	addi    r3,r0,0x0000
-	mtspr   dvlim,r3
-	mfspr   r3,ivpr
-	addi    r4,r0,1024
-	mtctr   r4
+	mfmsr	r9
+	rlwinm	r8,r9,0,15,13
+	rlwinm	r8,r8,0,17,15
+	mtmsr	r8
+	addi	r3,r0,0x0000
+	mtspr	dvlim,r3
+	mfspr	r3,ivpr
+	addi	r4,r0,1024
+	mtctr	r4
 ..dflush_loop:
-	lwz     r6,0x0(r3)
-	addi    r3,r3,32
-	bdnz    ..dflush_loop
-	addi    r3,r3,-32
-	mtctr   r4
-..ag:   dcbf    r0,r3
-	addi    r3,r3,-32
-	bdnz    ..ag
+	lwz	r6,0x0(r3)
+	addi	r3,r3,32
+	bdnz	..dflush_loop
+	addi	r3,r3,-32
+	mtctr	r4
+..ag:	dcbf	r0,r3
+	addi	r3,r3,-32
+	bdnz	..ag
 	sync
-	mtmsr   r9
+	mtmsr	r9
 	blr
 	function_epilog(dflush)
 #endif /* CONFIG_440 */
diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c
index 54659d3..7c44a29 100644
--- a/cpu/ppc4xx/traps.c
+++ b/cpu/ppc4xx/traps.c
@@ -89,22 +89,22 @@
 void
 print_backtrace(unsigned long *sp)
 {
-        int cnt = 0;
-        unsigned long i;
+	int cnt = 0;
+	unsigned long i;
 
-        printf("Call backtrace: ");
-        while (sp) {
-                if ((uint)sp > END_OF_MEM)
-                        break;
+	printf("Call backtrace: ");
+	while (sp) {
+		if ((uint)sp > END_OF_MEM)
+			break;
 
-                i = sp[1];
-                if (cnt++ % 7 == 0)
-                        printf("\n");
-                printf("%08lX ", i);
-                if (cnt > 32) break;
-                sp = (unsigned long *)*sp;
-        }
-        printf("\n");
+		i = sp[1];
+		if (cnt++ % 7 == 0)
+			printf("\n");
+		printf("%08lX ", i);
+		if (cnt > 32) break;
+		sp = (unsigned long *)*sp;
+	}
+	printf("\n");
 }
 
 void show_regs(struct pt_regs * regs)
@@ -121,14 +121,12 @@
 
 	printf("\n");
 	for (i = 0;  i < 32;  i++) {
-		if ((i % 8) == 0)
-		{
+		if ((i % 8) == 0) {
 			printf("GPR%02d: ", i);
 		}
 
 		printf("%08lX ", regs->gpr[i]);
-		if ((i % 8) == 7)
-		{
+		if ((i % 8) == 7) {
 			printf("\n");
 		}
 	}
@@ -147,7 +145,7 @@
 MachineCheckException(struct pt_regs *regs)
 {
 	unsigned long fixup, val;
-	
+
 	/* Probing PCI using config cycles cause this exception
 	 * when a device is not present.  Catch it and return to
 	 * the PCI exception handler.
@@ -172,16 +170,16 @@
 	if (val& ESR_IMCP) {
 		printf("Instruction");
 		mtspr(ESR, val & ~ESR_IMCP);
-	} else
+	} else {
 		printf("Data");
+	}
 	printf(" machine check.\n");
 
 #elif defined(CONFIG_440)
 	if (val& ESR_IMCP){
 		printf("Instruction Synchronous Machine Check exception\n");
 		mtspr(SPRN_ESR, val & ~ESR_IMCP);
-	}
-        else { 
+	} else {
 		val = mfspr(MCSR);
 		if (val & MCSR_IB)
 			printf("Instruction Read PLB Error\n");
@@ -297,17 +295,17 @@
 
 	__asm__ __volatile__(			\
 		"1:	lwz %0,0(%1)\n"		\
-						"	eieio\n"		\
-						"	li %0,0\n"		\
-						"2:\n"				\
-						".section .fixup,\"ax\"\n"	\
-						"3:	li %0,-1\n"		\
-						"	b 2b\n"			\
-						".section __ex_table,\"a\"\n"	\
-						"	.align 2\n"		\
-						"	.long 1b,3b\n"		\
-						".text"				\
-						: "=r" (retval) : "r"(addr));
+		"	eieio\n"		\
+		"	li %0,0\n"		\
+		"2:\n"				\
+		".section .fixup,\"ax\"\n"	\
+		"3:	li %0,-1\n"		\
+		"	b 2b\n"			\
+		".section __ex_table,\"a\"\n"	\
+		"	.align 2\n"		\
+		"	.long 1b,3b\n"		\
+		".text"				\
+		: "=r" (retval) : "r"(addr));
 
 	return (retval);
 #endif
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index e6ebe38..cc47a16 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -29,7 +29,7 @@
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
-//#define DEBUG
+
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index f15628a..ad027d6 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -113,11 +113,11 @@
 
 #if  defined(CONFIG_5xx)
 /* Some special purpose registers */
-#define DER	149		/* Debug Enable Register	    	*/
-#define COUNTA	150		/* Breakpoint Counter	    	 	*/
-#define COUNTB	151		/* Breakpoint Counter	    	 	*/
-#define LCTRL1	156		/* Load/Store Support	    	 	*/
-#define LCTRL2	157		/* Load/Store Support	    	 	*/
+#define DER	149		/* Debug Enable Register		*/
+#define COUNTA	150		/* Breakpoint Counter			*/
+#define COUNTB	151		/* Breakpoint Counter			*/
+#define LCTRL1	156		/* Load/Store Support			*/
+#define LCTRL2	157		/* Load/Store Support			*/
 #define ICTRL	158		/* I-Bus Support Control Register	*/
 #define EID	81
 #endif	/* CONFIG_5xx */
@@ -266,39 +266,39 @@
 	addi	r3,r1,STACK_FRAME_OVERHEAD;		\
 	li	r20,MSR_KERNEL;				\
 	rlwimi	r20,r23,0,25,25;			\
-	blrl;	 					\
+	blrl;						\
 .L_ ## label :						\
 	.long	hdlr - _start + _START_OFFSET;		\
 	.long	int_return - _start + _START_OFFSET
 
 #define CRIT_EXCEPTION(n, label, hdlr)				\
-        . = n;							\
+	. = n;							\
 label:								\
-        EXCEPTION_PROLOG(csrr0, csrr1);				\
-        lwz     r3,GOT(transfer_to_handler);			\
-        mtlr    r3;						\
-        addi    r3,r1,STACK_FRAME_OVERHEAD;			\
-        li      r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE));	\
-        rlwimi  r20,r23,0,25,25;				\
-        blrl;							\
+	EXCEPTION_PROLOG(csrr0, csrr1);				\
+	lwz	r3,GOT(transfer_to_handler);			\
+	mtlr	r3;						\
+	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
+	li	r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE));	\
+	rlwimi	r20,r23,0,25,25;				\
+	blrl;							\
 .L_ ## label :							\
-        .long   hdlr - _start + _START_OFFSET;			\
-        .long   crit_return - _start + _START_OFFSET
+	.long	hdlr - _start + _START_OFFSET;			\
+	.long	crit_return - _start + _START_OFFSET
 
 #ifdef CONFIG_440
 #define MCK_EXCEPTION(n, label, hdlr)				\
-        . = n;							\
+	. = n;							\
 label:								\
-        EXCEPTION_PROLOG(MCSRR0, MCSRR1);			\
-        lwz     r3,GOT(transfer_to_handler);			\
-        mtlr    r3;						\
-        addi    r3,r1,STACK_FRAME_OVERHEAD;			\
-        li      r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE));	\
-        rlwimi  r20,r23,0,25,25;				\
-        blrl;							\
+	EXCEPTION_PROLOG(MCSRR0, MCSRR1);			\
+	lwz	r3,GOT(transfer_to_handler);			\
+	mtlr	r3;						\
+	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
+	li	r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE));	\
+	rlwimi	r20,r23,0,25,25;				\
+	blrl;							\
 .L_ ## label :							\
-        .long   hdlr - _start + _START_OFFSET;			\
-        .long   mck_return - _start + _START_OFFSET
+	.long	hdlr - _start + _START_OFFSET;			\
+	.long	mck_return - _start + _START_OFFSET
 #endif /* CONFIG_440  */
 
 #endif	/* __PPC_ASM_TMPL__ */