| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright 2017 NXP |
| */ |
| |
| /dts-v1/; |
| |
| #include "imx7d.dtsi" |
| |
| / { |
| model = "Freescale i.MX7 SabreSD Board"; |
| compatible = "fsl,imx7d-sdb", "fsl,imx7d"; |
| |
| aliases { |
| spi5 = &soft_spi; |
| }; |
| |
| chosen { |
| stdout-path = &uart1; |
| }; |
| |
| memory { |
| reg = <0x80000000 0x80000000>; |
| }; |
| |
| modem_reset: modem-reset { |
| compatible = "gpio-reset"; |
| reset-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; |
| reset-delay-us = <1000>; |
| #reset-cells = <0>; |
| }; |
| |
| soft_spi: soft-spi { |
| compatible = "spi-gpio"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_spi4>; |
| gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; |
| gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; |
| cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; |
| num-chipselects = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| extended_io: gpio-expander@0 { |
| compatible = "fairchild,74hc595"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0>; |
| registers-number = <1>; |
| registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/ |
| spi-max-frequency = <100000>; |
| }; |
| }; |
| |
| reg_usb_otg1_vbus: regulator-usb-otg1-vbus { |
| compatible = "regulator-fixed"; |
| regulator-name = "usb_otg1_vbus"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reg_usb_otg2_vbus: regulator-usb-otg2-vbus { |
| compatible = "regulator-fixed"; |
| regulator-name = "usb_otg2_vbus"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reg_vref_1v8: regulator-vref-1v8 { |
| compatible = "regulator-fixed"; |
| regulator-name = "vref-1v8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| }; |
| |
| reg_can2_3v3: regulator-can2-3v3 { |
| compatible = "regulator-fixed"; |
| regulator-name = "can2-3v3"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexcan2_reg>; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; |
| }; |
| |
| reg_sd1_vmmc: regulator-sd1-vmmc { |
| compatible = "regulator-fixed"; |
| regulator-name = "VDD_SD1"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; |
| startup-delay-us = <200000>; |
| off-on-delay = <20000>; |
| enable-active-high; |
| }; |
| |
| backlight { |
| compatible = "pwm-backlight"; |
| pwms = <&pwm1 0 5000000 0>; |
| brightness-levels = <0 4 8 16 32 64 128 255>; |
| default-brightness-level = <6>; |
| status = "okay"; |
| }; |
| |
| pxp_v4l2_out { |
| compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; |
| status = "okay"; |
| }; |
| |
| sound { |
| compatible = "fsl,imx7d-evk-wm8960", |
| "fsl,imx-audio-wm8960"; |
| model = "wm8960-audio"; |
| cpu-dai = <&sai1>; |
| audio-codec = <&codec>; |
| codec-master; |
| /* JD2: hp detect high for headphone*/ |
| hp-det = <2 0>; |
| hp-det-gpios = <&gpio2 28 0>; |
| audio-routing = |
| "Headphone Jack", "HP_L", |
| "Headphone Jack", "HP_R", |
| "Ext Spk", "SPK_LP", |
| "Ext Spk", "SPK_LN", |
| "Ext Spk", "SPK_RP", |
| "Ext Spk", "SPK_RN", |
| "LINPUT1", "Main MIC", |
| "Main MIC", "MICB"; |
| assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, |
| <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; |
| assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; |
| assigned-clock-rates = <0>, <12288000>; |
| }; |
| |
| sound-hdmi { |
| compatible = "fsl,imx7d-sdb-sii902x", |
| "fsl,imx-audio-sii902x"; |
| model = "sii902x-audio"; |
| cpu-dai = <&sai3>; |
| hdmi-controler = <&sii902x>; |
| }; |
| |
| usdhc2_pwrseq: usdhc2_pwrseq { |
| compatible = "mmc-pwrseq-simple"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_brcm_reg>; |
| reset-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; |
| }; |
| }; |
| |
| &adc1 { |
| vref-supply = <®_vref_1v8>; |
| status = "okay"; |
| }; |
| |
| &adc2 { |
| vref-supply = <®_vref_1v8>; |
| status = "okay"; |
| }; |
| |
| &cpu0 { |
| arm-supply = <&sw1a_reg>; |
| }; |
| |
| &ecspi3 { |
| fsl,spi-num-chipselects = <1>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; |
| cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| |
| tsc2046@0 { |
| compatible = "ti,tsc2046"; |
| reg = <0>; |
| spi-max-frequency = <1000000>; |
| pinctrl-names ="default"; |
| pinctrl-0 = <&pinctrl_tsc2046_pendown>; |
| interrupt-parent = <&gpio2>; |
| interrupts = <29 0>; |
| pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; |
| ti,x-min = /bits/ 16 <0>; |
| ti,x-max = /bits/ 16 <0>; |
| ti,y-min = /bits/ 16 <0>; |
| ti,y-max = /bits/ 16 <0>; |
| ti,pressure-max = /bits/ 16 <0>; |
| ti,x-plate-ohms = /bits/ 16 <400>; |
| wakeup-source; |
| }; |
| }; |
| |
| &clks { |
| assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; |
| assigned-clock-rates = <884736000>; |
| }; |
| |
| &csi1 { |
| csi-mux-mipi = <&gpr 0x14 4>; |
| fsl,mipi-mode; |
| status = "okay"; |
| |
| port { |
| csi_ep: endpoint { |
| remote-endpoint = <&csi_mipi_ep>; |
| }; |
| }; |
| }; |
| |
| &epdc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_epdc0 &pinctrl_enet2_epdc0_en>; |
| V3P3-supply = <&V3P3_reg>; |
| VCOM-supply = <&VCOM_reg>; |
| DISPLAY-supply = <&DISPLAY_reg>; |
| en-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; |
| status = "disabled"; |
| }; |
| |
| &epxp { |
| status = "okay"; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet1>; |
| assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, |
| <&clks IMX7D_ENET_AXI_ROOT_SRC>, |
| <&clks IMX7D_ENET1_TIME_ROOT_SRC>, |
| <&clks IMX7D_ENET1_TIME_ROOT_CLK>, |
| <&clks IMX7D_ENET_AXI_ROOT_CLK>; |
| assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, |
| <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, |
| <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; |
| assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; |
| phy-mode = "rgmii"; |
| phy-handle = <ðphy0>; |
| fsl,magic-packet; |
| phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <0>; |
| }; |
| |
| ethphy1: ethernet-phy@1 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <1>; |
| }; |
| }; |
| }; |
| |
| &fec2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_epdc0_en>; |
| pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; |
| assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, |
| <&clks IMX7D_ENET_AXI_ROOT_SRC>, |
| <&clks IMX7D_ENET2_TIME_ROOT_SRC>, |
| <&clks IMX7D_ENET2_TIME_ROOT_CLK>, |
| <&clks IMX7D_ENET_AXI_ROOT_CLK>; |
| assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, |
| <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, |
| <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; |
| assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; |
| phy-mode = "rgmii"; |
| phy-handle = <ðphy1>; |
| fsl,magic-packet; |
| status = "okay"; |
| }; |
| |
| &flexcan2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexcan2>; |
| xceiver-supply = <®_can2_3v3>; |
| status = "okay"; |
| }; |
| |
| &mipi_csi { |
| clock-frequency = <240000000>; |
| status = "okay"; |
| port { |
| mipi_sensor_ep: endpoint1 { |
| remote-endpoint = <&ov5640_mipi_ep>; |
| data-lanes = <2>; |
| csis-hs-settle = <13>; |
| csis-clk-settle = <2>; |
| csis-wclk; |
| }; |
| |
| csi_mipi_ep: endpoint2 { |
| remote-endpoint = <&csi_ep>; |
| }; |
| }; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| pinctrl-1 = <&pinctrl_i2c1_gpio>; |
| scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; |
| sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| |
| pmic: pfuze3000@08 { |
| compatible = "fsl,pfuze3000"; |
| reg = <0x08>; |
| |
| regulators { |
| sw1a_reg: sw1a { |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <6250>; |
| }; |
| |
| /* use sw1c_reg to align with pfuze100/pfuze200 */ |
| sw1c_reg: sw1b { |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1475000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <6250>; |
| }; |
| |
| sw2_reg: sw2 { |
| regulator-min-microvolt = <1500000>; |
| regulator-max-microvolt = <1850000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| sw3a_reg: sw3 { |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <1650000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| swbst_reg: swbst { |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5150000>; |
| }; |
| |
| snvs_reg: vsnvs { |
| regulator-min-microvolt = <1000000>; |
| regulator-max-microvolt = <3000000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vref_reg: vrefddr { |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vgen1_reg: vldo1 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen2_reg: vldo2 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1550000>; |
| }; |
| |
| vgen3_reg: vccsd { |
| regulator-min-microvolt = <2850000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen4_reg: v33 { |
| regulator-min-microvolt = <2850000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen5_reg: vldo3 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen6_reg: vldo4 { |
| regulator-min-microvolt = <2800000>; |
| regulator-max-microvolt = <2800000>; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| }; |
| |
| &i2c2 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c2>; |
| pinctrl-1 = <&pinctrl_i2c2_gpio>; |
| scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; |
| sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| |
| fxas2100x@20 { |
| compatible = "fsl,fxas2100x"; |
| reg = <0x20>; |
| }; |
| |
| fxos8700@1e { |
| compatible = "fsl,fxos8700"; |
| reg = <0x1e>; |
| }; |
| |
| mpl3115@60 { |
| compatible = "fsl,mpl3115"; |
| reg = <0x60>; |
| }; |
| }; |
| |
| &i2c3 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c3>; |
| pinctrl-1 = <&pinctrl_i2c3_gpio>; |
| scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; |
| sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| sii902x: sii902x@39 { |
| compatible = "SiI,sii902x"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sii902x>; |
| interrupt-parent = <&gpio2>; |
| interrupts = <13 IRQ_TYPE_EDGE_FALLING>; |
| mode_str ="1280x720M@60"; |
| bits-per-pixel = <16>; |
| reg = <0x39>; |
| status = "okay"; |
| }; |
| |
| max17135: max17135@48 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_max17135>; |
| compatible = "maxim,max17135"; |
| reg = <0x48>; |
| status = "disabled"; |
| |
| vneg_pwrup = <1>; |
| gvee_pwrup = <2>; |
| vpos_pwrup = <10>; |
| gvdd_pwrup = <12>; |
| gvdd_pwrdn = <1>; |
| vpos_pwrdn = <2>; |
| gvee_pwrdn = <8>; |
| vneg_pwrdn = <10>; |
| gpio_pmic_pwrgood = <&gpio2 31 0>; |
| gpio_pmic_vcom_ctrl = <&gpio4 14 0>; |
| gpio_pmic_wakeup = <&gpio2 23 0>; |
| gpio_pmic_v3p3 = <&gpio2 30 0>; |
| gpio_pmic_intr = <&gpio2 22 0>; |
| |
| regulators { |
| DISPLAY_reg: DISPLAY { |
| regulator-name = "DISPLAY"; |
| }; |
| |
| GVDD_reg: GVDD { |
| /* 20v */ |
| regulator-name = "GVDD"; |
| }; |
| |
| GVEE_reg: GVEE { |
| /* -22v */ |
| regulator-name = "GVEE"; |
| }; |
| |
| HVINN_reg: HVINN { |
| /* -22v */ |
| regulator-name = "HVINN"; |
| }; |
| |
| HVINP_reg: HVINP { |
| /* 20v */ |
| regulator-name = "HVINP"; |
| }; |
| |
| VCOM_reg: VCOM { |
| regulator-name = "VCOM"; |
| /* Real max value: -500000 */ |
| regulator-max-microvolt = <4325000>; |
| /* Real min value: -4325000 */ |
| regulator-min-microvolt = <500000>; |
| }; |
| |
| VNEG_reg: VNEG { |
| /* -15v */ |
| regulator-name = "VNEG"; |
| }; |
| |
| VPOS_reg: VPOS { |
| /* 15v */ |
| regulator-name = "VPOS"; |
| }; |
| |
| V3P3_reg: V3P3 { |
| regulator-name = "V3P3"; |
| }; |
| }; |
| }; |
| }; |
| |
| &i2c4 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c4>; |
| pinctrl-1 = <&pinctrl_i2c4_gpio>; |
| scl-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; |
| sda-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| |
| codec: wm8960@1a { |
| compatible = "wlf,wm8960"; |
| reg = <0x1a>; |
| clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; |
| clock-names = "mclk"; |
| wlf,shared-lrclk; |
| }; |
| |
| ov5640_mipi: ov5640_mipi@3c { |
| compatible = "ovti,ov5640_mipi"; |
| reg = <0x3c>; |
| clocks = <&clks IMX7D_CLK_DUMMY>; |
| clock-names = "csi_mclk"; |
| csi_id = <0>; |
| pwn-gpios = <&extended_io 6 GPIO_ACTIVE_HIGH>; |
| AVDD-supply = <&vgen6_reg>; |
| mclk = <24000000>; |
| mclk_source = <0>; |
| port { |
| ov5640_mipi_ep: endpoint { |
| remote-endpoint = <&mipi_sensor_ep>; |
| }; |
| }; |
| }; |
| }; |
| |
| &lcdif { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lcdif>; |
| enable-gpio = <&extended_io 7 GPIO_ACTIVE_LOW>; |
| display = <&display0>; |
| status = "okay"; |
| |
| display0: display { |
| bits-per-pixel = <16>; |
| bus-width = <24>; |
| |
| display-timings { |
| native-mode = <&timing0>; |
| |
| timing0: timing0 { |
| clock-frequency = <9200000>; |
| hactive = <480>; |
| vactive = <272>; |
| hfront-porch = <8>; |
| hback-porch = <4>; |
| hsync-len = <41>; |
| vback-porch = <2>; |
| vfront-porch = <4>; |
| vsync-len = <10>; |
| hsync-active = <0>; |
| vsync-active = <0>; |
| de-active = <1>; |
| pixelclk-active = <0>; |
| }; |
| }; |
| }; |
| }; |
| |
| &sai1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sai1>; |
| assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, |
| <&clks IMX7D_SAI1_ROOT_CLK>; |
| assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; |
| assigned-clock-rates = <0>, <36864000>; |
| status = "okay"; |
| }; |
| |
| &sai3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>; |
| assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, |
| <&clks IMX7D_SAI3_ROOT_CLK>; |
| assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; |
| assigned-clock-rates = <0>, <36864000>; |
| status = "okay"; |
| }; |
| |
| &sdma { |
| status = "okay"; |
| }; |
| |
| &pwm1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pwm1>; |
| status = "okay"; |
| }; |
| |
| &pcie { |
| pinctrl-names = "default"; |
| reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>; |
| disable-gpio = <&extended_io 0 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &iomuxc_lpsr { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog_2 &pinctrl_usbotg2_pwr_2>; |
| |
| imx7d-sdb { |
| pinctrl_hog_2: hoggrp-2 { |
| fsl,pins = < |
| MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 |
| >; |
| }; |
| |
| pinctrl_pwm1: pwm1grp { |
| fsl,pins = < |
| MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 |
| >; |
| }; |
| |
| pinctrl_usbotg2_pwr_2: usbotg2-2 { |
| fsl,pins = < |
| MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 |
| >; |
| }; |
| |
| pinctrl_enet2_epdc0_en: enet2_epdc0_grp { |
| fsl,pins = < |
| MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x80000000 |
| >; |
| }; |
| |
| pinctrl_sai3_mclk: sai3grp_mclk { |
| fsl,pins = < |
| MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f |
| >; |
| }; |
| }; |
| }; |
| |
| &sim1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sim1_1>; |
| port = <0>; |
| sven_low_active; |
| status = "okay"; |
| }; |
| |
| |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; |
| assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; |
| status = "okay"; |
| }; |
| |
| &uart5 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart5>; |
| assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; |
| assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; |
| /* for DTE mode, add below change */ |
| /* fsl,dte-mode; */ |
| /* pinctrl-0 = <&pinctrl_uart5dte>; */ |
| status = "okay"; |
| }; |
| |
| &uart6 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart6>; |
| assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; |
| assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; |
| uart-has-rtscts; |
| resets = <&modem_reset>; |
| status = "okay"; |
| }; |
| |
| &usbotg1 { |
| vbus-supply = <®_usb_otg1_vbus>; |
| srp-disable; |
| hnp-disable; |
| adp-disable; |
| status = "okay"; |
| }; |
| |
| &usbotg2 { |
| vbus-supply = <®_usb_otg2_vbus>; |
| dr_mode = "host"; |
| status = "okay"; |
| }; |
| |
| &usdhc1 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; |
| pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; |
| pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; |
| cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; |
| wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; |
| wakeup-source; |
| vmmc-supply = <®_sd1_vmmc>; |
| enable-sdio-wakeup; |
| keep-power-in-suspend; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi>; |
| pinctrl-1 = <&pinctrl_usdhc2_100mhz &pinctrl_wifi>; |
| pinctrl-2 = <&pinctrl_usdhc2_200mhz &pinctrl_wifi>; |
| wakeup-source; |
| keep-power-in-suspend; |
| non-removable; |
| mmc-pwrseq = <&usdhc2_pwrseq>; |
| fsl,tuning-step = <2>; |
| pm-ignore-notify; |
| cap-power-off-card; |
| status = "disabled"; |
| |
| brcmf: bcrmf@1 { |
| reg = <1>; |
| compatible = "brcm,bcm4329-fmac"; |
| }; |
| }; |
| |
| &usdhc3 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc3>; |
| pinctrl-1 = <&pinctrl_usdhc3_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc3_200mhz>; |
| assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; |
| assigned-clock-rates = <400000000>; |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &wdog1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wdog>; |
| fsl,ext-reset-output; |
| }; |
| |
| &gpmi { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_gpmi_nand_1>; |
| status = "disabled"; |
| nand-on-flash-bbt; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog_1>; |
| |
| imx7d-sdb { |
| pinctrl_brcm_reg: brcmreggrp { |
| fsl,pins = < |
| MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14 |
| >; |
| }; |
| |
| pinctrl_epdc_elan_touch: epdc_elan_touch_grp { |
| fsl,pins = < |
| MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x59 |
| MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x1b |
| MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x80000000 |
| >; |
| }; |
| |
| pinctrl_hog_1: hoggrp-1 { |
| fsl,pins = < |
| MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */ |
| >; |
| }; |
| |
| pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp { |
| fsl,pins = < |
| MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x1b |
| >; |
| }; |
| |
| pinctrl_ecspi3: ecspi3grp { |
| fsl,pins = < |
| MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 |
| MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 |
| MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 |
| >; |
| }; |
| |
| pinctrl_ecspi3_cs: ecspi3_cs_grp { |
| fsl,pins = < |
| MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x80000000 |
| >; |
| }; |
| |
| pinctrl_enet1: enet1grp { |
| fsl,pins = < |
| MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 |
| MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 |
| MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 |
| MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 |
| MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 |
| MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 |
| MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 |
| MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 |
| MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 |
| MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 |
| MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 |
| MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 |
| MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 |
| MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 |
| >; |
| }; |
| |
| pinctrl_enet2: enet2grp { |
| fsl,pins = < |
| MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 |
| MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 |
| MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 |
| MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 |
| MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 |
| MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 |
| MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 |
| MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 |
| MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 |
| MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 |
| MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 |
| MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 |
| >; |
| }; |
| |
| pinctrl_flexcan2: flexcan2grp { |
| fsl,pins = < |
| MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 |
| MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 |
| >; |
| }; |
| |
| pinctrl_flexcan2_reg: flexcan2reggrp { |
| fsl,pins = < |
| MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */ |
| >; |
| }; |
| |
| pinctrl_epdc0: epdcgrp0 { |
| fsl,pins = < |
| MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2 |
| MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2 |
| MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2 |
| MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2 |
| MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2 |
| MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2 |
| MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2 |
| MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2 |
| MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2 |
| MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2 |
| MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2 |
| MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2 |
| MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2 |
| MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2 |
| MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2 |
| MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2 |
| MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2 |
| MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2 |
| MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2 |
| MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2 |
| MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2 |
| MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2 |
| MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2 |
| MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2 |
| MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2 |
| MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2 |
| >; |
| }; |
| |
| pinctrl_gpmi_nand_1: gpmi-nand-1 { |
| fsl,pins = < |
| MX7D_PAD_SD3_CLK__NAND_CLE 0x71 |
| MX7D_PAD_SD3_CMD__NAND_ALE 0x71 |
| MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x71 |
| MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 |
| MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 |
| MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 |
| MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 |
| MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 |
| MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 |
| MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 |
| MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 |
| MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 |
| MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 |
| MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 |
| MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 |
| MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 |
| |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f |
| MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f |
| >; |
| }; |
| |
| pinctrl_i2c1_gpio: i2c1grp_gpio { |
| fsl,pins = < |
| MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x7f |
| MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x7f |
| >; |
| }; |
| |
| pinctrl_i2c2: i2c2grp { |
| fsl,pins = < |
| MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f |
| MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f |
| >; |
| }; |
| |
| pinctrl_i2c2_gpio: i2c2grp_gpio { |
| fsl,pins = < |
| MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x7f |
| MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x7f |
| >; |
| }; |
| |
| pinctrl_i2c3: i2c3grp { |
| fsl,pins = < |
| MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f |
| MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f |
| >; |
| }; |
| |
| pinctrl_i2c3_gpio: i2c3grp_gpio { |
| fsl,pins = < |
| MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x7f |
| MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x7f |
| >; |
| }; |
| |
| pinctrl_i2c4: i2c4grp { |
| fsl,pins = < |
| MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f |
| MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f |
| >; |
| }; |
| |
| pinctrl_i2c4_gpio: i2c4grp_gpio { |
| fsl,pins = < |
| MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x7f |
| MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x7f |
| >; |
| }; |
| |
| pinctrl_lcdif: lcdifgrp { |
| fsl,pins = < |
| MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 |
| MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 |
| MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 |
| MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 |
| MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 |
| MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 |
| MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 |
| MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 |
| MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 |
| MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 |
| MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 |
| MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 |
| MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 |
| MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 |
| MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 |
| MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 |
| MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 |
| MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 |
| MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 |
| MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 |
| MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 |
| MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 |
| MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 |
| MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 |
| MX7D_PAD_LCD_CLK__LCD_CLK 0x79 |
| MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 |
| MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 |
| MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 |
| MX7D_PAD_LCD_RESET__LCD_RESET 0x79 |
| >; |
| }; |
| |
| pinctrl_max17135: max17135grp-1 { |
| fsl,pins = < |
| MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000 /* pwrgood */ |
| MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 /* vcom_ctrl */ |
| MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x80000000 /* wakeup */ |
| MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x80000000 /* v3p3 */ |
| MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x80000000 /* pwr int */ |
| >; |
| }; |
| |
| pinctrl_sai1: sai1grp { |
| fsl,pins = < |
| MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f |
| MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f |
| MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f |
| MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 |
| MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f |
| >; |
| }; |
| |
| pinctrl_sai2: sai2grp { |
| fsl,pins = < |
| MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f |
| MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f |
| MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 |
| MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f |
| >; |
| }; |
| |
| pinctrl_sai3: sai3grp { |
| fsl,pins = < |
| MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f |
| MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f |
| MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 |
| >; |
| }; |
| |
| pinctrl_spi4: spi4grp { |
| fsl,pins = < |
| MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 |
| MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 |
| MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 |
| >; |
| }; |
| |
| pinctrl_tsc2046_pendown: tsc2046_pendown { |
| fsl,pins = < |
| MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 |
| >; |
| }; |
| |
| |
| pinctrl_sii902x: hdmigrp-1 { |
| fsl,pins = < |
| MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59 |
| >; |
| }; |
| |
| pinctrl_sim1_1: sim1grp-1 { |
| fsl,pins = < |
| MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B 0x77 |
| MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD 0x77 |
| MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN 0x77 |
| MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK 0x73 |
| MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD 0x73 |
| >; |
| }; |
| |
| pinctrl_uart1: uart1grp { |
| fsl,pins = < |
| MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 |
| MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 |
| >; |
| }; |
| |
| pinctrl_uart5: uart5grp { |
| fsl,pins = < |
| MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 |
| MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 |
| >; |
| }; |
| |
| pinctrl_uart5dte: uart5dtegrp { |
| fsl,pins = < |
| MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x79 |
| MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x79 |
| >; |
| }; |
| |
| pinctrl_uart6: uart6grp { |
| fsl,pins = < |
| MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 |
| MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 |
| MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 |
| MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 |
| MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x19 /* BT_REG_ON */ |
| >; |
| }; |
| |
| pinctrl_usdhc1_gpio: usdhc1_gpiogrp { |
| fsl,pins = < |
| MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ |
| MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ |
| MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ |
| MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ |
| >; |
| }; |
| |
| pinctrl_usbotg2_pwr_1: usbotg2-1 { |
| fsl,pins = < |
| MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| MX7D_PAD_SD1_CMD__SD1_CMD 0x59 |
| MX7D_PAD_SD1_CLK__SD1_CLK 0x19 |
| MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 |
| MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 |
| MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 |
| MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 |
| >; |
| }; |
| |
| pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { |
| fsl,pins = < |
| MX7D_PAD_SD1_CMD__SD1_CMD 0x5a |
| MX7D_PAD_SD1_CLK__SD1_CLK 0x1a |
| MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a |
| MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a |
| MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a |
| MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a |
| >; |
| }; |
| |
| pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { |
| fsl,pins = < |
| MX7D_PAD_SD1_CMD__SD1_CMD 0x5b |
| MX7D_PAD_SD1_CLK__SD1_CLK 0x1b |
| MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b |
| MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b |
| MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b |
| MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX7D_PAD_SD2_CMD__SD2_CMD 0x59 |
| MX7D_PAD_SD2_CLK__SD2_CLK 0x19 |
| MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 |
| MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 |
| MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 |
| MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 |
| >; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { |
| fsl,pins = < |
| MX7D_PAD_SD2_CMD__SD2_CMD 0x5a |
| MX7D_PAD_SD2_CLK__SD2_CLK 0x1a |
| MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a |
| MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a |
| MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a |
| MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a |
| >; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { |
| fsl,pins = < |
| MX7D_PAD_SD2_CMD__SD2_CMD 0x5b |
| MX7D_PAD_SD2_CLK__SD2_CLK 0x1b |
| MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b |
| MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b |
| MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b |
| MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b |
| >; |
| }; |
| |
| pinctrl_usdhc3: usdhc3grp { |
| fsl,pins = < |
| MX7D_PAD_SD3_CMD__SD3_CMD 0x59 |
| MX7D_PAD_SD3_CLK__SD3_CLK 0x19 |
| MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 |
| MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 |
| MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 |
| MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 |
| MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 |
| MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 |
| MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 |
| MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 |
| MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 |
| >; |
| }; |
| |
| pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { |
| fsl,pins = < |
| MX7D_PAD_SD3_CMD__SD3_CMD 0x5a |
| MX7D_PAD_SD3_CLK__SD3_CLK 0x1a |
| MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a |
| MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a |
| MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a |
| MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a |
| MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a |
| MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a |
| MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a |
| MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a |
| MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a |
| >; |
| }; |
| |
| pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { |
| fsl,pins = < |
| MX7D_PAD_SD3_CMD__SD3_CMD 0x5b |
| MX7D_PAD_SD3_CLK__SD3_CLK 0x1b |
| MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b |
| MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b |
| MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b |
| MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b |
| MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b |
| MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b |
| MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b |
| MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b |
| MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b |
| >; |
| }; |
| |
| pinctrl_wifi: wifigrp { |
| fsl,pins = < |
| MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */ |
| >; |
| }; |
| }; |
| }; |
| |
| &iomuxc_lpsr { |
| pinctrl_wdog: wdoggrp { |
| fsl,pins = < |
| MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 |
| >; |
| }; |
| |
| pinctrl_backlight: backlightgrp { |
| fsl,pins = < |
| MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x110b0 |
| >; |
| }; |
| }; |
