// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2017-2019 NXP
 */

/dts-v1/;

#include "fsl-imx8qxp.dtsi"

/ {
	model = "Freescale i.MX8QXP LPDDR4 ARM2";
	compatible = "fsl,imx8qxp-lpddr4-arm2", "fsl,imx8qxp";

	aliases {
		gpio8 = &pca9557_a;
		gpio9 = &pca9557_b;
		gpio10 = &pca9557_c;
	};

	chosen {
		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
		stdout-path = &lpuart0;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_usb_otg1_vbus: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "usb_otg1_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_usdhc2_vmmc: usdhc2_vmmc {
			compatible = "regulator-fixed";
			regulator-name = "SD1_SPWR";
			regulator-min-microvolt = <3000000>;
			regulator-max-microvolt = <3000000>;
			gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
			enable-active-high;
			startup-delay-us = <300>;
			u-boot,off-on-delay-us = <5000>;
		};
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog_1>;

	imx8qxp-arm2 {
		pinctrl_hog_1: hoggrp-1 {
			fsl,pins = <
				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000048
				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0
			>;
		};

		pinctrl_fec1: fec1grp {
			fsl,pins = <
				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0
				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0
				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000060
				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x00000060
				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000060
				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000060
				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x00000060
				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x00000060
				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x00000060
				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000060
				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000060
				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000060
				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x00000060
				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x00000060
			>;
		};

		pinctrl_fec2: fec2grp {
			fsl,pins = <
				SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x00000060
				SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC		0x00000060
				SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0	0x00000060
				SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1	0x00000060
				SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2		0x00000060
				SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3		0x00000060
				SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC		0x00000060
				SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x00000060
				SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x00000060
				SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1	0x00000060
				SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2	0x00000060
				SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3		0x00000060
			>;
		};

		pinctrl_lpi2c1: lpi1cgrp {
			fsl,pins = <
				SC_P_USB_SS3_TC1_ADMA_I2C1_SCL	0x06000021
				SC_P_USB_SS3_TC3_ADMA_I2C1_SDA	0x06000021
			>;
		};

		pinctrl_lpi2c3: lpi2cgrp {
			fsl,pins = <
				SC_P_SPI3_CS1_ADMA_I2C3_SCL	0x06000020
				SC_P_MCLK_IN1_ADMA_I2C3_SDA	0x06000020
			>;
		};

		pinctrl_lpuart0: lpuart0grp {
			fsl,pins = <
				SC_P_UART0_RX_ADMA_UART0_RX	0x0600002c
				SC_P_UART0_TX_ADMA_UART0_TX	0x0600002c
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
			>;
		};

		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
			fsl,pins = <
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
			>;
		};

		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
			fsl,pins = <
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
			>;
		};

		pinctrl_usdhc2_gpio: usdhc2gpiogrp {
			fsl,pins = <
				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19	0x00000021
				SC_P_USDHC1_WP_LSIO_GPIO4_IO21		0x00000021
				SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22	0x00000021
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
			>;
		};

		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
			fsl,pins = <
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
			>;
		};

		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
			fsl,pins = <
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
			>;
		};

		pinctrl_flexspi0: flexspi0grp {
			fsl,pins = <
				SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x06000021
				SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x06000021
				SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x06000021
				SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x06000021
				SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS		0x06000021
				SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x06000021
				SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B	0x06000021
				SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x06000021
				SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK	0x06000021
				SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x06000021
				SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x06000021
				SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x06000021
				SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x06000021
				SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS		0x06000021
				SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B	0x06000021
				SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B	0x06000021
			>;
		};

		pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp {
			fsl,pins = <
				SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020
				SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020
			>;
		};

		pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp {
			fsl,pins = <
				SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020
				SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020
			>;
		};
	};
};

&gpio0 {
	status = "okay";
};

&gpio3 {
	status = "okay";
};

&gpio4 {
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-txid";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	fsl,rgmii_rxc_dly;
	status = "okay";
	phy-reset-gpios = <&pca9557_a 1 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <10>;
	phy-reset-post-delay = <150>;

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			at803x,eee-disabled;
			at803x,vddio-1p8v;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			at803x,eee-disabled;
			at803x,vddio-1p8v;
			status = "disabled";
		};
	};
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec2>;
	phy-mode = "rgmii-txid";
	phy-handle = <&ethphy1>;
	fsl,magic-packet;
	fsl,rgmii_rxc_dly;
	status = "disabled";
	phy-reset-gpios = <&pca9557_a 4 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <10>;
	phy-reset-post-delay = <150>;
};

&flexspi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
	status = "okay";

	flash0: mt35xu512aba@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "spi-flash";
		spi-max-frequency = <29000000>;
		spi-nor,ddr-quad-read-dummy = <8>;
	};
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c1>;
	status = "okay";
};

&i2c3 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c3>;
	status = "okay";

	pca9557_a: gpio@18 {
		compatible = "nxp,pca9557";
		reg = <0x18>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pca9557_b: gpio@19 {
		compatible = "nxp,pca9557";
		reg = <0x19>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pca9557_c: gpio@1b {
		compatible = "nxp,pca9557";
		reg = <0x1b>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&i2c0_mipi_lvds0 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>;
	clock-frequency = <100000>;
	status = "okay";

	it6263-0@4c {
		compatible = "ITE,it6263";
		reg = <0x4c>;
	};
};

&i2c0_mipi_lvds1 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>;
	clock-frequency = <100000>;
	status = "okay";

	it6263-1@4c {
		compatible = "ITE,it6263";
		reg = <0x4c>;
	};
};

&lpuart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	bus-width = <4>;
	cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&usbotg1 {
	vbus-supply = <&reg_usb_otg1_vbus>;
	srp-disable;
	hnp-disable;
	adp-disable;
	disable-over-current;
	status = "okay";
};

&usbotg3 {
	status = "okay";
};