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coral / uboot-imx / 3d2285690dce3bbdbf945a7b94a426342651ed36 / . / arch / arm / dts / fsl-imx8qm-device.dtsi
blob: 86a21ecdcef3dbea0b7c9bdb89aa66bab3303ae5 [file] [log] [blame]
/*
* Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
imx8qm-pm {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
pd_dc0: PD_DC_0 {
compatible = "nxp,imx8-pd";
reg = <SC_R_DC_0>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dc0_pll0: PD_DC_0_PLL_0{
reg = <SC_R_DC_0_PLL_0>;
#power-domain-cells = <0>;
power-domains =<&pd_dc0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dc0_pll1: PD_DC_0_PLL_1{
reg = <SC_R_DC_0_PLL_1>;
#power-domain-cells = <0>;
power-domains =<&pd_dc0_pll0>;
};
};
pd_mipi0: PD_MIPI_0_DSI {
reg = <SC_R_MIPI_0>;
#power-domain-cells = <0>;
power-domains =<&pd_dc0>;
#address-cells = <1>;
#size-cells = <0>;
pd_mipi0_i2c0: PD_MIPI_0_DSI_I2C0 {
reg = <SC_R_MIPI_0_I2C_0>;
#power-domain-cells = <0>;
power-domains =<&pd_mipi0>;
};
pd_mipi0_i2c1: PD_MIPI_0_DSI_I2C1 {
reg = <SC_R_MIPI_0_I2C_1>;
#power-domain-cells = <0>;
power-domains =<&pd_mipi0>;
};
pd_mipi0_pwm: PD_MIPI_0_DSI_PWM0 {
reg = <SC_R_MIPI_0_PWM_0>;
#power-domain-cells = <0>;
power-domains =<&pd_mipi0>;
};
};
pd_lvds0: PD_LVDS0 {
reg = <SC_R_LVDS_0>;
#power-domain-cells = <0>;
power-domains =<&pd_dc0>;
#address-cells = <1>;
#size-cells = <0>;
pd_lvds0_i2c0: PD_LVDS0_I2C0 {
reg = <SC_R_LVDS_0_I2C_0>;
#power-domain-cells = <0>;
power-domains =<&pd_lvds0>;
};
pd_lvds0_pwm: PD_LVDS0_PWM {
reg = <SC_R_LVDS_0_PWM_0>;
#power-domain-cells = <0>;
power-domains =<&pd_lvds0>;
};
};
pd_hdmi: PD_HDMI {
reg = <SC_R_HDMI>;
#power-domain-cells = <0>;
power-domains =<&pd_dc0>;
#address-cells = <1>;
#size-cells = <0>;
pd_hdmi_pll0: PD_HDMI_PLL_0{
reg = <SC_R_HDMI_PLL_0>;
#power-domain-cells = <0>;
power-domains =<&pd_hdmi>;
#address-cells = <1>;
#size-cells = <0>;
pd_hdmi_pll1: PD_HDMI_PLL_1{
reg = <SC_R_HDMI_PLL_1>;
#power-domain-cells = <0>;
power-domains =<&pd_hdmi_pll0>;
#address-cells = <1>;
#size-cells = <0>;
pd_hdmi_i2c0: PD_HDMI_I2C_0 {
reg = <SC_R_HDMI_I2C_0>;
#power-domain-cells = <0>;
power-domains =<&pd_hdmi_pll1>;
};
pd_hdmi_i2s: PD_HDMI_I2S {
reg = <SC_R_HDMI_I2S>;
#power-domain-cells = <0>;
power-domains =<&pd_hdmi_pll1>;
};
};
};
};
};
pd_dc1: PD_DC_1 {
compatible = "nxp,imx8-pd";
reg = <SC_R_DC_1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dc1_pll0: PD_DC_1_PLL_0{
reg = <SC_R_DC_1_PLL_0>;
#power-domain-cells = <0>;
power-domains =<&pd_dc1>;
#address-cells = <1>;
#size-cells = <0>;
pd_dc1_pll1: PD_DC_1_PLL_1{
reg = <SC_R_DC_1_PLL_1>;
#power-domain-cells = <0>;
power-domains =<&pd_dc1_pll0>;
};
};
pd_mipi1: PD_MIPI_1_DSI {
reg = <SC_R_MIPI_1>;
#power-domain-cells = <0>;
power-domains =<&pd_dc1>;
#address-cells = <1>;
#size-cells = <0>;
pd_mipi1_i2c0: PD_MIPI_1_DSI_I2C0 {
reg = <SC_R_MIPI_1_I2C_0>;
#power-domain-cells = <0>;
power-domains =<&pd_mipi1>;
};
pd_mipi1_i2c1: PD_MIPI_1_DSI_I2C1 {
reg = <SC_R_MIPI_1_I2C_1>;
#power-domain-cells = <0>;
power-domains =<&pd_mipi1>;
};
pd_mipi1_pwm: PD_MIPI_1_DSI_PWM {
reg = <SC_R_MIPI_1_PWM_0>;
#power-domain-cells = <0>;
power-domains =<&pd_mipi1>;
};
};
pd_lvds1: PD_LVDS1 {
reg = <SC_R_LVDS_1>;
#power-domain-cells = <0>;
power-domains =<&pd_dc1>;
#address-cells = <1>;
#size-cells = <0>;
pd_lvds1_i2c0: PD_LVDS1_I2C0 {
reg = <SC_R_LVDS_1_I2C_0>;
#power-domain-cells = <0>;
power-domains =<&pd_lvds1>;
};
pd_lvds1_pwm: PD_LVDS1_PWM {
reg = <SC_R_LVDS_1_PWM_0>;
#power-domain-cells = <0>;
power-domains =<&pd_lvds1>;
};
};
};
pd_lsio: PD_LSIO {
compatible = "nxp,imx8-pd";
reg = <SC_R_NONE>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_lsio_pwm0: PD_LSIO_PWM_0 {
reg = <SC_R_PWM_0>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_pwm1: PD_LSIO_PWM_1 {
reg = <SC_R_PWM_1>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_pwm2: PD_LSIO_PWM_2 {
reg = <SC_R_PWM_2>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_pwm3: PD_LSIO_PWM_3 {
reg = <SC_R_PWM_3>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_pwm4: PD_LSIO_PWM_4 {
reg = <SC_R_PWM_4>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_pwm5: PD_LSIO_PWM_5 {
reg = <SC_R_PWM_5>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_pwm6: PD_LSIO_PWM_6 {
reg = <SC_R_PWM_6>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_pwm7: PD_LSIO_PWM_7 {
reg = <SC_R_PWM_7>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_kpp: PD_LSIO_KPP {
reg = <SC_R_KPP>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpio0: PD_LSIO_GPIO_0 {
reg = <SC_R_GPIO_0>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpio1: PD_LSIO_GPIO_1 {
reg = <SC_R_GPIO_1>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpio2: PD_LSIO_GPIO_2 {
reg = <SC_R_GPIO_2>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpio3: PD_LSIO_GPIO_3 {
reg = <SC_R_GPIO_3>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpio4: PD_LSIO_GPIO_4 {
reg = <SC_R_GPIO_4>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpio5: PD_LSIO_GPIO_5{
reg = <SC_R_GPIO_5>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpio6:PD_LSIO_GPIO_6 {
reg = <SC_R_GPIO_6>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpio7: PD_LSIO_GPIO_7 {
reg = <SC_R_GPIO_7>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpt0: PD_LSIO_GPT_0 {
reg = <SC_R_GPT_0>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpt1: PD_LSIO_GPT_1 {
reg = <SC_R_GPT_1>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpt2: PD_LSIO_GPT_2 {
reg = <SC_R_GPT_2>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpt3: PD_LSIO_GPT_3 {
reg = <SC_R_GPT_3>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpt4: PD_LSIO_GPT_4 {
reg = <SC_R_GPT_4>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_flexspi0: PD_LSIO_FSPI_0 {
reg = <SC_R_FSPI_0>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_flexspi1: PD_LSIO_FSPI_1{
reg = <SC_R_FSPI_1>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_mu5a: PD_LSIO_MU5A {
reg = <SC_R_MU_5A>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_mu6a: PD_LSIO_MU6A {
reg = <SC_R_MU_6A>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_mu8a: PD_LSIO_MU8A {
reg = <SC_R_MU_8A>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_mu9a: PD_LSIO_MU9A {
reg = <SC_R_MU_9A>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
};
pd_conn: PD_CONN {
compatible = "nxp,imx8-pd";
reg = <SC_R_NONE>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_conn_usbotg0: PD_CONN_USB_0 {
reg = <SC_R_USB_0>;
#power-domain-cells = <0>;
power-domains = <&pd_conn>;
wakeup-irq = <267>;
};
pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY {
reg = <SC_R_USB_0_PHY>;
#power-domain-cells = <0>;
power-domains = <&pd_conn>;
wakeup-irq = <267>;
};
pd_conn_usbh1: PD_CONN_USB_1 {
reg = <SC_R_USB_1>;
#power-domain-cells = <0>;
power-domains = <&pd_conn>;
wakeup-irq = <268>;
};
pd_conn_usb2: PD_CONN_USB_2 {
reg = <SC_R_USB_2>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pd_conn>;
wakeup-irq = <271>;
pd_conn_usb2_phy: PD_CONN_USB_2_PHY {
reg = <SC_R_USB_2_PHY>;
#power-domain-cells = <0>;
power-domains = <&pd_conn_usb2>;
wakeup-irq = <271>;
};
};
pd_conn_sdch0: PD_CONN_SDHC_0 {
reg = <SC_R_SDHC_0>;
#power-domain-cells = <0>;
power-domains = <&pd_conn>;
};
pd_conn_sdch1: PD_CONN_SDHC_1 {
reg = <SC_R_SDHC_1>;
#power-domain-cells = <0>;
power-domains = <&pd_conn>;
};
pd_conn_sdch2: PD_CONN_SDHC_2 {
reg = <SC_R_SDHC_2>;
#power-domain-cells = <0>;
power-domains = <&pd_conn>;
};
pd_conn_enet0: PD_CONN_ENET_0 {
reg = <SC_R_ENET_0>;
#power-domain-cells = <0>;
power-domains = <&pd_conn>;
wakeup-irq = <258>;
};
pd_conn_enet1: PD_CONN_ENET_1 {
reg = <SC_R_ENET_1>;
#power-domain-cells = <0>;
power-domains = <&pd_conn>;
fsl,wakeup_irq = <262>;
};
pd_conn_nand: PD_CONN_NAND {
reg = <SC_R_NAND>;
#power-domain-cells = <0>;
power-domains = <&pd_conn>;
};
pd_conn_mlb0: PD_CONN_MLB_0 {
reg = <SC_R_MLB_0>;
#power-domain-cells = <0>;
power-domains = <&pd_conn>;
};
pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 {
reg = <SC_R_DMA_4_CH0>;
#power-domain-cells = <0>;
power-domains =<&pd_conn>;
};
pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 {
reg = <SC_R_DMA_4_CH1>;
#power-domain-cells = <0>;
power-domains =<&pd_conn>;
};
pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 {
reg = <SC_R_DMA_4_CH2>;
#power-domain-cells = <0>;
power-domains =<&pd_conn>;
};
pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 {
reg = <SC_R_DMA_4_CH3>;
#power-domain-cells = <0>;
power-domains =<&pd_conn>;
};
pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 {
reg = <SC_R_DMA_4_CH4>;
#power-domain-cells = <0>;
power-domains =<&pd_conn>;
};
};
pd_hsio: PD_HSIO {
compatible = "nxp,imx8-pd";
reg = <SC_R_NONE>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_hsio_gpio: PD_HSIO_GPIO {
reg = <SC_R_HSIO_GPIO>;
#power-domain-cells = <0>;
power-domains =<&pd_hsio>;
#address-cells = <1>;
#size-cells = <0>;
pd_serdes0: PD_HSIO_SERDES_0 {
reg = <SC_R_SERDES_0>;
#power-domain-cells = <0>;
power-domains =<&pd_hsio_gpio>;
#address-cells = <1>;
#size-cells = <0>;
pd_pcie0: PD_HSIO_PCIE_A {
reg = <SC_R_PCIE_A>;
#power-domain-cells = <0>;
power-domains =<&pd_serdes0>;
#address-cells = <1>;
#size-cells = <0>;
pd_pcie1: PD_HSIO_PCIE_B {
reg = <SC_R_PCIE_B>;
#power-domain-cells = <0>;
power-domains =<&pd_pcie0>;
#address-cells = <1>;
#size-cells = <0>;
pd_serdes1: PD_HSIO_SERDES_1 {
reg = <SC_R_SERDES_1>;
#power-domain-cells = <0>;
power-domains =<&pd_pcie1>;
#address-cells = <1>;
#size-cells = <0>;
pd_sata0: PD_HSIO_SATA_0 {
reg = <SC_R_SATA_0>;
#power-domain-cells = <0>;
power-domains =<&pd_serdes1>;
};
};
};
};
};
};
};
pd_audio: PD_AUDIO {
compatible = "nxp,imx8-pd";
reg = <SC_R_NONE>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_audio_pll0: PD_AUD_AUDIO_PLL_0 {
reg = <SC_R_AUDIO_PLL_0>;
power-domains =<&pd_audio>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_audio_pll1: PD_AUD_AUDIO_PLL_1 {
reg = <SC_R_AUDIO_PLL_1>;
power-domains =<&pd_audio_pll0>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_audio_clk0: PD_AUD_AUDIO_CLK_0 {
reg = <SC_R_AUDIO_CLK_0>;
power-domains =<&pd_audio_pll1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_audio_clk1: PD_AUD_AUDIO_CLK_1 {
reg = <SC_R_AUDIO_CLK_1>;
power-domains =<&pd_audio_clk0>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan0: PD_ASRC_0_RXA {
reg = <SC_R_DMA_2_CH0>;
power-domains =<&pd_audio_clk1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan1: PD_ASRC_0_RXB {
reg = <SC_R_DMA_2_CH1>;
power-domains =<&pd_dma2_chan0>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan2: PD_ASRC_0_RXC {
reg = <SC_R_DMA_2_CH2>;
power-domains =<&pd_dma2_chan1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan3: PD_ASRC_0_TXA {
reg = <SC_R_DMA_2_CH3>;
power-domains =<&pd_dma2_chan2>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan4: PD_ASRC_0_TXB {
reg = <SC_R_DMA_2_CH4>;
power-domains =<&pd_dma2_chan3>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan5: PD_ASRC_0_TXC {
reg = <SC_R_DMA_2_CH5>;
power-domains =<&pd_dma2_chan4>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_asrc0:PD_AUD_ASRC_0 {
reg = <SC_R_ASRC_0>;
#power-domain-cells = <0>;
power-domains =<&pd_dma2_chan5>;
};
};
};
};
};
};
};
pd_dma3_chan0: PD_ASRC_1_RXA {
reg = <SC_R_DMA_3_CH0>;
power-domains =<&pd_audio_clk1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma3_chan1: PD_ASRC_1_RXB {
reg = <SC_R_DMA_3_CH1>;
power-domains =<&pd_dma3_chan0>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma3_chan2: PD_ASRC_1_RXC {
reg = <SC_R_DMA_3_CH2>;
power-domains =<&pd_dma3_chan1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma3_chan3: PD_ASRC_1_TXA {
reg = <SC_R_DMA_3_CH3>;
power-domains =<&pd_dma3_chan2>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma3_chan4: PD_ASRC_1_TXB {
reg = <SC_R_DMA_3_CH4>;
power-domains =<&pd_dma3_chan3>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma3_chan5: PD_ASRC_1_TXC {
reg = <SC_R_DMA_3_CH5>;
power-domains =<&pd_dma3_chan4>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_asrc1: PD_AUD_ASRC_1 {
reg = <SC_R_ASRC_1>;
#power-domain-cells = <0>;
power-domains =<&pd_dma3_chan5>;
};
};
};
};
};
};
};
pd_dma2_chan6: PD_ESAI_0_RX {
reg = <SC_R_DMA_2_CH6>;
power-domains =<&pd_audio_clk1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan7: PD_ESAI_0_TX {
reg = <SC_R_DMA_2_CH7>;
power-domains =<&pd_dma2_chan6>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_esai0: PD_AUD_ESAI_0 {
reg = <SC_R_ESAI_0>;
#power-domain-cells = <0>;
power-domains =<&pd_dma2_chan7>;
};
};
};
pd_dma3_chan6: PD_ESAI_1_RX {
reg = <SC_R_DMA_3_CH6>;
power-domains =<&pd_audio_clk1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma3_chan7: PD_ESAI_1_TX {
reg = <SC_R_DMA_3_CH7>;
power-domains =<&pd_dma3_chan6>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_esai1: PD_AUD_ESAI_1 {
reg = <SC_R_ESAI_1>;
#power-domain-cells = <0>;
power-domains =<&pd_dma3_chan7>;
};
};
};
pd_dma2_chan8: PD_SPDIF_0_RX {
reg = <SC_R_DMA_2_CH8>;
power-domains =<&pd_audio_clk1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan9: PD_SPDIF_0_TX {
reg = <SC_R_DMA_2_CH9>;
power-domains =<&pd_dma2_chan8>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_spdif0: PD_AUD_SPDIF_0 {
reg = <SC_R_SPDIF_0>;
#power-domain-cells = <0>;
power-domains =<&pd_dma2_chan9>;
};
};
};
pd_dma2_chan10: PD_SPDIF_1_RX {
reg = <SC_R_DMA_2_CH10>;
power-domains =<&pd_audio_clk1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan11: PD_SPDIF_1_TX {
reg = <SC_R_DMA_2_CH11>;
power-domains =<&pd_dma2_chan10>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_spdif1: PD_AUD_SPDIF_1 {
reg = <SC_R_SPDIF_1>;
#power-domain-cells = <0>;
power-domains =<&pd_dma2_chan11>;
};
};
};
pd_dma2_chan12: PD_SAI_0_RX {
reg = <SC_R_DMA_2_CH12>;
power-domains =<&pd_audio_clk1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan13: PD_SAI_0_TX {
reg = <SC_R_DMA_2_CH13>;
power-domains =<&pd_dma2_chan12>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_sai0:PD_AUD_SAI_0 {
reg = <SC_R_SAI_0>;
#power-domain-cells = <0>;
power-domains =<&pd_dma2_chan13>;
};
};
};
pd_dma2_chan14: PD_SAI_1_RX {
reg = <SC_R_DMA_2_CH14>;
power-domains =<&pd_audio_clk1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan15: PD_SAI_1_TX {
reg = <SC_R_DMA_2_CH15>;
power-domains =<&pd_dma2_chan14>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_sai1: PD_AUD_SAI_1 {
reg = <SC_R_SAI_1>;
#power-domain-cells = <0>;
power-domains =<&pd_dma2_chan15>;
};
};
};
pd_dma2_chan16: PD_SAI_2_RX {
reg = <SC_R_DMA_2_CH16>;
power-domains =<&pd_audio_clk1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_sai2: PD_AUD_SAI_2 {
reg = <SC_R_SAI_2>;
#power-domain-cells = <0>;
power-domains =<&pd_dma2_chan16>;
};
};
pd_dma2_chan17: PD_SAI_3_RX {
reg = <SC_R_DMA_2_CH17>;
power-domains =<&pd_audio_clk1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_sai3: PD_AUD_SAI_3 {
reg = <SC_R_SAI_3>;
#power-domain-cells = <0>;
power-domains =<&pd_dma2_chan17>;
};
};
pd_dma2_chan18: PD_SAI_4_RX {
reg = <SC_R_DMA_2_CH18>;
power-domains =<&pd_audio_clk1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_sai4: PD_AUD_SAI_4 {
reg = <SC_R_SAI_4>;
#power-domain-cells = <0>;
power-domains =<&pd_dma2_chan18>;
};
};
pd_dma2_chan19: PD_SAI_5_RX {
reg = <SC_R_DMA_2_CH19>;
power-domains =<&pd_audio_clk1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_sai5: PD_AUD_SAI_5 {
reg = <SC_R_SAI_5>;
#power-domain-cells = <0>;
power-domains =<&pd_dma2_chan19>;
};
};
pd_dma3_chan8: PD_SAI_6_RX {
reg = <SC_R_DMA_3_CH8>;
power-domains =<&pd_audio_clk1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma3_chan9: PD_SAI_6_TX {
reg = <SC_R_DMA_3_CH9>;
power-domains =<&pd_dma3_chan8>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_sai6: PD_AUD_SAI_6 {
reg = <SC_R_SAI_6>;
#power-domain-cells = <0>;
power-domains =<&pd_dma3_chan9>;
};
};
};
pd_dma3_chan10: PD_SAI_7_TX {
reg = <SC_R_DMA_3_CH10>;
power-domains =<&pd_audio_clk1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_sai7: PD_AUD_SAI_7 {
reg = <SC_R_SAI_7>;
#power-domain-cells = <0>;
power-domains =<&pd_dma3_chan10>;
};
};
pd_gpt5: PD_AUD_GPT_5 {
reg = <SC_R_GPT_5>;
#power-domain-cells = <0>;
power-domains =<&pd_audio_clk1>;
};
pd_gpt6: PD_AUD_GPT_6 {
reg = <SC_R_GPT_6>;
#power-domain-cells = <0>;
power-domains =<&pd_audio_clk1>;
};
pd_gpt7: PD_AUD_GPT_7 {
reg = <SC_R_GPT_7>;
#power-domain-cells = <0>;
power-domains =<&pd_audio_clk1>;
};
pd_gpt8: PD_AUD_GPT_8 {
reg = <SC_R_GPT_8>;
#power-domain-cells = <0>;
power-domains =<&pd_audio_clk1>;
};
pd_gpt9: PD_AUD_GPT_9 {
reg = <SC_R_GPT_9>;
#power-domain-cells = <0>;
power-domains =<&pd_audio_clk1>;
};
pd_gpt10: PD_AUD_GPT_10 {
reg = <SC_R_GPT_10>;
#power-domain-cells = <0>;
power-domains =<&pd_audio_clk1>;
};
pd_amix: PD_AUD_AMIX {
reg = <SC_R_AMIX>;
#power-domain-cells = <0>;
power-domains =<&pd_audio_clk1>;
};
pd_mqs0: PD_AUD_MQS_0 {
reg = <SC_R_MQS_0>;
#power-domain-cells = <0>;
power-domains =<&pd_audio_clk1>;
};
pd_mclk_out0: PD_AUD_MCLK_OUT_0 {
reg = <SC_R_MCLK_OUT_0>;
#power-domain-cells = <0>;
power-domains =<&pd_audio_clk1>;
};
pd_mclk_out1: PD_AUD_MCLK_OUT_1 {
reg = <SC_R_MCLK_OUT_1>;
#power-domain-cells = <0>;
power-domains =<&pd_audio_clk1>;
};
};
};
};
};
pd_dsp_irqsteer: PD_DSP_MU_A {
reg = <SC_R_IRQSTR_DSP>;
#power-domain-cells = <0>;
power-domains =<&pd_audio>;
#address-cells = <1>;
#size-cells = <0>;
pd_dsp_mu_A: PD_DSP_MU_A {
reg = <SC_R_MU_13A>;
#power-domain-cells = <0>;
power-domains =<&pd_dsp_irqsteer>;
#address-cells = <1>;
#size-cells = <0>;
pd_dsp_mu_B: PD_DSP_MU_B {
reg = <SC_R_MU_13B>;
#power-domain-cells = <0>;
power-domains =<&pd_dsp_mu_A>;
#address-cells = <1>;
#size-cells = <0>;
pd_dsp_ram: PD_AUD_OCRAM {
reg = <SC_R_DSP_RAM>;
#power-domain-cells = <0>;
power-domains =<&pd_dsp_mu_B>;
#address-cells = <1>;
#size-cells = <0>;
pd_dsp: PD_AUD_DSP {
reg = <SC_R_DSP>;
#power-domain-cells = <0>;
power-domains =<&pd_dsp_ram>;
};
};
};
};
};
};
pd_dma: PD_DMA {
compatible = "nxp,imx8-pd";
reg = <SC_R_NONE>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma_flexcan0: PD_DMA_CAN_0 {
reg = <SC_R_CAN_0>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
wakeup-irq = <235>;
};
pd_dma_flexcan1: PD_DMA_CAN_1 {
reg = <SC_R_CAN_1>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
wakeup-irq = <236>;
};
pd_dma_flexcan2: PD_DMA_CAN_2 {
reg = <SC_R_CAN_2>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
wakeup-irq = <237>;
};
pd_dma_ftm0: PD_DMA_FTM_0 {
reg = <SC_R_FTM_0>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
pd_dma_ftm1: PD_DMA_FTM_1 {
reg = <SC_R_FTM_1>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
pd_dma_adc0: PD_DMA_ADC_0 {
reg = <SC_R_ADC_0>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
pd_dma_adc1: PD_DMA_ADC_1 {
reg = <SC_R_ADC_1>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
pd_dma_lpi2c0: PD_DMA_I2C_0 {
reg = <SC_R_I2C_0>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
pd_dma_lpi2c1: PD_DMA_I2C_1 {
reg = <SC_R_I2C_1>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
pd_dma_lpi2c2:PD_DMA_I2C_2 {
reg = <SC_R_I2C_2>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
pd_dma_lpi2c3: PD_DMA_I2C_3 {
reg = <SC_R_I2C_3>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
pd_dma_lpi2c4: PD_DMA_I2C_4 {
reg = <SC_R_I2C_4>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
pd_dma_lpuart0: PD_DMA_UART0 {
reg = <SC_R_UART_0>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
wakeup-irq = <345>;
};
pd_dma_lpuart1: PD_DMA_UART1 {
reg = <SC_R_UART_1>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
#address-cells = <1>;
#size-cells = <0>;
wakeup-irq = <346>;
pd_dma0_chan14: PD_UART1_RX {
reg = <SC_R_DMA_0_CH14>;
power-domains =<&pd_dma_lpuart1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma0_chan15: PD_UART1_TX {
reg = <SC_R_DMA_0_CH15>;
power-domains =<&pd_dma0_chan14>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
pd_dma_lpuart2: PD_DMA_UART2 {
reg = <SC_R_UART_2>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
#address-cells = <1>;
#size-cells = <0>;
wakeup-irq = <347>;
pd_dma0_chan16: PD_UART2_RX {
reg = <SC_R_DMA_0_CH16>;
power-domains =<&pd_dma_lpuart2>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma0_chan17: PD_UART2_TX {
reg = <SC_R_DMA_0_CH17>;
power-domains =<&pd_dma0_chan16>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
pd_dma_lpuart3: PD_DMA_UART3 {
reg = <SC_R_UART_3>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
#address-cells = <1>;
#size-cells = <0>;
wakeup-irq = <348>;
pd_dma0_chan18: PD_UART3_RX {
reg = <SC_R_DMA_0_CH18>;
power-domains =<&pd_dma_lpuart3>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma0_chan19: PD_UART3_TX {
reg = <SC_R_DMA_0_CH19>;
power-domains =<&pd_dma0_chan18>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
pd_dma_lpuart4: PD_DMA_UART4 {
reg = <SC_R_UART_4>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
#address-cells = <1>;
#size-cells = <0>;
wakeup-irq = <349>;
pd_dma0_chan20: PD_UART4_RX {
reg = <SC_R_DMA_0_CH20>;
power-domains =<&pd_dma_lpuart4>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma0_chan21: PD_UART4_TX {
reg = <SC_R_DMA_0_CH21>;
power-domains =<&pd_dma0_chan20>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
pd_dma_lpspi0: PD_DMA_SPI_0 {
reg = <SC_R_SPI_0>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma0_chan0: PD_LPSPI0_RX {
reg = <SC_R_DMA_0_CH0>;
power-domains =<&pd_dma_lpspi0>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma0_chan1: PD_LPSPI0_TX {
reg = <SC_R_DMA_0_CH1>;
power-domains =<&pd_dma0_chan0>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
pd_dma_lpspi1: PD_DMA_SPI_1 {
reg = <SC_R_SPI_1>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
pd_dma_lpspi2: PD_DMA_SPI_2 {
reg = <SC_R_SPI_2>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
pd_dma_lpspi3: PD_DMA_SPI_3 {
reg = <SC_R_SPI_3>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma0_chan6: PD_LPSPI3_RX {
reg = <SC_R_DMA_0_CH6>;
power-domains =<&pd_dma_lpspi3>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma0_chan7: PD_LPSPI3_TX {
reg = <SC_R_DMA_0_CH7>;
power-domains =<&pd_dma0_chan6>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
pd_dma_emvsim0: PD_DMA_EMVSIM_0 {
reg = <SC_R_EMVSIM_0>;
power-domains = <&pd_dma>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_ldo1_sim: LDO1_SIM {
reg = <SC_R_BOARD_R2>;
#power-domain-cells = <0>;
power-domains = <&pd_dma_emvsim0>;
};
};
pd_dma_emvsim1: PD_DMA_EMVSIM_1 {
reg = <SC_R_EMVSIM_1>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
};
pd_gpu: PD_GPU {
compatible = "nxp,imx8-pd";
reg = <SC_R_NONE>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_gpu0: PD_GPU0 {
reg = <SC_R_GPU_0_PID0>;
#power-domain-cells = <0>;
power-domains =<&pd_gpu>;
};
pd_gpu1: PD_GPU1 {
reg = <SC_R_GPU_1_PID0>;
#power-domain-cells = <0>;
power-domains =<&pd_gpu>;
};
};
pd_vpu: vpu-power-domain {
compatible = "nxp,imx8-pd";
reg = <SC_R_VPU>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_vpu_mu1_enc: VPU_ENC_MU1 {
reg = <SC_R_VPU_MU_2>;
#power-domain-cells = <0>;
power-domains =<&pd_vpu>;
#address-cells = <1>;
#size-cells = <0>;
pd_vpu_enc1: VPU_ENC1 {
reg = <SC_R_VPU_ENC_1>;
#power-domain-cells = <0>;
power-domains =<&pd_vpu_mu1_enc>;
#address-cells = <1>;
#size-cells = <0>;
pd_vpu_mu_enc: VPU_ENC_MU {
reg = <SC_R_VPU_MU_1>;
#power-domain-cells = <0>;
power-domains =<&pd_vpu_enc1>;
#address-cells = <1>;
#size-cells = <0>;
pd_vpu_enc: VPU_ENC {
reg = <SC_R_VPU_ENC_0>;
#power-domain-cells = <0>;
power-domains =<&pd_vpu_mu_enc>;
};
};
};
};
pd_vpu_mu_dec: VPU_DEC_MU {
reg = <SC_R_VPU_MU_0>;
#power-domain-cells = <0>;
power-domains =<&pd_vpu>;
#address-cells = <1>;
#size-cells = <0>;
pd_vpu_dec: VPU_DEC {
reg = <SC_R_VPU_DEC_0>;
#power-domain-cells = <0>;
power-domains =<&pd_vpu_mu_dec>;
};
};
};
pd_isi_ch0: PD_IMAGING {
compatible = "nxp,imx8-pd";
reg = <SC_R_ISI_CH0>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_csi0: PD_MIPI_CSI0 {
reg = <SC_R_CSI_0>;
#power-domain-cells = <0>;
power-domains =<&pd_isi_ch0>;
#address-cells = <1>;
#size-cells = <0>;
pd_csi0_i2c0: PD_MIPI_CSI0_I2C0 {
reg = <SC_R_CSI_0_I2C_0>;
#power-domain-cells = <0>;
power-domains =<&pd_csi0>;
};
pd_csi0_pwm: PD_MIPI_CSI0_PWM {
reg = <SC_R_CSI_0_PWM_0>;
#power-domain-cells = <0>;
power-domains =<&pd_csi0>;
};
};
pd_csi1: PD_MIPI_CSI1 {
reg = <SC_R_CSI_1>;
#power-domain-cells = <0>;
power-domains =<&pd_isi_ch0>;
#address-cells = <1>;
#size-cells = <0>;
pd_csi1_i2c0: PD_MIPI_CSI1_I2C0 {
reg = <SC_R_CSI_1_I2C_0>;
#power-domain-cells = <0>;
power-domains =<&pd_csi1>;
};
pd_csi1_pwm: PD_MIPI_CSI1_PWM {
reg = <SC_R_CSI_1_PWM_0>;
#power-domain-cells = <0>;
power-domains =<&pd_csi1>;
};
};
pd_hdmi_rx: PD_HDMI_RX {
reg = <SC_R_HDMI_RX>;
#power-domain-cells = <0>;
power-domains =<&pd_isi_ch0>;
#address-cells = <1>;
#size-cells = <0>;
pd_hdmi_rx_bypass: PD_HDMI_RX_BYPASS {
reg = <SC_R_HDMI_RX_BYPASS>;
#power-domain-cells = <0>;
power-domains =<&pd_hdmi_rx>;
#address-cells = <1>;
#size-cells = <0>;
pd_hdmi_rx_i2c0: PD_HDMI_RX_I2C {
reg = <SC_R_HDMI_RX_I2C_0>;
#power-domain-cells = <0>;
power-domains =<&pd_hdmi_rx_bypass>;
};
pd_hdmi_rx_pwm0: PD_HDMI_RX_PWM {
reg = <SC_R_HDMI_RX_PWM_0>;
#power-domain-cells = <0>;
power-domains =<&pd_hdmi_rx_bypass>;
};
};
};
pd_isi_ch1: PD_IMAGING_PDMA1 {
reg = <SC_R_ISI_CH1>;
#power-domain-cells = <0>;
power-domains =<&pd_isi_ch0>;
};
pd_isi_ch2: PD_IMAGING_PDMA2 {
reg = <SC_R_ISI_CH2>;
#power-domain-cells = <0>;
power-domains =<&pd_isi_ch0>;
};
pd_isi_ch3: PD_IMAGING_PDMA3 {
reg = <SC_R_ISI_CH3>;
#power-domain-cells = <0>;
power-domains =<&pd_isi_ch0>;
};
pd_isi_ch4: PD_IMAGING_PDMA4 {
reg = <SC_R_ISI_CH4>;
#power-domain-cells = <0>;
power-domains =<&pd_isi_ch0>;
};
pd_isi_ch5: PD_IMAGING_PDMA5 {
reg = <SC_R_ISI_CH5>;
#power-domain-cells = <0>;
power-domains =<&pd_isi_ch0>;
};
pd_isi_ch6: PD_IMAGING_PDMA6 {
reg = <SC_R_ISI_CH6>;
#power-domain-cells = <0>;
power-domains =<&pd_isi_ch0>;
};
pd_isi_ch7: PD_IMAGING_PDMA7 {
reg = <SC_R_ISI_CH7>;
#power-domain-cells = <0>;
power-domains =<&pd_isi_ch0>;
};
pd_jpeg_dec_mp: PD_JPEG_DEC_MP {
reg = <SC_R_MJPEG_DEC_MP>;
#power-domain-cells = <0>;
power-domains =<&pd_isi_ch0>;
#address-cells = <1>;
#size-cells = <0>;
pd_jpgdec: PD_IMAGING_JPEG_DEC {
reg = <SC_R_MJPEG_DEC_S0>;
#power-domain-cells = <0>;
power-domains =<&pd_jpeg_dec_mp>;
};
};
pd_jpeg_enc_mp: PD_JPEG_ENC_MP {
reg = <SC_R_MJPEG_ENC_MP>;
#power-domain-cells = <0>;
power-domains =<&pd_isi_ch0>;
#address-cells = <1>;
#size-cells = <0>;
pd_jpgenc: PD_IMAGING_JPEG_ENC {
reg = <SC_R_MJPEG_ENC_S0>;
#power-domain-cells = <0>;
power-domains =<&pd_jpeg_enc_mp>;
};
};
};
pd_cm40: PD_CM40 {
compatible = "nxp,imx8-pd";
reg = <SC_R_NONE>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_cm40_i2c: PD_CM40_I2C {
reg = <SC_R_M4_0_I2C>;
#power-domain-cells = <0>;
power-domains =<&pd_cm40>;
};
pd_cm40_intmux: PD_CM40_INTMUX {
reg = <SC_R_M4_0_INTMUX>;
#power-domain-cells = <0>;
power-domains =<&pd_cm40>;
};
};
pd_cm41: PD_CM41 {
compatible = "nxp,imx8-pd";
reg = <SC_R_NONE>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_cm41_intmux: PD_CM41_INTMUX {
reg = <SC_R_M4_1_INTMUX>;
#power-domain-cells = <0>;
power-domains =<&pd_cm41>;
#address-cells = <1>;
#size-cells = <0>;
early_power_on;
pd_cm41_i2c: PD_CM41_I2C {
reg = <SC_R_M4_1_I2C>;
#power-domain-cells = <0>;
power-domains =<&pd_cm41_intmux>;
};
};
};
pd_caam: PD_CAAM {
compatible = "nxp,imx8-pd";
reg = <SC_R_NONE>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_caam_jr1: PD_CAAM_JR1 {
reg = <SC_R_CAAM_JR1>;
#power-domain-cells = <0>;
power-domains = <&pd_caam>;
};
pd_caam_jr2: PD_CAAM_JR2 {
reg = <SC_R_CAAM_JR2>;
#power-domain-cells = <0>;
power-domains = <&pd_caam>;
};
pd_caam_jr3: PD_CAAM_JR3 {
reg = <SC_R_CAAM_JR3>;
#power-domain-cells = <0>;
power-domains = <&pd_caam>;
};
};
};
tsens: thermal-sensor {
compatible = "nxp,imx8qm-sc-tsens";
u-boot,dm-pre-reloc;
/* number of the temp sensor on the chip */
tsens-num = <5>;
#thermal-sensor-cells = <1>;
};
thermal_zones: thermal-zones {
/* cpu thermal */
cpu-thermal0 {
polling-delay-passive = <250>;
polling-delay = <2000>;
/*the slope and offset of the temp sensor */
thermal-sensors = <&tsens 0>;
trips {
cpu_alert0: trip0 {
temperature = <107000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit0: trip1 {
temperature = <127000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device =
<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu-thermal1 {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tsens 1>;
trips {
cpu_alert1: trip0 {
temperature = <107000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit1: trip1 {
temperature = <127000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert1>;
cooling-device =
<&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpu-thermal0 {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tsens 2>;
trips {
gpu_alert0: trip0 {
temperature = <107000>;
hysteresis = <2000>;
type = "passive";
};
gpu_crit0: trip1 {
temperature = <127000>;
hysteresis = <2000>;
type = "critical";
};
};
};
gpu-thermal1 {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tsens 3>;
trips {
gpu_alert1: trip0 {
temperature = <107000>;
hysteresis = <2000>;
type = "passive";
};
gpu_crit1: trip1 {
temperature = <127000>;
hysteresis = <2000>;
type = "critical";
};
};
};
drc-thermal0 {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tsens 4>;
trips {
drc_alert0: trip0 {
temperature = <107000>;
hysteresis = <2000>;
type = "passive";
};
drc_crit0: trip1 {
temperature = <127000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
rtc: rtc {
compatible = "fsl,imx-sc-rtc";
};
dpu1_intsteer: dpu_intsteer@56000000 {
compatible = "fsl,imx8qm-dpu-intsteer", "syscon";
reg = <0x0 0x56000000 0x0 0x10000>;
};
pixel_combiner1: pixel-combiner@56020000 {
compatible = "fsl,imx8qm-pixel-combiner";
reg = <0x0 0x56020000 0x0 0x10000>;
power-domains = <&pd_dc0>;
status = "disabled";
};
prg1: prg@56040000 {
compatible = "fsl,imx8qm-prg";
reg = <0x0 0x56040000 0x0 0x10000>;
clocks = <&clk IMX8QM_DC0_PRG0_APB_CLK>,
<&clk IMX8QM_DC0_PRG0_RTRAM_CLK>;
clock-names = "apb", "rtram";
power-domains = <&pd_dc0>;
status = "disabled";
};
prg2: prg@56050000 {
compatible = "fsl,imx8qm-prg";
reg = <0x0 0x56050000 0x0 0x10000>;
clocks = <&clk IMX8QM_DC0_PRG1_APB_CLK>,
<&clk IMX8QM_DC0_PRG1_RTRAM_CLK>;
clock-names = "apb", "rtram";
power-domains = <&pd_dc0>;
status = "disabled";
};
prg3: prg@56060000 {
compatible = "fsl,imx8qm-prg";
reg = <0x0 0x56060000 0x0 0x10000>;
clocks = <&clk IMX8QM_DC0_PRG2_APB_CLK>,
<&clk IMX8QM_DC0_PRG2_RTRAM_CLK>;
clock-names = "apb", "rtram";
power-domains = <&pd_dc0>;
status = "disabled";
};
prg4: prg@56070000 {
compatible = "fsl,imx8qm-prg";
reg = <0x0 0x56070000 0x0 0x10000>;
clocks = <&clk IMX8QM_DC0_PRG3_APB_CLK>,
<&clk IMX8QM_DC0_PRG3_RTRAM_CLK>;
clock-names = "apb", "rtram";
power-domains = <&pd_dc0>;
status = "disabled";
};
prg5: prg@56080000 {
compatible = "fsl,imx8qm-prg";
reg = <0x0 0x56080000 0x0 0x10000>;
clocks = <&clk IMX8QM_DC0_PRG4_APB_CLK>,
<&clk IMX8QM_DC0_PRG4_RTRAM_CLK>;
clock-names = "apb", "rtram";
power-domains = <&pd_dc0>;
status = "disabled";
};
prg6: prg@56090000 {
compatible = "fsl,imx8qm-prg";
reg = <0x0 0x56090000 0x0 0x10000>;
clocks = <&clk IMX8QM_DC0_PRG5_APB_CLK>,
<&clk IMX8QM_DC0_PRG5_RTRAM_CLK>;
clock-names = "apb", "rtram";
power-domains = <&pd_dc0>;
status = "disabled";
};
prg7: prg@560a0000 {
compatible = "fsl,imx8qm-prg";
reg = <0x0 0x560a0000 0x0 0x10000>;
clocks = <&clk IMX8QM_DC0_PRG6_APB_CLK>,
<&clk IMX8QM_DC0_PRG6_RTRAM_CLK>;
clock-names = "apb", "rtram";
power-domains = <&pd_dc0>;
status = "disabled";
};
prg8: prg@560b0000 {
compatible = "fsl,imx8qm-prg";
reg = <0x0 0x560b0000 0x0 0x10000>;
clocks = <&clk IMX8QM_DC0_PRG7_APB_CLK>,
<&clk IMX8QM_DC0_PRG7_RTRAM_CLK>;
clock-names = "apb", "rtram";
power-domains = <&pd_dc0>;
status = "disabled";
};
prg9: prg@560c0000 {
compatible = "fsl,imx8qm-prg";
reg = <0x0 0x560c0000 0x0 0x10000>;
clocks = <&clk IMX8QM_DC0_PRG8_APB_CLK>,
<&clk IMX8QM_DC0_PRG8_RTRAM_CLK>;
clock-names = "apb", "rtram";
power-domains = <&pd_dc0>;
status = "disabled";
};
dpr1_channel1: dpr-channel@560d0000 {
compatible = "fsl,imx8qm-dpr-channel";
reg = <0x0 0x560d0000 0x0 0x10000>;
fsl,sc-resource = <SC_R_DC_0_BLIT0>;
fsl,prgs = <&prg1>;
clocks = <&clk IMX8QM_DC0_DPR0_APB_CLK>,
<&clk IMX8QM_DC0_DPR0_B_CLK>,
<&clk IMX8QM_DC0_RTRAM0_CLK>;
clock-names = "apb", "b", "rtram";
power-domains = <&pd_dc0>;
status = "disabled";
};
dpr1_channel2: dpr-channel@560e0000 {
compatible = "fsl,imx8qm-dpr-channel";
reg = <0x0 0x560e0000 0x0 0x10000>;
fsl,sc-resource = <SC_R_DC_0_BLIT1>;
fsl,prgs = <&prg2>, <&prg1>;
clocks = <&clk IMX8QM_DC0_DPR0_APB_CLK>,
<&clk IMX8QM_DC0_DPR0_B_CLK>,
<&clk IMX8QM_DC0_RTRAM0_CLK>;
clock-names = "apb", "b", "rtram";
power-domains = <&pd_dc0>;
status = "disabled";
};
dpr1_channel3: dpr-channel@560f0000 {
compatible = "fsl,imx8qm-dpr-channel";
reg = <0x0 0x560f0000 0x0 0x10000>;
fsl,sc-resource = <SC_R_DC_0_FRAC0>;
fsl,prgs = <&prg3>;
clocks = <&clk IMX8QM_DC0_DPR0_APB_CLK>,
<&clk IMX8QM_DC0_DPR0_B_CLK>,
<&clk IMX8QM_DC0_RTRAM0_CLK>;
clock-names = "apb", "b", "rtram";
power-domains = <&pd_dc0>;
status = "disabled";
};
dpr2_channel1: dpr-channel@56100000 {
compatible = "fsl,imx8qm-dpr-channel";
reg = <0x0 0x56100000 0x0 0x10000>;
fsl,sc-resource = <SC_R_DC_0_VIDEO0>;
fsl,prgs = <&prg4>, <&prg5>;
clocks = <&clk IMX8QM_DC0_DPR1_APB_CLK>,
<&clk IMX8QM_DC0_DPR1_B_CLK>,
<&clk IMX8QM_DC0_RTRAM1_CLK>;
clock-names = "apb", "b", "rtram";
power-domains = <&pd_dc0>;
status = "disabled";
};
dpr2_channel2: dpr-channel@56110000 {
compatible = "fsl,imx8qm-dpr-channel";
reg = <0x0 0x56110000 0x0 0x10000>;
fsl,sc-resource = <SC_R_DC_0_VIDEO1>;
fsl,prgs = <&prg6>, <&prg7>;
clocks = <&clk IMX8QM_DC0_DPR1_APB_CLK>,
<&clk IMX8QM_DC0_DPR1_B_CLK>,
<&clk IMX8QM_DC0_RTRAM1_CLK>;
clock-names = "apb", "b", "rtram";
power-domains = <&pd_dc0>;
status = "disabled";
};
dpr2_channel3: dpr-channel@56120000 {
compatible = "fsl,imx8qm-dpr-channel";
reg = <0x0 0x56120000 0x0 0x10000>;
fsl,sc-resource = <SC_R_DC_0_WARP>;
fsl,prgs = <&prg8>, <&prg9>;
clocks = <&clk IMX8QM_DC0_DPR1_APB_CLK>,
<&clk IMX8QM_DC0_DPR1_B_CLK>,
<&clk IMX8QM_DC0_RTRAM1_CLK>;
clock-names = "apb", "b", "rtram";
power-domains = <&pd_dc0>;
status = "disabled";
};
dpu1: dpu@56180000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8qm-dpu";
reg = <0x0 0x56180000 0x0 0x40000>;
intsteer = <&dpu1_intsteer>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_common",
"irq_stream0a",
"irq_stream0b", /* to M4? */
"irq_stream1a",
"irq_stream1b", /* to M4? */
"irq_reserved0",
"irq_reserved1",
"irq_blit",
"irq_dpr0",
"irq_dpr1";
clocks = <&clk IMX8QM_DC0_PLL0_CLK>,
<&clk IMX8QM_DC0_PLL1_CLK>,
<&clk IMX8QM_DC0_BYPASS_0_DIV>,
<&clk IMX8QM_DC0_DISP0_SEL>,
<&clk IMX8QM_DC0_DISP1_SEL>,
<&clk IMX8QM_DC0_DISP0_CLK>,
<&clk IMX8QM_DC0_DISP1_CLK>;
clock-names = "pll0", "pll1", "bypass0",
"disp0_sel", "disp1_sel", "disp0", "disp1";
power-domains = <&pd_dc0_pll1>;
fsl,dpr-channels = <&dpr1_channel1>, <&dpr1_channel2>,
<&dpr1_channel3>, <&dpr2_channel1>,
<&dpr2_channel2>, <&dpr2_channel3>;
fsl,pixel-combiner = <&pixel_combiner1>;
status = "disabled";
dpu1_disp0: port@0 {
reg = <0>;
dpu1_disp0_hdmi: hdmi-endpoint {
remote-endpoint = <&hdmi_disp>;
};
dpu1_disp0_mipi_dsi: mipi-dsi-endpoint {
remote-endpoint = <&mipi_dsi1_in>;
};
};
dpu1_disp1: port@1 {
reg = <1>;
dpu1_disp1_lvds0: lvds0-endpoint {
remote-endpoint = <&ldb1_lvds0>;
};
dpu1_disp1_lvds1: lvds1-endpoint {
remote-endpoint = <&ldb1_lvds1>;
};
};
};
hdmi:hdmi@56268000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x56268000 0x0 0x100000>, /* HDP Controller */
<0x0 0x56261000 0x0 0x1000>; /* HDP SubSystem CSR */
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
<13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "plug_in", "plug_out";
interrupt-parent = <&irqsteer_hdmi>;
status = "disabled";
clocks = <&clk IMX8QM_HDMI_DIG_PLL_CLK>,
<&clk IMX8QM_HDMI_AV_PLL_CLK>,
<&clk IMX8QM_HDMI_IPG_CLK>,
<&clk IMX8QM_HDMI_HDP_CORE_CLK>,
<&clk IMX8QM_HDMI_PXL_CLK>,
<&clk IMX8QM_HDMI_PXL_MUX_CLK>,
<&clk IMX8QM_HDMI_PXL_LINK_CLK>,
<&clk IMX8QM_HDMI_HDP_CLK>,
<&clk IMX8QM_HDMI_HDP_PHY_CLK>,
<&clk IMX8QM_HDMI_APB_CLK>,
<&clk IMX8QM_HDMI_LIS_IPG_CLK>,
<&clk IMX8QM_HDMI_MSI_HCLK>,
<&clk IMX8QM_HDMI_PXL_LPCG_CLK>,
<&clk IMX8QM_HDMI_PXL_EVEN_CLK>,
<&clk IMX8QM_HDMI_PXL_DBL_CLK>,
<&clk IMX8QM_HDMI_VIF_CLK>,
<&clk IMX8QM_HDMI_APB_MUX_CSR_CLK>,
<&clk IMX8QM_HDMI_APB_MUX_CTRL_CLK>,
<&clk IMX8QM_HDMI_I2S_CLK>,
<&clk IMX8QM_HDMI_I2S_BYPASS_CLK>;
clock-names = "dig_pll", "av_pll", "clk_ipg",
"clk_core", "clk_pxl", "clk_pxl_mux",
"clk_pxl_link", "clk_hdp", "clk_phy",
"clk_apb", "clk_lis","clk_msi",
"clk_lpcg", "clk_even","clk_dbl",
"clk_vif", "clk_apb_csr","clk_apb_ctrl",
"clk_i2s", "clk_i2s_bypass";
power-domains = <&pd_hdmi_i2s>;
port@0 {
reg = <0>;
hdmi_disp: endpoint {
remote-endpoint = <&dpu1_disp0_hdmi>;
};
};
};
irqsteer_dsi0: irqsteer@56220000 {
compatible = "nxp,imx-irqsteer";
reg = <0x0 0x56220000 0x0 0x1000>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
clocks = <&clk IMX8QM_MIPI0_LIS_IPG_CLK>;
clock-names = "ipg";
power-domains = <&pd_mipi0>;
};
i2c0_mipi_dsi0: i2c@56226000 {
compatible = "fsl,imx8qm-lpi2c";
reg = <0x0 0x56226000 0x0 0x1000>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&irqsteer_dsi0>;
clocks = <&clk IMX8QM_MIPI0_I2C0_CLK>,
<&clk IMX8QM_MIPI0_I2C0_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_MIPI0_I2C0_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_mipi0_i2c0>;
status = "disabled";
};
mipi_dsi_csr1: csr@56221000 {
compatible = "fsl,imx8qm-mipi-dsi-csr", "syscon";
reg = <0x0 0x56221000 0x0 0x1000>;
};
mipi_dsi_phy1: dsi_phy@56228300 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mixel,imx8qm-mipi-dsi-phy";
reg = <0x0 0x56228300 0x0 0x100>;
power-domains = <&pd_mipi0>;
#phy-cells = <0>;
status = "disabled";
};
mipi_dsi1: mipi_dsi@56228000 {
compatible = "fsl,imx8qm-mipi-dsi";
clocks =
<&clk IMX8QM_MIPI0_PXL_CLK>,
<&clk IMX8QM_MIPI0_BYPASS_CLK>,
<&clk IMX8QM_CLK_DUMMY>;
clock-names = "pixel", "bypass", "phy_ref";
power-domains = <&pd_mipi0>;
csr = <&mipi_dsi_csr1>;
phys = <&mipi_dsi_phy1>;
phy-names = "dphy";
pwr-delay = <100>;
status = "disabled";
port@0 {
mipi_dsi1_in: endpoint {
remote-endpoint = <&dpu1_disp0_mipi_dsi>;
};
};
port@1 {
mipi_dsi1_out: endpoint {
remote-endpoint = <&mipi_dsi_bridge1_in>;
};
};
};
mipi_dsi_bridge1: mipi_dsi_bridge@56228000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nwl,mipi-dsi";
reg = <0x0 0x56228000 0x0 0x300>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&irqsteer_dsi0>;
clocks =
<&clk IMX8QM_MIPI0_BYPASS_CLK>,
<&clk IMX8QM_MIPI0_DSI_TX_ESC_CLK>,
<&clk IMX8QM_MIPI0_DSI_RX_ESC_CLK>;
clock-names = "phy_ref", "tx_esc", "rx_esc";
assigned-clocks = <&clk IMX8QM_MIPI0_DSI_TX_ESC_DIV>,
<&clk IMX8QM_MIPI0_DSI_RX_ESC_DIV>;
assigned-clock-rates = <18000000>, <72000000>;
power-domains = <&pd_mipi0>;
phys = <&mipi_dsi_phy1>;
phy-names = "dphy";
status = "disabled";
port@0 {
mipi_dsi_bridge1_in: endpoint {
remote-endpoint = <&mipi_dsi1_out>;
};
};
};
lvds_region1: lvds_region@56240000 {
compatible = "fsl,imx8qm-lvds-region", "syscon";
reg = <0x0 0x56240000 0x0 0x10000>;
};
ldb1_phy: ldb_phy@56241000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mixel,lvds-phy";
reg = <0x0 0x56241000 0x0 0x100>;
clocks = <&clk IMX8QM_LVDS0_PHY_CLK>;
clock-names = "phy";
power-domains = <&pd_lvds0>;
status = "disabled";
ldb1_phy1: port@0 {
reg = <0>;
#phy-cells = <0>;
};
ldb1_phy2: port@1 {
reg = <1>;
#phy-cells = <0>;
};
};
ldb1: ldb@562410e0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8qm-ldb";
clocks = <&clk IMX8QM_LVDS0_PIXEL_CLK>,
<&clk IMX8QM_LVDS0_BYPASS_CLK>;
clock-names = "pixel", "bypass";
power-domains = <&pd_lvds0>;
gpr = <&lvds_region1>;
status = "disabled";
lvds-channel@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
phys = <&ldb1_phy1>;
phy-names = "ldb_phy";
status = "disabled";
port@0 {
reg = <0>;
ldb1_lvds0: endpoint {
remote-endpoint = <&dpu1_disp1_lvds0>;
};
};
};
lvds-channel@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
phys = <&ldb1_phy2>;
phy-names = "ldb_phy";
status = "disabled";
port@0 {
reg = <0>;
ldb1_lvds1: endpoint {
remote-endpoint = <&dpu1_disp1_lvds1>;
};
};
};
};
lvds0_pwm: pwm@56244000 {
compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
reg = <0x0 0x56244000 0 0x1000>;
clocks = <&clk IMX8QM_LVDS0_PWM0_IPG_CLK>,
<&clk IMX8QM_LVDS0_PWM0_CLK>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8QM_LVDS0_PWM0_CLK>;
assigned-clock-rates = <24000000>;
#pwm-cells = <2>;
power-domains = <&pd_lvds0_pwm>;
status = "disabled";
};
dpu2_intsteer: dpu_intsteer@57000000 {
compatible = "fsl,imx8qm-dpu-intsteer", "syscon";
reg = <0x0 0x57000000 0x0 0x10000>;
};
pixel_combiner2: pixel-combiner@57020000 {
compatible = "fsl,imx8qm-pixel-combiner";
reg = <0x0 0x57020000 0x0 0x10000>;
power-domains = <&pd_dc1>;
status = "disabled";
};
prg10: prg@57040000 {
compatible = "fsl,imx8qm-prg";
reg = <0x0 0x57040000 0x0 0x10000>;
clocks = <&clk IMX8QM_DC1_PRG0_APB_CLK>,
<&clk IMX8QM_DC1_PRG0_RTRAM_CLK>;
clock-names = "apb", "rtram";
power-domains = <&pd_dc1>;
status = "disabled";
};
prg11: prg@57050000 {
compatible = "fsl,imx8qm-prg";
reg = <0x0 0x57050000 0x0 0x10000>;
clocks = <&clk IMX8QM_DC1_PRG1_APB_CLK>,
<&clk IMX8QM_DC1_PRG1_RTRAM_CLK>;
clock-names = "apb", "rtram";
power-domains = <&pd_dc1>;
status = "disabled";
};
prg12: prg@57060000 {
compatible = "fsl,imx8qm-prg";
reg = <0x0 0x57060000 0x0 0x10000>;
clocks = <&clk IMX8QM_DC1_PRG2_APB_CLK>,
<&clk IMX8QM_DC1_PRG2_RTRAM_CLK>;
clock-names = "apb", "rtram";
power-domains = <&pd_dc1>;
status = "disabled";
};
prg13: prg@57070000 {
compatible = "fsl,imx8qm-prg";
reg = <0x0 0x57070000 0x0 0x10000>;
clocks = <&clk IMX8QM_DC1_PRG3_APB_CLK>,
<&clk IMX8QM_DC1_PRG3_RTRAM_CLK>;
clock-names = "apb", "rtram";
power-domains = <&pd_dc1>;
status = "disabled";
};
prg14: prg@57080000 {
compatible = "fsl,imx8qm-prg";
reg = <0x0 0x57080000 0x0 0x10000>;
clocks = <&clk IMX8QM_DC1_PRG4_APB_CLK>,
<&clk IMX8QM_DC1_PRG4_RTRAM_CLK>;
clock-names = "apb", "rtram";
power-domains = <&pd_dc1>;
status = "disabled";
};
prg15: prg@57090000 {
compatible = "fsl,imx8qm-prg";
reg = <0x0 0x57090000 0x0 0x10000>;
clocks = <&clk IMX8QM_DC1_PRG5_APB_CLK>,
<&clk IMX8QM_DC1_PRG5_RTRAM_CLK>;
clock-names = "apb", "rtram";
power-domains = <&pd_dc1>;
status = "disabled";
};
prg16: prg@570a0000 {
compatible = "fsl,imx8qm-prg";
reg = <0x0 0x570a0000 0x0 0x10000>;
clocks = <&clk IMX8QM_DC1_PRG6_APB_CLK>,
<&clk IMX8QM_DC1_PRG6_RTRAM_CLK>;
clock-names = "apb", "rtram";
power-domains = <&pd_dc1>;
status = "disabled";
};
prg17: prg@570b0000 {
compatible = "fsl,imx8qm-prg";
reg = <0x0 0x570b0000 0x0 0x10000>;
clocks = <&clk IMX8QM_DC1_PRG7_APB_CLK>,
<&clk IMX8QM_DC1_PRG7_RTRAM_CLK>;
clock-names = "apb", "rtram";
power-domains = <&pd_dc1>;
status = "disabled";
};
prg18: prg@570c0000 {
compatible = "fsl,imx8qm-prg";
reg = <0x0 0x570c0000 0x0 0x10000>;
clocks = <&clk IMX8QM_DC1_PRG8_APB_CLK>,
<&clk IMX8QM_DC1_PRG8_RTRAM_CLK>;
clock-names = "apb", "rtram";
power-domains = <&pd_dc1>;
status = "disabled";
};
dpr3_channel1: dpr-channel@570d0000 {
compatible = "fsl,imx8qm-dpr-channel";
reg = <0x0 0x570d0000 0x0 0x10000>;
fsl,sc-resource = <SC_R_DC_1_BLIT0>;
fsl,prgs = <&prg10>;
clocks = <&clk IMX8QM_DC1_DPR0_APB_CLK>,
<&clk IMX8QM_DC1_DPR0_B_CLK>,
<&clk IMX8QM_DC1_RTRAM0_CLK>;
clock-names = "apb", "b", "rtram";
power-domains = <&pd_dc1>;
status = "disabled";
};
dpr3_channel2: dpr-channel@570e0000 {
compatible = "fsl,imx8qm-dpr-channel";
reg = <0x0 0x570e0000 0x0 0x10000>;
fsl,sc-resource = <SC_R_DC_1_BLIT1>;
fsl,prgs = <&prg11>, <&prg10>;
clocks = <&clk IMX8QM_DC1_DPR0_APB_CLK>,
<&clk IMX8QM_DC1_DPR0_B_CLK>,
<&clk IMX8QM_DC1_RTRAM0_CLK>;
clock-names = "apb", "b", "rtram";
power-domains = <&pd_dc1>;
status = "disabled";
};
dpr3_channel3: dpr-channel@570f0000 {
compatible = "fsl,imx8qm-dpr-channel";
reg = <0x0 0x570f0000 0x0 0x10000>;
fsl,sc-resource = <SC_R_DC_1_FRAC0>;
fsl,prgs = <&prg12>;
clocks = <&clk IMX8QM_DC1_DPR0_APB_CLK>,
<&clk IMX8QM_DC1_DPR0_B_CLK>,
<&clk IMX8QM_DC1_RTRAM0_CLK>;
clock-names = "apb", "b", "rtram";
power-domains = <&pd_dc1>;
status = "disabled";
};
dpr4_channel1: dpr-channel@57100000 {
compatible = "fsl,imx8qm-dpr-channel";
reg = <0x0 0x57100000 0x0 0x10000>;
fsl,sc-resource = <SC_R_DC_1_VIDEO0>;
fsl,prgs = <&prg13>, <&prg14>;
clocks = <&clk IMX8QM_DC1_DPR1_APB_CLK>,
<&clk IMX8QM_DC1_DPR1_B_CLK>,
<&clk IMX8QM_DC1_RTRAM1_CLK>;
clock-names = "apb", "b", "rtram";
power-domains = <&pd_dc1>;
status = "disabled";
};
dpr4_channel2: dpr-channel@57110000 {
compatible = "fsl,imx8qm-dpr-channel";
reg = <0x0 0x57110000 0x0 0x10000>;
fsl,sc-resource = <SC_R_DC_1_VIDEO1>;
fsl,prgs = <&prg15>, <&prg16>;
clocks = <&clk IMX8QM_DC1_DPR1_APB_CLK>,
<&clk IMX8QM_DC1_DPR1_B_CLK>,
<&clk IMX8QM_DC1_RTRAM1_CLK>;
clock-names = "apb", "b", "rtram";
power-domains = <&pd_dc1>;
status = "disabled";
};
dpr4_channel3: dpr-channel@56712000 {
compatible = "fsl,imx8qm-dpr-channel";
reg = <0x0 0x57120000 0x0 0x10000>;
fsl,sc-resource = <SC_R_DC_1_WARP>;
fsl,prgs = <&prg17>, <&prg18>;
clocks = <&clk IMX8QM_DC1_DPR1_APB_CLK>,
<&clk IMX8QM_DC1_DPR1_B_CLK>,
<&clk IMX8QM_DC1_RTRAM1_CLK>;
clock-names = "apb", "b", "rtram";
power-domains = <&pd_dc1>;
status = "disabled";
};
dpu2: dpu@57180000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8qm-dpu";
reg = <0x0 0x57180000 0x0 0x40000>;
intsteer = <&dpu2_intsteer>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_common",
"irq_stream0a",
"irq_stream0b", /* to M4? */
"irq_stream1a",
"irq_stream1b", /* to M4? */
"irq_reserved0",
"irq_reserved1",
"irq_blit",
"irq_dpr0",
"irq_dpr1";
clocks = <&clk IMX8QM_DC1_PLL0_CLK>,
<&clk IMX8QM_DC1_PLL1_CLK>,
<&clk IMX8QM_DC1_BYPASS_0_DIV>,
<&clk IMX8QM_DC1_DISP0_SEL>,
<&clk IMX8QM_DC1_DISP1_SEL>,
<&clk IMX8QM_DC1_DISP0_CLK>,
<&clk IMX8QM_DC1_DISP1_CLK>;
clock-names = "pll0", "pll1", "bypass0",
"disp0_sel", "disp1_sel", "disp0", "disp1";
power-domains = <&pd_dc1_pll1>;
fsl,dpr-channels = <&dpr3_channel1>, <&dpr3_channel2>,
<&dpr3_channel3>, <&dpr4_channel1>,
<&dpr4_channel2>, <&dpr4_channel3>;
fsl,pixel-combiner = <&pixel_combiner2>;
status = "disabled";
dpu2_disp0: port@0 {
reg = <0>;
dpu2_disp0_mipi_dsi: mipi-dsi-endpoint {
remote-endpoint = <&mipi_dsi2_in>;
};
};
dpu2_disp1: port@1 {
reg = <1>;
dpu2_disp1_lvds0: lvds0-endpoint {
remote-endpoint = <&ldb2_lvds0>;
};
dpu2_disp1_lvds1: lvds1-endpoint {
remote-endpoint = <&ldb2_lvds1>;
};
};
};
irqsteer_dsi1: irqsteer@57220000 {
compatible = "nxp,imx-irqsteer";
reg = <0x0 0x57220000 0x0 0x1000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
clocks = <&clk IMX8QM_MIPI1_LIS_IPG_CLK>;
clock-names = "ipg";
power-domains = <&pd_mipi1>;
};
i2c0_mipi_dsi1: i2c@57226000 {
compatible = "fsl,imx8qm-lpi2c";
reg = <0x0 0x57226000 0x0 0x1000>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&irqsteer_dsi1>;
clocks = <&clk IMX8QM_MIPI1_I2C0_CLK>,
<&clk IMX8QM_MIPI1_I2C0_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_MIPI1_I2C0_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_mipi1_i2c0>;
status = "disabled";
};
mipi_dsi_csr2: csr@57221000 {
compatible = "fsl,imx8qm-mipi-dsi-csr", "syscon";
reg = <0x0 0x57221000 0x0 0x1000>;
};
mipi_dsi_phy2: mipi_phy@57228300 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mixel,imx8qm-mipi-dsi-phy";
reg = <0x0 0x57228300 0x0 0x100>;
power-domains = <&pd_mipi1>;
#phy-cells = <0>;
status = "disabled";
};
mipi_dsi2: mipi_dsi@57228000 {
compatible = "fsl,imx8qm-mipi-dsi";
clocks =
<&clk IMX8QM_MIPI1_PXL_CLK>,
<&clk IMX8QM_MIPI1_BYPASS_CLK>,
<&clk IMX8QM_CLK_DUMMY>;
clock-names = "pixel", "bypass", "phy_ref";
power-domains = <&pd_mipi1>;
csr = <&mipi_dsi_csr2>;
phys = <&mipi_dsi_phy2>;
phy-names = "dphy";
pwr-delay = <100>;
status = "disabled";
port@0 {
mipi_dsi2_in: endpoint {
remote-endpoint = <&dpu2_disp0_mipi_dsi>;
};
};
port@1 {
mipi_dsi2_out: endpoint {
remote-endpoint = <&mipi_dsi_bridge2_in>;
};
};
};
mipi_dsi_bridge2: mipi_dsi_bridge@57228000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nwl,mipi-dsi";
reg = <0x0 0x57228000 0x0 0x300>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&irqsteer_dsi1>;
clocks =
<&clk IMX8QM_MIPI1_BYPASS_CLK>,
<&clk IMX8QM_MIPI1_DSI_TX_ESC_CLK>,
<&clk IMX8QM_MIPI1_DSI_RX_ESC_CLK>;
clock-names = "phy_ref", "tx_esc", "rx_esc";
assigned-clocks = <&clk IMX8QM_MIPI1_DSI_TX_ESC_DIV>,
<&clk IMX8QM_MIPI1_DSI_RX_ESC_DIV>;
assigned-clock-rates = <18000000>, <72000000>;
power-domains = <&pd_mipi1>;
phys = <&mipi_dsi_phy2>;
phy-names = "dphy";
status = "disabled";
port@0 {
mipi_dsi_bridge2_in: endpoint {
remote-endpoint = <&mipi_dsi2_out>;
};
};
};
lvds_region2: lvds_region@57240000 {
compatible = "fsl,imx8qm-lvds-region", "syscon";
reg = <0x0 0x57240000 0x0 0x10000>;
};
ldb2_phy: ldb_phy@57241000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mixel,lvds-phy";
reg = <0x0 0x57241000 0x0 0x100>;
clocks = <&clk IMX8QM_LVDS1_PHY_CLK>;
clock-names = "phy";
power-domains = <&pd_lvds1>;
status = "disabled";
ldb2_phy1: port@0 {
reg = <0>;
#phy-cells = <0>;
};
ldb2_phy2: port@1 {
reg = <1>;
#phy-cells = <0>;
};
};
ldb2: ldb@572410e0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8qm-ldb";
clocks = <&clk IMX8QM_LVDS1_PIXEL_CLK>,
<&clk IMX8QM_LVDS1_BYPASS_CLK>;
clock-names = "pixel", "bypass";
power-domains = <&pd_lvds1>;
gpr = <&lvds_region2>;
status = "disabled";
lvds-channel@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
phys = <&ldb2_phy1>;
phy-names = "ldb_phy";
status = "disabled";
port@0 {
reg = <0>;
ldb2_lvds0: endpoint {
remote-endpoint = <&dpu2_disp1_lvds0>;
};
};
};
lvds-channel@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
phys = <&ldb2_phy2>;
phy-names = "ldb_phy";
status = "disabled";
port@0 {
reg = <0>;
ldb2_lvds1: endpoint {
remote-endpoint = <&dpu2_disp1_lvds1>;
};
};
};
};
lvds1_pwm: pwm@57244000 {
compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
reg = <0x0 0x57244000 0 0x1000>;
clocks = <&clk IMX8QM_LVDS1_PWM0_IPG_CLK>,
<&clk IMX8QM_LVDS1_PWM0_CLK>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8QM_LVDS1_PWM0_CLK>;
assigned-clock-rates = <24000000>;
#pwm-cells = <2>;
power-domains = <&pd_lvds1_pwm>;
status = "disabled";
};
camera: camera {
compatible = "fsl,mxc-md", "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
isi_0: isi@58100000 {
compatible = "fsl,imx8-isi";
reg = <0x0 0x58100000 0x0 0x10000>;
interrupts = <0 297 0>;
interface = <2 0 2>; /* <Input MIPI_VCx Output>
Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM
VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only
Output: 0-DC0, 1-DC1, 2-MEM */
clocks = <&clk IMX8QM_IMG_PDMA_0_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX8QM_IMG_PDMA_0_CLK>;
assigned-clock-rates = <600000000>;
power-domains =<&pd_isi_ch0>;
status = "disabled";
};
isi_1: isi@58110000 {
compatible = "fsl,imx8-isi";
reg = <0x0 0x58110000 0x0 0x10000>;
interrupts = <0 298 0>;
interface = <2 1 2>;
clocks = <&clk IMX8QM_IMG_PDMA_1_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX8QM_IMG_PDMA_1_CLK>;
assigned-clock-rates = <600000000>;
power-domains =<&pd_isi_ch1>;
status = "disabled";
};
isi_2: isi@58120000 {
compatible = "fsl,imx8-isi";
reg = <0x0 0x58120000 0x0 0x10000>;
interrupts = <0 299 0>;
interface = <2 2 2>;
clocks = <&clk IMX8QM_IMG_PDMA_2_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX8QM_IMG_PDMA_2_CLK>;
assigned-clock-rates = <600000000>;
power-domains =<&pd_isi_ch2>;
status = "disabled";
};
isi_3: isi@58130000 {
compatible = "fsl,imx8-isi";
reg = <0x0 0x58130000 0x0 0x10000>;
interrupts = <0 300 0>;
interface = <2 3 2>;
clocks = <&clk IMX8QM_IMG_PDMA_3_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX8QM_IMG_PDMA_3_CLK>;
assigned-clock-rates = <600000000>;
power-domains =<&pd_isi_ch3>;
status = "disabled";
};
isi_4: isi@58140000 {
compatible = "fsl,imx8-isi";
reg = <0x0 0x58140000 0x0 0x10000>;
interrupts = <0 301 0>;
interface = <3 0 2>;
clocks = <&clk IMX8QM_IMG_PDMA_4_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX8QM_IMG_PDMA_4_CLK>;
assigned-clock-rates = <600000000>;
power-domains =<&pd_isi_ch4>;
status = "disabled";
};
isi_5: isi@58150000 {
compatible = "fsl,imx8-isi";
reg = <0x0 0x58150000 0x0 0x10000>;
interrupts = <0 302 0>;
interface = <3 1 2>;
clocks = <&clk IMX8QM_IMG_PDMA_5_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX8QM_IMG_PDMA_5_CLK>;
assigned-clock-rates = <600000000>;
power-domains =<&pd_isi_ch5>;
status = "disabled";
};
isi_6: isi@58160000 {
compatible = "fsl,imx8-isi";
reg = <0x0 0x58160000 0x0 0x10000>;
interrupts = <0 303 0>;
interface = <3 2 2>;
clocks = <&clk IMX8QM_IMG_PDMA_6_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX8QM_IMG_PDMA_6_CLK>;
assigned-clock-rates = <600000000>;
power-domains =<&pd_isi_ch6>;
status = "disabled";
};
isi_7: isi@58170000 {
compatible = "fsl,imx8-isi";
reg = <0x0 0x58170000 0x0 0x10000>;
interrupts = <0 304 0>;
interface = <3 3 2>;
clocks = <&clk IMX8QM_IMG_PDMA_7_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX8QM_IMG_PDMA_7_CLK>;
assigned-clock-rates = <600000000>;
power-domains =<&pd_isi_ch7>;
status = "disabled";
};
mipi_csi_0: csi@58227000 {
compatible = "fsl,mxc-mipi-csi2";
reg = <0x0 0x58227000 0x0 0x1000>, /* CSI0 Controler base addr */
<0x0 0x58221000 0x0 0x1000>; /* CSI0 Subsystem CSR base addr */
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&irqsteer_csi0>;
clocks = <&clk IMX8QM_CLK_DUMMY>,
<&clk IMX8QM_CSI0_CORE_CLK>,
<&clk IMX8QM_CSI0_ESC_CLK>,
<&clk IMX8QM_IMG_PXL_LINK_CSI0_CLK>;
clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
assigned-clocks = <&clk IMX8QM_CSI0_CORE_CLK>,
<&clk IMX8QM_CSI0_ESC_CLK>;
assigned-clock-rates = <360000000>, <72000000>;
power-domains = <&pd_csi0>;
status = "disabled";
};
mipi_csi_1: csi@58247000 {
compatible = "fsl,mxc-mipi-csi2";
reg = <0x0 0x58247000 0x0 0x1000>, /* CSI1 Controler base addr */
<0x0 0x58241000 0x0 0x1000>; /* CSI1 Subsystem CSR base addr */
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&irqsteer_csi1>;
clocks = <&clk IMX8QM_CLK_DUMMY>,
<&clk IMX8QM_CSI1_CORE_CLK>,
<&clk IMX8QM_CSI1_ESC_CLK>,
<&clk IMX8QM_IMG_PXL_LINK_CSI1_CLK>;
clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
assigned-clocks = <&clk IMX8QM_CSI1_CORE_CLK>,
<&clk IMX8QM_CSI1_ESC_CLK>;
assigned-clock-rates = <360000000>, <72000000>;
power-domains = <&pd_csi1>;
status = "disabled";
};
hdmi_rx: hdmi_rx@58268000 {
compatible = "fsl,imx-hdmi-rx";
reg = <0x0 0x58268000 0x0 0x10000>, /* HDP Controller */
<0x0 0x58261000 0x0 0x1000>; /* HDP SubSystem CSR */
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
<13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "plug_in", "plug_out";
interrupt-parent = <&irqsteer_hdmi_rx>;
clocks = <&clk IMX8QM_HDMI_RX_HD_REF_CLK>,
<&clk IMX8QM_HDMI_RX_HD_CORE_CLK>,
<&clk IMX8QM_HDMI_RX_PXL_CLK>,
<&clk IMX8QM_HDMI_RX_SINK_PCLK>,
<&clk IMX8QM_HDMI_RX_SINK_SCLK>,
<&clk IMX8QM_HDMI_RX_PXL_ENC_CLK>,
<&clk IMX8QM_HDMI_RX_I2S_CLK>,
<&clk IMX8QM_HDMI_RX_SPDIF_CLK>,
<&clk IMX8QM_IMG_PXL_LINK_HDMI_IN_CLK>;
clock-names = "ref_clk", "core_clk", "pxl_clk",
"pclk", "sclk", "enc_clk",
"i2s_clk", "spdif_clk",
"pxl_link_clk";
power-domains = <&pd_hdmi_rx_bypass>;
status = "disabled";
};
jpegdec: jpegdec@58400000 {
compatible = "fsl,imx8-jpgdec";
reg = <0x0 0x58400000 0x0 0x00040020 >;
interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8QM_IMG_JPEG_DEC_IPG_CLK >,
<&clk IMX8QM_IMG_JPEG_DEC_CLK >;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8QM_IMG_JPEG_DEC_IPG_CLK >,
<&clk IMX8QM_IMG_JPEG_DEC_CLK >;
assigned-clock-rates = <200000000>;
power-domains =<&pd_jpgdec>;
};
jpegenc: jpegenc@58450000 {
compatible = "fsl,imx8-jpgenc";
reg = <0x0 0x58450000 0x0 0x00240020 >;
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8QM_IMG_JPEG_ENC_IPG_CLK >,
<&clk IMX8QM_IMG_JPEG_ENC_CLK >;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8QM_IMG_JPEG_ENC_IPG_CLK >,
<&clk IMX8QM_IMG_JPEG_ENC_CLK >;
assigned-clock-rates = <200000000>;
power-domains =<&pd_jpgenc>;
};
};
adc0: adc@5a880000 {
compatible = "fsl,imx8qxp-adc";
reg = <0x0 0x5a880000 0x0 0x10000>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&clk IMX8QM_ADC0_CLK>,
<&clk IMX8QM_ADC0_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_ADC0_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_dma_adc0>;
status = "disabled";
};
adc1: adc@5a890000 {
compatible = "fsl,imx8qxp-adc";
reg = <0x0 0x5a890000 0x0 0x10000>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&clk IMX8QM_ADC1_CLK>,
<&clk IMX8QM_ADC1_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_ADC1_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_dma_adc1>;
status = "disabled";
};
i2c0: i2c@5a800000 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x0 0x5a800000 0x0 0x4000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&clk IMX8QM_I2C0_CLK>,
<&clk IMX8QM_I2C0_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_I2C0_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_dma_lpi2c0>;
status = "disabled";
};
i2c1: i2c@5a810000 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x0 0x5a810000 0x0 0x4000>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&clk IMX8QM_I2C1_CLK>,
<&clk IMX8QM_I2C1_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_I2C1_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_dma_lpi2c1>;
status = "disabled";
};
i2c2: i2c@5a820000 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x0 0x5a820000 0x0 0x4000>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&clk IMX8QM_I2C2_CLK>,
<&clk IMX8QM_I2C2_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_I2C2_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_dma_lpi2c2>;
status = "disabled";
};
i2c3: i2c@5a830000 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x0 0x5a830000 0x0 0x4000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&clk IMX8QM_I2C3_CLK>,
<&clk IMX8QM_I2C3_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_I2C3_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_dma_lpi2c3>;
status = "disabled";
};
i2c4: i2c@5a840000 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x0 0x5a840000 0x0 0x4000>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&clk IMX8QM_I2C4_CLK>,
<&clk IMX8QM_I2C4_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_I2C4_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_dma_lpi2c4>;
status = "disabled";
};
i2c0_cm40: i2c@37230000 {
compatible = "fsl,imx8qm-lpi2c";
reg = <0x0 0x37230000 0x0 0x1000>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intmux_cm40>;
clocks = <&clk IMX8QM_CM40_I2C_CLK>,
<&clk IMX8QM_CM40_I2C_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_CM40_I2C_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_cm40_i2c>;
status = "disabled";
};
i2c0_cm41: i2c@3b230000 {
compatible = "fsl,imx8qm-lpi2c";
reg = <0x0 0x3b230000 0x0 0x1000>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intmux_cm41>;
clocks = <&clk IMX8QM_CM41_I2C_CLK>,
<&clk IMX8QM_CM41_I2C_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_CM41_I2C_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_cm41_i2c>;
status = "disabled";
};
irqsteer_hdmi: irqsteer@56260000 {
compatible = "nxp,imx-irqsteer";
reg = <0x0 0x56260000 0x0 0x1000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
clocks = <&clk IMX8QM_HDMI_LIS_IPG_CLK>;
clock-names = "ipg";
assigned-clocks = <&clk IMX8QM_HDMI_DIG_PLL_CLK>,
<&clk IMX8QM_HDMI_LIS_IPG_CLK>;
assigned-clock-rates = <675000000>, <84375000>;
power-domains = <&pd_hdmi>;
status = "disabled";
};
irqsteer_hdmi_rx: irqsteer@58260000 {
compatible = "nxp,imx-irqsteer";
reg = <0x0 0x58260000 0x0 0x1000>;
interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clk IMX8QM_HDMI_RX_IPG_CLK>;
clock-names = "ipg";
power-domains = <&pd_hdmi_rx>;
};
i2c0_hdmi: i2c@56266000 {
compatible = "fsl,imx8qm-lpi2c";
reg = <0x0 0x56266000 0x0 0x1000>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&irqsteer_hdmi>;
clocks = <&clk IMX8QM_HDMI_I2C0_CLK>,
<&clk IMX8QM_HDMI_I2C_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_HDMI_I2C0_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_hdmi_i2c0>;
status = "disabled";
};
irqsteer_lvds0: irqsteer@562400000 {
compatible = "nxp,imx-irqsteer";
reg = <0x0 0x56240000 0x0 0x1000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
clocks = <&clk IMX8QM_LVDS0_LIS_IPG_CLK>;
clock-names = "ipg";
power-domains = <&pd_lvds0>;
};
flexcan1: can@5a8d0000 {
compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan";
reg = <0x0 0x5a8d0000 0x0 0x10000>;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&wu>;
clocks = <&clk IMX8QM_CAN0_IPG_CLK>,
<&clk IMX8QM_CAN0_CLK>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8QM_CAN0_CLK>;
assigned-clock-rates = <40000000>;
power-domains = <&pd_dma_flexcan0>;
status = "disabled";
};
flexcan2: can@5a8e0000 {
compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan";
reg = <0x0 0x5a8e0000 0x0 0x10000>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&wu>;
clocks = <&clk IMX8QM_CAN1_IPG_CLK>,
<&clk IMX8QM_CAN1_CLK>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8QM_CAN1_CLK>;
assigned-clock-rates = <40000000>;
power-domains = <&pd_dma_flexcan1>;
status = "disabled";
};
flexcan3: can@5a8f0000 {
compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan";
reg = <0x0 0x5a8f0000 0x0 0x10000>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&wu>;
clocks = <&clk IMX8QM_CAN2_IPG_CLK>,
<&clk IMX8QM_CAN2_CLK>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8QM_CAN2_CLK>;
assigned-clock-rates = <40000000>;
power-domains = <&pd_dma_flexcan2>;
status = "disabled";
};
i2c1_lvds0: i2c@56247000 {
compatible = "fsl,imx8qm-lpi2c";
reg = <0x0 0x56247000 0x0 0x1000>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&irqsteer_lvds0>;
clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>,
<&clk IMX8QM_LVDS0_I2C0_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_lvds0_i2c0>;
status = "disabled";
};
irqsteer_lvds1: irqsteer@572400000 {
compatible = "nxp,imx-irqsteer";
reg = <0x0 0x57240000 0x0 0x1000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
clocks = <&clk IMX8QM_LVDS1_LIS_IPG_CLK>;
clock-names = "ipg";
power-domains = <&pd_lvds1>;
};
i2c1_lvds1: i2c@57247000 {
compatible = "fsl,imx8qm-lpi2c";
reg = <0x0 0x57247000 0x0 0x1000>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&irqsteer_lvds1>;
clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>,
<&clk IMX8QM_LVDS1_I2C0_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_lvds1_i2c0>;
status = "disabled";
};
irqsteer_csi0: irqsteer@58220000 {
compatible = "nxp,imx-irqsteer";
reg = <0x0 0x58220000 0x0 0x1000>;
interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
clocks = <&clk IMX8QM_CLK_DUMMY>;
clock-names = "ipg";
power-domains = <&pd_csi0>;
};
i2c0_mipi_csi0: i2c@58226000 {
compatible = "fsl,imx8qm-lpi2c";
reg = <0x0 0x58226000 0x0 0x1000>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&irqsteer_csi0>;
clocks = <&clk IMX8QM_CSI0_I2C0_CLK>,
<&clk IMX8QM_CSI0_I2C0_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_CSI0_I2C0_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_csi0_i2c0>;
status = "disabled";
};
irqsteer_csi1: irqsteer@582400000 {
compatible = "nxp,imx-irqsteer";
reg = <0x0 0x58240000 0x0 0x1000>;
interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
clocks = <&clk IMX8QM_CLK_DUMMY>;
clock-names = "ipg";
power-domains = <&pd_csi1>;
};
i2c0_mipi_csi1: i2c@58246000 {
compatible = "fsl,imx8qm-lpi2c";
reg = <0x0 0x58246000 0x0 0x1000>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&irqsteer_csi1>;
clocks = <&clk IMX8QM_CSI1_I2C0_CLK>,
<&clk IMX8QM_CSI1_I2C0_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_CSI1_I2C0_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_csi1_i2c0>;
status = "disabled";
};
lpspi0: lpspi@5a000000 {
compatible = "fsl,imx7ulp-spi";
reg = <0x0 0x5a000000 0x0 0x10000>;
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&clk IMX8QM_SPI0_CLK>,
<&clk IMX8QM_SPI0_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_SPI0_CLK>;
assigned-clock-rates = <20000000>;
power-domains = <&pd_dma0_chan1>;
dma-names = "tx","rx";
dmas = <&edma0 1 0 0>, <&edma0 0 0 1>;
status = "disabled";
};
lpspi3: lpspi@5a030000 {
compatible = "fsl,imx7ulp-spi";
reg = <0x0 0x5a030000 0x0 0x10000>;
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&clk IMX8QM_SPI3_CLK>,
<&clk IMX8QM_SPI3_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_SPI3_CLK>;
assigned-clock-rates = <60000000>;
power-domains = <&pd_dma0_chan7>;
dma-names = "tx","rx";
dmas = <&edma0 7 0 0>, <&edma0 6 0 1>;
status = "disabled";
};
lpuart0: serial@5a060000 {
compatible = "fsl,imx8qm-lpuart";
reg = <0x0 0x5a060000 0x0 0x1000>;
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&wu>;
clocks = <&clk IMX8QM_UART0_CLK>,
<&clk IMX8QM_UART0_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_UART0_CLK>;
assigned-clock-rates = <80000000>;
power-domains = <&pd_dma_lpuart0>;
status = "disabled";
};
lpuart1: serial@5a070000 {
compatible = "fsl,imx8qm-lpuart";
reg = <0x0 0x5a070000 0x0 0x1000>;
interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&wu>;
clocks = <&clk IMX8QM_UART1_CLK>,
<&clk IMX8QM_UART1_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_UART1_CLK>;
assigned-clock-rates = <80000000>;
power-domains = <&pd_dma0_chan15>;
dma-names = "tx","rx";
dmas = <&edma0 15 0 0>,
<&edma0 14 0 1>;
status = "disabled";
};
lpuart2: serial@5a080000 {
compatible = "fsl,imx8qm-lpuart";
reg = <0x0 0x5a080000 0x0 0x1000>;
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&wu>;
clocks = <&clk IMX8QM_UART2_CLK>,
<&clk IMX8QM_UART2_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_UART2_CLK>;
assigned-clock-rates = <80000000>;
power-domains = <&pd_dma0_chan17>;
dma-names = "tx","rx";
dmas = <&edma0 17 0 0>,
<&edma0 16 0 1>;
status = "disabled";
};
lpuart3: serial@5a090000 {
compatible = "fsl,imx8qm-lpuart";
reg = <0x0 0x5a090000 0x0 0x1000>;
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&wu>;
clocks = <&clk IMX8QM_UART3_CLK>,
<&clk IMX8QM_UART3_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_UART3_CLK>;
assigned-clock-rates = <80000000>;
power-domains = <&pd_dma0_chan19>;
dma-names = "tx","rx";
dmas = <&edma0 19 0 0>,
<&edma0 18 0 1>;
status = "disabled";
};
lpuart4: serial@5a0a0000 {
compatible = "fsl,imx8qm-lpuart";
reg = <0x0 0x5a0a0000 0x0 0x1000>;
interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&wu>;
clocks = <&clk IMX8QM_UART4_CLK>,
<&clk IMX8QM_UART4_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_UART4_CLK>;
assigned-clock-rates = <80000000>;
power-domains = <&pd_dma0_chan21>;
dma-names = "tx","rx";
dmas = <&edma0 21 0 0>,
&l