board/freescale/mx6qarm2/imximage_mx6dl.cfg - uboot-imx - Git at Google

 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  * Jason Liu <r64343@freescale.com>
  *
  * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
  */

 #define __ASSEMBLY__
 #include <config.h>

 /* image version */
 IMAGE_VERSION 2

 /*
  * Boot Device : one of
  * spi, sd (the board has no nand neither onenand)
  */
 BOOT_FROM	sd

 #ifdef CONFIG_USE_IMXIMG_PLUGIN
 /*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
 PLUGIN board/freescale/mx6qarm2/plugin.bin 0x00907000
 #else

 #ifdef CONFIG_SECURE_BOOT
 CSF CONFIG_CSF_SIZE
 #endif

 /*
  * Device Configuration Data (DCD)
  *
  * Each entry must have the format:
  * Addr-type           Address        Value
  *
  * where:
  *	Addr-type register length (1,2 or 4 bytes)
  *	Address	  absolute address of the register
  *	value	  value to be stored in the register
  */


 #ifdef CONFIG_MX6DL_LPDDR2

 /* IOMUX SETTINGS */
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
 DATA 4 0x020E04bc 0x00003028
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
 DATA 4 0x020E04c0 0x00003028
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */
 DATA 4 0x020E04c4 0x00003028
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */
 DATA 4 0x020E04c8 0x00003028
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */
 DATA 4 0x020E04cc 0x00003028
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */
 DATA 4 0x020E04d0 0x00003028
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */
 DATA 4 0x020E04d4 0x00003028
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */
 DATA 4 0x020E04d8 0x00003028

 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
 DATA 4 0x020E0470 0x00000038
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
 DATA 4 0x020E0474 0x00000038
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */
 DATA 4 0x020E0478 0x00000038
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */
 DATA 4 0x020E047c 0x00000038
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */
 DATA 4 0x020E0480 0x00000038
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */
 DATA 4 0x020E0484 0x00000038
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */
 DATA 4 0x020E0488 0x00000038
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */
 DATA 4 0x020E048c 0x00000038
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
 DATA 4 0x020E0464 0x00000038
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
 DATA 4 0x020E0490 0x00000038
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
 DATA 4 0x020E04ac 0x00000038
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */
 DATA 4 0x020E04b0 0x00000038
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
 DATA 4 0x020E0494 0x00000038
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */
 DATA 4 0x020E04a4 0x00000038
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */
 DATA 4 0x020E04a8 0x00000038
 /*
  * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
  * DSE can be configured using Group Control Register:
  * IOMUXC_SW_PAD_CTL_GRP_CTLDS
  */
 DATA 4 0x020E04a0 0x00000000
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
 DATA 4 0x020E04b4 0x00000038
 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
 DATA 4 0x020E04b8 0x00000038
 /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
 DATA 4 0x020E0764 0x00000038
 /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
 DATA 4 0x020E0770 0x00000038
 /* IOMUXC_SW_PAD_CTL_GRP_B2DS */
 DATA 4 0x020E0778 0x00000038
 /* IOMUXC_SW_PAD_CTL_GRP_B3DS */
 DATA 4 0x020E077c 0x00000038
 /* IOMUXC_SW_PAD_CTL_GRP_B4DS */
 DATA 4 0x020E0780 0x00000038
 /* IOMUXC_SW_PAD_CTL_GRP_B5DS */
 DATA 4 0x020E0784 0x00000038
 /* IOMUXC_SW_PAD_CTL_GRP_B6DS */
 DATA 4 0x020E078c 0x00000038
 /* IOMUXC_SW_PAD_CTL_GRP_B7DS */
 DATA 4 0x020E0748 0x00000038
 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
 DATA 4 0x020E074c 0x00000038
 /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
 DATA 4 0x020E076c 0x00000038
 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
 DATA 4 0x020E0750 0x00020000
 /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
 DATA 4 0x020E0754 0x00000000
 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
 DATA 4 0x020E0760 0x00020000
 /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
 DATA 4 0x020E0774 0x00080000

 /*
  * DDR Controller Registers
  *
  * Manufacturer:	Mocron
  * Device Part Number:	MT42L64M64D2KH-18
  * Clock Freq.: 	528MHz
  * MMDC channels: Both MMDC0, MMDC1
  *Density per CS in Gb: 	256M
  * Chip Selects used:	2
  * Number of Banks:	8
  * Row address:    	14
  * Column address: 	9
  * Data bus width	32
  */

 /* MMDC_P0_BASE_ADDR = 0x021b0000 */
 /* MMDC_P1_BASE_ADDR = 0x021b4000 */

 /* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
 DATA 4 0x021b001c 0x00008000

 /* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
 DATA 4 0x021b401c 0x00008000

 /*LPDDR2 ZQ params */
 DATA 4 0x021b085c 0x1b5f01ff
 DATA 4 0x021b485c 0x1b5f01ff

 /* Calibration setup. */
 /* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */
 DATA 4 0x021b0800 0xa1390003

 /*ca bus abs delay */
 DATA 4 0x021b0890 0x00400000
 /*ca bus abs delay */
 DATA 4 0x021b4890 0x00400000
 /* values of 20,40,50,60,7f tried. no difference seen */

 /* DDR_PHY_P1_MPWRCADL */
 DATA 4 0x021b48bc 0x00055555

 /*frc_msr.*/
 DATA 4 0x021b08b8 0x00000800
 /*frc_msr.*/
 DATA 4 0x021b48b8 0x00000800

 /* DDR_PHY_P0_MPREDQBY0DL3 */
 DATA 4 0x021b081c 0x33333333
 /* DDR_PHY_P0_MPREDQBY1DL3 */
 DATA 4 0x021b0820 0x33333333
 /* DDR_PHY_P0_MPREDQBY2DL3 */
 DATA 4 0x021b0824 0x33333333
 /* DDR_PHY_P0_MPREDQBY3DL3 */
 DATA 4 0x021b0828 0x33333333
 /* DDR_PHY_P1_MPREDQBY0DL3 */
 DATA 4 0x021b481c 0x33333333
 /* DDR_PHY_P1_MPREDQBY1DL3 */
 DATA 4 0x021b4820 0x33333333
 /* DDR_PHY_P1_MPREDQBY2DL3 */
 DATA 4 0x021b4824 0x33333333
 /* DDR_PHY_P1_MPREDQBY3DL3 */
 DATA 4 0x021b4828 0x33333333

 /*
  * Read and write data delay, per byte.
  * For optimized DDR operation it is recommended to run mmdc_calibration
  * on your board, and replace 4 delay register assigns with resulted values
  * Note:
  * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section
  *    should be skipped, or the write/read calibration comming after that
  *    will stall
  * b. The calibration code that runs for both MMDC0 & MMDC1 should be used.
  */

 DATA 4 0x021b0848 0x4b4b524f
 DATA 4 0x021b4848 0x494f4c44

 DATA 4 0x021b0850 0x3c3d303c
 DATA 4 0x021b4850 0x3c343d38

 /*dqs gating dis */
 DATA 4 0x021b083c 0x20000000
 DATA 4 0x021b0840 0x0
 DATA 4 0x021b483c 0x20000000
 DATA 4 0x021b4840 0x0

 /*clk delay */
 DATA 4 0x021b0858 0xa00
 /*clk delay */
 DATA 4 0x021b4858 0xa00

 /*frc_msr */
 DATA 4 0x021b08b8 0x00000800
 /*frc_msr */
 DATA 4 0x021b48b8 0x00000800
 /* Calibration setup end */

 /* Channel0 - startng address 0x80000000 */
 /* MMDC0_MDCFG0 */
 DATA 4 0x021b000c 0x34386145

 /* MMDC0_MDPDC */
 DATA 4 0x021b0004 0x00020036
 /* MMDC0_MDCFG1 */
 DATA 4 0x021b0010 0x00100c83
 /* MMDC0_MDCFG2 */
 DATA 4 0x021b0014 0x000000Dc
 /* MMDC0_MDMISC */
 DATA 4 0x021b0018 0x0000174C
 /* MMDC0_MDRWD;*/
 DATA 4 0x021b002c 0x0f9f26d2
 /* MMDC0_MDOR */
 DATA 4 0x021b0030 0x009f0e10
 /* MMDC0_MDCFG3LP */
 DATA 4 0x021b0038 0x00190778
 /* MMDC0_MDOTC */
 DATA 4 0x021b0008 0x00000000

 /* CS0_END */
 DATA 4 0x021b0040 0x0000005f
 /* ROC */
 DATA 4 0x021b0404 0x0000000f

 /* MMDC0_MDCTL */
 DATA 4 0x021b0000 0xc3010000

 /* Channel1 - starting address 0x10000000 */
 /* MMDC1_MDCFG0 */
 DATA 4 0x021b400c 0x34386145

 /* MMDC1_MDPDC */
 DATA 4 0x021b4004 0x00020036
 /* MMDC1_MDCFG1 */
 DATA 4 0x021b4010 0x00100c83
 /* MMDC1_MDCFG2 */
 DATA 4 0x021b4014 0x000000Dc
 /* MMDC1_MDMISC */
 DATA 4 0x021b4018 0x0000174C
 /* MMDC1_MDRWD;*/
 DATA 4 0x021b402c 0x0f9f26d2
 /* MMDC1_MDOR */
 DATA 4 0x021b4030 0x009f0e10
 /* MMDC1_MDCFG3LP */
 DATA 4 0x021b4038 0x00190778
 /* MMDC1_MDOTC */
 DATA 4 0x021b4008 0x00000000

 /* CS0_END */
 DATA 4 0x021b4040 0x0000003f

 /* MMDC1_MDCTL */
 DATA 4 0x021b4000 0xc3010000

 /* Channel0 : Configure DDR device:*/
 /* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
 DATA 4 0x021b001c 0x003f8030
 /* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
 DATA 4 0x021b001c 0xff0a8030
 /* MRW: BA=0 CS=0 MR_ADDR=1  MR_OP=a2 */
 DATA 4 0x021b001c 0xa2018030
 /* MRW: BA=0 CS=0 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4 */
 DATA 4 0x021b001c 0x06028030
 /* MRW: BA=0 CS=0 MR_ADDR=3  MR_OP=2.drive=240/6 */
 DATA 4 0x021b001c 0x01038030

 /* Channel1 : Configure DDR device:*/
 /* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
 DATA 4 0x021b401c 0x003f8030
 /* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
 DATA 4 0x021b401c 0xff0a8030
 /* MRW: BA=0 CS=0 MR_ADDR=1  MR_OP=a2 */
 DATA 4 0x021b401c 0xa2018030
 /* MRW: BA=0 CS=0 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4 */
 DATA 4 0x021b401c 0x06028030
 /* MRW: BA=0 CS=0 MR_ADDR=3  MR_OP=2.drive=240/6 */
 DATA 4 0x021b401c 0x01038030

 /* MMDC0_MDREF */
 DATA 4 0x021b0020 0x00005800
 /* MMDC1_MDREF */
 DATA 4 0x021b4020 0x00005800

 /* DDR_PHY_P0_MPODTCTRL */
 DATA 4 0x021b0818 0x0
 /* DDR_PHY_P1_MPODTCTRL */
 DATA 4 0x021b4818 0x0

 /*
  * calibration values based on calibration compare of 0x00ffff00:
  * Note, these calibration values are based on Freescale's board
  * May need to run calibration on target board to fine tune these
  */

 /* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */
 DATA 4 0x021b0800 0xa1310003

 /* DDR_PHY_P0_MPMUR0, frc_msr */
 DATA 4 0x021b08b8 0x00000800
 /* DDR_PHY_P1_MPMUR0, frc_msr */
 DATA 4 0x021b48b8 0x00000800

 /*
  * MMDC0_MDSCR, clear this register
  * (especially the configuration bit as initialization is complete)
  */
 DATA 4 0x021b001c 0x00000000
 /*
  * MMDC0_MDSCR, clear this register
  * (especially the configuration bit as initialization is complete)
  */
 DATA 4 0x021b401c 0x00000000

 DATA 4 0x020c4068 0x00C03F3F
 DATA 4 0x020c406c 0x0030FC03
 DATA 4 0x020c4070 0x0FFFC000
 DATA 4 0x020c4074 0x3FF00000
 DATA 4 0x020c4078 0x00FFF300
 DATA 4 0x020c407c 0x0F0000C3
 DATA 4 0x020c4080 0x000003FF

 DATA 4 0x020e0010 0xF00000CF
 DATA 4 0x020e0018 0x007F007F
 DATA 4 0x020e001c 0x007F007F

 #else /* CONFIG_MX6DL_LPDDR2 */

 DATA 4 0x020e0798 0x000c0000
 DATA 4 0x020e0758 0x00000000
 DATA 4 0x020e0588 0x00000030
 DATA 4 0x020e0594 0x00000030
 DATA 4 0x020e056c 0x00000030
 DATA 4 0x020e0578 0x00000030
 DATA 4 0x020e074c 0x00000030
 DATA 4 0x020e057c 0x00000030
 DATA 4 0x020e0590 0x00003000
 DATA 4 0x020e0598 0x00003000
 DATA 4 0x020e058c 0x00000000
 DATA 4 0x020e059c 0x00003030
 DATA 4 0x020e05a0 0x00003030
 DATA 4 0x020e078c 0x00000030
 DATA 4 0x020e0750 0x00020000
 DATA 4 0x020e05a8 0x00000030
 DATA 4 0x020e05b0 0x00000030
 DATA 4 0x020e0524 0x00000030
 DATA 4 0x020e051c 0x00000030
 DATA 4 0x020e0518 0x00000030
 DATA 4 0x020e050c 0x00000030
 DATA 4 0x020e05b8 0x00000030
 DATA 4 0x020e05c0 0x00000030
 DATA 4 0x020e0774 0x00020000
 DATA 4 0x020e0784 0x00000030
 DATA 4 0x020e0788 0x00000030
 DATA 4 0x020e0794 0x00000030
 DATA 4 0x020e079c 0x00000030
 DATA 4 0x020e07a0 0x00000030
 DATA 4 0x020e07a4 0x00000030
 DATA 4 0x020e07a8 0x00000030
 DATA 4 0x020e0748 0x00000030
 DATA 4 0x020e05ac 0x00000030
 DATA 4 0x020e05b4 0x00000030
 DATA 4 0x020e0528 0x00000030
 DATA 4 0x020e0520 0x00000030
 DATA 4 0x020e0514 0x00000030
 DATA 4 0x020e0510 0x00000030
 DATA 4 0x020e05bc 0x00000030
 DATA 4 0x020e05c4 0x00000030

 DATA 4 0x021b0800 0xa1390003
 DATA 4 0x021b4800 0xa1390003
 DATA 4 0x021b080c 0x001F001F
 DATA 4 0x021b0810 0x001F001F
 DATA 4 0x021b480c 0x00370037
 DATA 4 0x021b4810 0x00370037
 DATA 4 0x021b083c 0x422f0220
 DATA 4 0x021b0840 0x021f0219
 DATA 4 0x021b483C 0x422f0220
 DATA 4 0x021b4840 0x022d022f
 DATA 4 0x021b0848 0x47494b49
 DATA 4 0x021b4848 0x48484c47
 DATA 4 0x021b0850 0x39382b2f
 DATA 4 0x021b4850 0x2f35312c
 DATA 4 0x021b081c 0x33333333
 DATA 4 0x021b0820 0x33333333
 DATA 4 0x021b0824 0x33333333
 DATA 4 0x021b0828 0x33333333
 DATA 4 0x021b481c 0x33333333
 DATA 4 0x021b4820 0x33333333
 DATA 4 0x021b4824 0x33333333
 DATA 4 0x021b4828 0x33333333
 DATA 4 0x021b08b8 0x00000800
 DATA 4 0x021b48b8 0x00000800
 DATA 4 0x021b0004 0x0002002d
 DATA 4 0x021b0008 0x00333030

 DATA 4 0x021b000c 0x40445323
 DATA 4 0x021b0010 0xb66e8c63

 DATA 4 0x021b0014 0x01ff00db
 DATA 4 0x021b0018 0x00081740
 DATA 4 0x021b001c 0x00008000
 DATA 4 0x021b002c 0x000026d2
 DATA 4 0x021b0030 0x00440e21
 #ifdef CONFIG_DDR_32BIT
 DATA 4 0x021b0040 0x00000017
 DATA 4 0x021b0000 0xc3190000
 #else
 DATA 4 0x021b0040 0x00000027
 DATA 4 0x021b0000 0xc31a0000
 #endif
 DATA 4 0x021b001c 0x04008032
 DATA 4 0x021b001c 0x0400803a
 DATA 4 0x021b001c 0x00008033
 DATA 4 0x021b001c 0x0000803b
 DATA 4 0x021b001c 0x00428031
 DATA 4 0x021b001c 0x00428039
 DATA 4 0x021b001c 0x07208030
 DATA 4 0x021b001c 0x07208038
 DATA 4 0x021b001c 0x04008040
 DATA 4 0x021b001c 0x04008048
 DATA 4 0x021b0020 0x00005800
 DATA 4 0x021b0818 0x00000007
 DATA 4 0x021b4818 0x00000007
 DATA 4 0x021b0004 0x0002556d
 DATA 4 0x021b4004 0x00011006
 DATA 4 0x021b001c 0x00000000

 DATA 4 0x020c4068 0x00C03F3F
 DATA 4 0x020c406c 0x0030FC03
 DATA 4 0x020c4070 0x0FFFC000
 DATA 4 0x020c4074 0x3FF00000
 DATA 4 0x020c4078 0x00FFF300
 DATA 4 0x020c407c 0x0F0000C3
 DATA 4 0x020c4080 0x000003FF

 DATA 4 0x020e0010 0xF00000CF
 DATA 4 0x020e0018 0x007F007F
 DATA 4 0x020e001c 0x007F007F
 #endif /* CONFIG_MX6DL_LPDDR2 */
 #endif
	/* SPDX-License-Identifier: GPL-2.0+ */
	/*
	* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
	* Jason Liu <r64343@freescale.com>
	*
	* Refer doc/README.imximage for more details about how-to configure
	* and create imximage boot image
	*
	* The syntax is taken as close as possible with the kwbimage
	*/

	#define __ASSEMBLY__
	#include <config.h>

	/* image version */
	IMAGE_VERSION 2

	/*
	* Boot Device : one of
	* spi, sd (the board has no nand neither onenand)
	*/
	BOOT_FROM sd

	#ifdef CONFIG_USE_IMXIMG_PLUGIN
	/PLUGIN plugin-binary-file IRAM_FREE_START_ADDR/
	PLUGIN board/freescale/mx6qarm2/plugin.bin 0x00907000
	#else

	#ifdef CONFIG_SECURE_BOOT
	CSF CONFIG_CSF_SIZE
	#endif

	/*
	* Device Configuration Data (DCD)
	*
	* Each entry must have the format:
	* Addr-type Address Value
	*
	* where:
	* Addr-type register length (1,2 or 4 bytes)
	* Address absolute address of the register
	* value value to be stored in the register
	*/



	#ifdef CONFIG_MX6DL_LPDDR2

	/* IOMUX SETTINGS */
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
	DATA 4 0x020E04bc 0x00003028
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
	DATA 4 0x020E04c0 0x00003028
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */
	DATA 4 0x020E04c4 0x00003028
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */
	DATA 4 0x020E04c8 0x00003028
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */
	DATA 4 0x020E04cc 0x00003028
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */
	DATA 4 0x020E04d0 0x00003028
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */
	DATA 4 0x020E04d4 0x00003028
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */
	DATA 4 0x020E04d8 0x00003028

	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
	DATA 4 0x020E0470 0x00000038
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
	DATA 4 0x020E0474 0x00000038
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */
	DATA 4 0x020E0478 0x00000038
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */
	DATA 4 0x020E047c 0x00000038
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */
	DATA 4 0x020E0480 0x00000038
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */
	DATA 4 0x020E0484 0x00000038
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */
	DATA 4 0x020E0488 0x00000038
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */
	DATA 4 0x020E048c 0x00000038
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
	DATA 4 0x020E0464 0x00000038
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
	DATA 4 0x020E0490 0x00000038
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
	DATA 4 0x020E04ac 0x00000038
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */
	DATA 4 0x020E04b0 0x00000038
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
	DATA 4 0x020E0494 0x00000038
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */
	DATA 4 0x020E04a4 0x00000038
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */
	DATA 4 0x020E04a8 0x00000038
	/*
	* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
	* DSE can be configured using Group Control Register:
	* IOMUXC_SW_PAD_CTL_GRP_CTLDS
	*/
	DATA 4 0x020E04a0 0x00000000
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
	DATA 4 0x020E04b4 0x00000038
	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
	DATA 4 0x020E04b8 0x00000038
	/* IOMUXC_SW_PAD_CTL_GRP_B0DS */
	DATA 4 0x020E0764 0x00000038
	/* IOMUXC_SW_PAD_CTL_GRP_B1DS */
	DATA 4 0x020E0770 0x00000038
	/* IOMUXC_SW_PAD_CTL_GRP_B2DS */
	DATA 4 0x020E0778 0x00000038
	/* IOMUXC_SW_PAD_CTL_GRP_B3DS */
	DATA 4 0x020E077c 0x00000038
	/* IOMUXC_SW_PAD_CTL_GRP_B4DS */
	DATA 4 0x020E0780 0x00000038
	/* IOMUXC_SW_PAD_CTL_GRP_B5DS */
	DATA 4 0x020E0784 0x00000038
	/* IOMUXC_SW_PAD_CTL_GRP_B6DS */
	DATA 4 0x020E078c 0x00000038
	/* IOMUXC_SW_PAD_CTL_GRP_B7DS */
	DATA 4 0x020E0748 0x00000038
	/* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
	DATA 4 0x020E074c 0x00000038
	/* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
	DATA 4 0x020E076c 0x00000038
	/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
	DATA 4 0x020E0750 0x00020000
	/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
	DATA 4 0x020E0754 0x00000000
	/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
	DATA 4 0x020E0760 0x00020000
	/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
	DATA 4 0x020E0774 0x00080000

	/*
	* DDR Controller Registers
	*
	* Manufacturer: Mocron
	* Device Part Number: MT42L64M64D2KH-18
	* Clock Freq.: 528MHz
	* MMDC channels: Both MMDC0, MMDC1
	*Density per CS in Gb: 256M
	* Chip Selects used: 2
	* Number of Banks: 8
	* Row address: 14
	* Column address: 9
	* Data bus width 32
	*/

	/* MMDC_P0_BASE_ADDR = 0x021b0000 */
	/* MMDC_P1_BASE_ADDR = 0x021b4000 */

	/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
	DATA 4 0x021b001c 0x00008000

	/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
	DATA 4 0x021b401c 0x00008000

	/LPDDR2 ZQ params /
	DATA 4 0x021b085c 0x1b5f01ff
	DATA 4 0x021b485c 0x1b5f01ff

	/* Calibration setup. */
	/* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */
	DATA 4 0x021b0800 0xa1390003

	/ca bus abs delay /
	DATA 4 0x021b0890 0x00400000
	/ca bus abs delay /
	DATA 4 0x021b4890 0x00400000
	/* values of 20,40,50,60,7f tried. no difference seen */

	/* DDR_PHY_P1_MPWRCADL */
	DATA 4 0x021b48bc 0x00055555

	/frc_msr./
	DATA 4 0x021b08b8 0x00000800
	/frc_msr./
	DATA 4 0x021b48b8 0x00000800

	/* DDR_PHY_P0_MPREDQBY0DL3 */
	DATA 4 0x021b081c 0x33333333
	/* DDR_PHY_P0_MPREDQBY1DL3 */
	DATA 4 0x021b0820 0x33333333
	/* DDR_PHY_P0_MPREDQBY2DL3 */
	DATA 4 0x021b0824 0x33333333
	/* DDR_PHY_P0_MPREDQBY3DL3 */
	DATA 4 0x021b0828 0x33333333
	/* DDR_PHY_P1_MPREDQBY0DL3 */
	DATA 4 0x021b481c 0x33333333
	/* DDR_PHY_P1_MPREDQBY1DL3 */
	DATA 4 0x021b4820 0x33333333
	/* DDR_PHY_P1_MPREDQBY2DL3 */
	DATA 4 0x021b4824 0x33333333
	/* DDR_PHY_P1_MPREDQBY3DL3 */
	DATA 4 0x021b4828 0x33333333

	/*
	* Read and write data delay, per byte.
	* For optimized DDR operation it is recommended to run mmdc_calibration
	* on your board, and replace 4 delay register assigns with resulted values
	* Note:
	* a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section
	* should be skipped, or the write/read calibration comming after that
	* will stall
	* b. The calibration code that runs for both MMDC0 & MMDC1 should be used.
	*/

	DATA 4 0x021b0848 0x4b4b524f
	DATA 4 0x021b4848 0x494f4c44

	DATA 4 0x021b0850 0x3c3d303c
	DATA 4 0x021b4850 0x3c343d38

	/dqs gating dis /
	DATA 4 0x021b083c 0x20000000
	DATA 4 0x021b0840 0x0
	DATA 4 0x021b483c 0x20000000
	DATA 4 0x021b4840 0x0

	/clk delay /
	DATA 4 0x021b0858 0xa00
	/clk delay /
	DATA 4 0x021b4858 0xa00

	/frc_msr /
	DATA 4 0x021b08b8 0x00000800
	/frc_msr /
	DATA 4 0x021b48b8 0x00000800
	/* Calibration setup end */

	/* Channel0 - startng address 0x80000000 */
	/* MMDC0_MDCFG0 */
	DATA 4 0x021b000c 0x34386145

	/* MMDC0_MDPDC */
	DATA 4 0x021b0004 0x00020036
	/* MMDC0_MDCFG1 */
	DATA 4 0x021b0010 0x00100c83
	/* MMDC0_MDCFG2 */
	DATA 4 0x021b0014 0x000000Dc
	/* MMDC0_MDMISC */
	DATA 4 0x021b0018 0x0000174C
	/* MMDC0_MDRWD;*/
	DATA 4 0x021b002c 0x0f9f26d2
	/* MMDC0_MDOR */
	DATA 4 0x021b0030 0x009f0e10
	/* MMDC0_MDCFG3LP */
	DATA 4 0x021b0038 0x00190778
	/* MMDC0_MDOTC */
	DATA 4 0x021b0008 0x00000000

	/* CS0_END */
	DATA 4 0x021b0040 0x0000005f
	/* ROC */
	DATA 4 0x021b0404 0x0000000f

	/* MMDC0_MDCTL */
	DATA 4 0x021b0000 0xc3010000

	/* Channel1 - starting address 0x10000000 */
	/* MMDC1_MDCFG0 */
	DATA 4 0x021b400c 0x34386145

	/* MMDC1_MDPDC */
	DATA 4 0x021b4004 0x00020036
	/* MMDC1_MDCFG1 */
	DATA 4 0x021b4010 0x00100c83
	/* MMDC1_MDCFG2 */
	DATA 4 0x021b4014 0x000000Dc
	/* MMDC1_MDMISC */
	DATA 4 0x021b4018 0x0000174C
	/* MMDC1_MDRWD;*/
	DATA 4 0x021b402c 0x0f9f26d2
	/* MMDC1_MDOR */
	DATA 4 0x021b4030 0x009f0e10
	/* MMDC1_MDCFG3LP */
	DATA 4 0x021b4038 0x00190778
	/* MMDC1_MDOTC */
	DATA 4 0x021b4008 0x00000000

	/* CS0_END */
	DATA 4 0x021b4040 0x0000003f

	/* MMDC1_MDCTL */
	DATA 4 0x021b4000 0xc3010000

	/* Channel0 : Configure DDR device:*/
	/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
	DATA 4 0x021b001c 0x003f8030
	/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
	DATA 4 0x021b001c 0xff0a8030
	/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */
	DATA 4 0x021b001c 0xa2018030
	/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
	DATA 4 0x021b001c 0x06028030
	/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */
	DATA 4 0x021b001c 0x01038030

	/* Channel1 : Configure DDR device:*/
	/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
	DATA 4 0x021b401c 0x003f8030
	/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
	DATA 4 0x021b401c 0xff0a8030
	/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */
	DATA 4 0x021b401c 0xa2018030
	/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
	DATA 4 0x021b401c 0x06028030
	/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */
	DATA 4 0x021b401c 0x01038030

	/* MMDC0_MDREF */
	DATA 4 0x021b0020 0x00005800
	/* MMDC1_MDREF */
	DATA 4 0x021b4020 0x00005800

	/* DDR_PHY_P0_MPODTCTRL */
	DATA 4 0x021b0818 0x0
	/* DDR_PHY_P1_MPODTCTRL */
	DATA 4 0x021b4818 0x0

	/*
	* calibration values based on calibration compare of 0x00ffff00:
	* Note, these calibration values are based on Freescale's board
	* May need to run calibration on target board to fine tune these
	*/

	/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */
	DATA 4 0x021b0800 0xa1310003

	/* DDR_PHY_P0_MPMUR0, frc_msr */
	DATA 4 0x021b08b8 0x00000800
	/* DDR_PHY_P1_MPMUR0, frc_msr */
	DATA 4 0x021b48b8 0x00000800

	/*
	* MMDC0_MDSCR, clear this register
	* (especially the configuration bit as initialization is complete)
	*/
	DATA 4 0x021b001c 0x00000000
	/*
	* MMDC0_MDSCR, clear this register
	* (especially the configuration bit as initialization is complete)
	*/
	DATA 4 0x021b401c 0x00000000

	DATA 4 0x020c4068 0x00C03F3F
	DATA 4 0x020c406c 0x0030FC03
	DATA 4 0x020c4070 0x0FFFC000
	DATA 4 0x020c4074 0x3FF00000
	DATA 4 0x020c4078 0x00FFF300
	DATA 4 0x020c407c 0x0F0000C3
	DATA 4 0x020c4080 0x000003FF

	DATA 4 0x020e0010 0xF00000CF
	DATA 4 0x020e0018 0x007F007F
	DATA 4 0x020e001c 0x007F007F

	#else /* CONFIG_MX6DL_LPDDR2 */

	DATA 4 0x020e0798 0x000c0000
	DATA 4 0x020e0758 0x00000000
	DATA 4 0x020e0588 0x00000030
	DATA 4 0x020e0594 0x00000030
	DATA 4 0x020e056c 0x00000030
	DATA 4 0x020e0578 0x00000030
	DATA 4 0x020e074c 0x00000030
	DATA 4 0x020e057c 0x00000030
	DATA 4 0x020e0590 0x00003000
	DATA 4 0x020e0598 0x00003000
	DATA 4 0x020e058c 0x00000000
	DATA 4 0x020e059c 0x00003030
	DATA 4 0x020e05a0 0x00003030
	DATA 4 0x020e078c 0x00000030
	DATA 4 0x020e0750 0x00020000
	DATA 4 0x020e05a8 0x00000030
	DATA 4 0x020e05b0 0x00000030
	DATA 4 0x020e0524 0x00000030
	DATA 4 0x020e051c 0x00000030
	DATA 4 0x020e0518 0x00000030
	DATA 4 0x020e050c 0x00000030
	DATA 4 0x020e05b8 0x00000030
	DATA 4 0x020e05c0 0x00000030
	DATA 4 0x020e0774 0x00020000
	DATA 4 0x020e0784 0x00000030
	DATA 4 0x020e0788 0x00000030
	DATA 4 0x020e0794 0x00000030
	DATA 4 0x020e079c 0x00000030
	DATA 4 0x020e07a0 0x00000030
	DATA 4 0x020e07a4 0x00000030
	DATA 4 0x020e07a8 0x00000030
	DATA 4 0x020e0748 0x00000030
	DATA 4 0x020e05ac 0x00000030
	DATA 4 0x020e05b4 0x00000030
	DATA 4 0x020e0528 0x00000030
	DATA 4 0x020e0520 0x00000030
	DATA 4 0x020e0514 0x00000030
	DATA 4 0x020e0510 0x00000030
	DATA 4 0x020e05bc 0x00000030
	DATA 4 0x020e05c4 0x00000030

	DATA 4 0x021b0800 0xa1390003
	DATA 4 0x021b4800 0xa1390003
	DATA 4 0x021b080c 0x001F001F
	DATA 4 0x021b0810 0x001F001F
	DATA 4 0x021b480c 0x00370037
	DATA 4 0x021b4810 0x00370037
	DATA 4 0x021b083c 0x422f0220
	DATA 4 0x021b0840 0x021f0219
	DATA 4 0x021b483C 0x422f0220
	DATA 4 0x021b4840 0x022d022f
	DATA 4 0x021b0848 0x47494b49
	DATA 4 0x021b4848 0x48484c47
	DATA 4 0x021b0850 0x39382b2f
	DATA 4 0x021b4850 0x2f35312c
	DATA 4 0x021b081c 0x33333333
	DATA 4 0x021b0820 0x33333333
	DATA 4 0x021b0824 0x33333333
	DATA 4 0x021b0828 0x33333333
	DATA 4 0x021b481c 0x33333333
	DATA 4 0x021b4820 0x33333333
	DATA 4 0x021b4824 0x33333333
	DATA 4 0x021b4828 0x33333333
	DATA 4 0x021b08b8 0x00000800
	DATA 4 0x021b48b8 0x00000800
	DATA 4 0x021b0004 0x0002002d
	DATA 4 0x021b0008 0x00333030

	DATA 4 0x021b000c 0x40445323
	DATA 4 0x021b0010 0xb66e8c63

	DATA 4 0x021b0014 0x01ff00db
	DATA 4 0x021b0018 0x00081740
	DATA 4 0x021b001c 0x00008000
	DATA 4 0x021b002c 0x000026d2
	DATA 4 0x021b0030 0x00440e21
	#ifdef CONFIG_DDR_32BIT
	DATA 4 0x021b0040 0x00000017
	DATA 4 0x021b0000 0xc3190000
	#else
	DATA 4 0x021b0040 0x00000027
	DATA 4 0x021b0000 0xc31a0000
	#endif
	DATA 4 0x021b001c 0x04008032
	DATA 4 0x021b001c 0x0400803a
	DATA 4 0x021b001c 0x00008033
	DATA 4 0x021b001c 0x0000803b
	DATA 4 0x021b001c 0x00428031
	DATA 4 0x021b001c 0x00428039
	DATA 4 0x021b001c 0x07208030
	DATA 4 0x021b001c 0x07208038
	DATA 4 0x021b001c 0x04008040
	DATA 4 0x021b001c 0x04008048
	DATA 4 0x021b0020 0x00005800
	DATA 4 0x021b0818 0x00000007
	DATA 4 0x021b4818 0x00000007
	DATA 4 0x021b0004 0x0002556d
	DATA 4 0x021b4004 0x00011006
	DATA 4 0x021b001c 0x00000000

	DATA 4 0x020c4068 0x00C03F3F
	DATA 4 0x020c406c 0x0030FC03
	DATA 4 0x020c4070 0x0FFFC000
	DATA 4 0x020c4074 0x3FF00000
	DATA 4 0x020c4078 0x00FFF300
	DATA 4 0x020c407c 0x0F0000C3
	DATA 4 0x020c4080 0x000003FF

	DATA 4 0x020e0010 0xF00000CF
	DATA 4 0x020e0018 0x007F007F
	DATA 4 0x020e001c 0x007F007F
	#endif /* CONFIG_MX6DL_LPDDR2 */
	#endif