| /* |
| * Copyright 2018 NXP |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #include <linux/kernel.h> |
| #include <common.h> |
| #include <asm/arch/ddr.h> |
| |
| struct dram_cfg_param ddr4_ddrc_cfg[] = { |
| /* Start to config, default 2400mbps */ |
| { DDRC_MSTR(0), 0x81040010 }, |
| { DDRC_PWRCTL(0), 0x000000aa }, |
| { DDRC_PWRTMG(0), 0x00221306 }, |
| { DDRC_RFSHCTL0(0), 0x00c0a070 }, |
| { DDRC_RFSHCTL1(0), 0x00010008 }, |
| { DDRC_RFSHCTL3(0), 0x00000000 }, |
| { DDRC_RFSHTMG(0), 0x004980f4 }, |
| { DDRC_CRCPARCTL0(0), 0x00000000 }, |
| { DDRC_CRCPARCTL1(0), 0x00001010 }, |
| { DDRC_INIT0(0), 0xc0030002 }, |
| { DDRC_INIT1(0), 0x00020009 }, |
| { DDRC_INIT2(0), 0x0000350f }, |
| { DDRC_INIT3(0), (0xa34 << 16) | 0x105 }, |
| { DDRC_INIT4(0), (0x1028 << 16) | 0x200 }, |
| { DDRC_INIT5(0), 0x001103cb }, |
| { DDRC_INIT6(0), (0x200 << 16) | 0x200 }, |
| { DDRC_INIT7(0), 0x814 }, |
| { DDRC_DIMMCTL(0), 0x00000032 }, |
| { DDRC_RANKCTL(0), 0x00000fc7 }, |
| { DDRC_DRAMTMG0(0), 0x14132813 }, |
| { DDRC_DRAMTMG1(0), 0x0004051b }, |
| { DDRC_DRAMTMG2(0), 0x0808030f }, |
| { DDRC_DRAMTMG3(0), 0x0000400c }, |
| { DDRC_DRAMTMG4(0), 0x08030409 }, |
| { DDRC_DRAMTMG5(0), 0x0e090504 }, |
| { DDRC_DRAMTMG6(0), 0x05030000 }, |
| { DDRC_DRAMTMG7(0), 0x0000090e }, |
| { DDRC_DRAMTMG8(0), 0x0606700c }, |
| { DDRC_DRAMTMG9(0), 0x0002040c }, |
| { DDRC_DRAMTMG10(0), 0x000f0c07 }, |
| { DDRC_DRAMTMG11(0), 0x1809011d }, |
| { DDRC_DRAMTMG12(0), 0x0000000d }, |
| { DDRC_DRAMTMG13(0), 0x2b000000 }, |
| { DDRC_DRAMTMG14(0), 0x000000a4 }, |
| { DDRC_DRAMTMG15(0), 0x00000000 }, |
| { DDRC_DRAMTMG17(0), 0x00250078 }, |
| { DDRC_ZQCTL0(0), 0x51000040 }, |
| { DDRC_ZQCTL1(0), 0x00000070 }, |
| { DDRC_ZQCTL2(0), 0x00000000 }, |
| { DDRC_DFITMG0(0), 0x038b820b }, |
| { DDRC_DFITMG1(0), 0x02020103 }, |
| { DDRC_DFILPCFG0(0), 0x07f04011 }, |
| { DDRC_DFILPCFG1(0), 0x000000b0 }, |
| { DDRC_DFIUPD0(0), 0xe0400018 }, |
| { DDRC_DFIUPD1(0), 0x0048005a }, |
| { DDRC_DFIUPD2(0), 0x80000000 }, |
| { DDRC_DFIMISC(0), 0x00000001 }, |
| { DDRC_DFITMG2(0), 0x00000b0b }, |
| { DDRC_DFITMG3(0), 0x00000001 }, |
| { DDRC_DBICTL(0), 0x00000000 }, |
| { DDRC_DFIPHYMSTR(0), 0x00000000 }, |
| |
| /* MT40A512M16 addr map */ |
| { DDRC_ADDRMAP0(0), 0x0000001F }, |
| { DDRC_ADDRMAP1(0), 0x003F0909 }, |
| { DDRC_ADDRMAP2(0), 0x01010100 }, |
| { DDRC_ADDRMAP3(0), 0x01010101 }, |
| { DDRC_ADDRMAP4(0), 0x00001f1f }, |
| { DDRC_ADDRMAP5(0), 0x07070707 }, |
| { DDRC_ADDRMAP6(0), 0x07070707 }, |
| { DDRC_ADDRMAP7(0), 0x00000f0f }, |
| { DDRC_ADDRMAP8(0), 0x00003F01 }, |
| { DDRC_ADDRMAP9(0), 0x0a020b06 }, |
| { DDRC_ADDRMAP10(0), 0x0a0a0a0a }, |
| { DDRC_ADDRMAP11(0), 0x00000000 }, |
| |
| { DDRC_ODTCFG(0), 0x07000600 }, |
| { DDRC_ODTMAP(0), 0x0001 }, |
| |
| /* P1 400mts */ |
| { DDRC_FREQ1_RFSHCTL0(0), 0x0021a0c0 }, |
| { DDRC_FREQ1_RFSHTMG(0), 0x0018001a }, |
| { DDRC_FREQ1_INIT3(0), (0x204 << 16) | 0x104 }, |
| { DDRC_FREQ1_INIT4(0), (0x1000 << 16) }, |
| { DDRC_FREQ1_INIT6(0), (0x200 << 16) | 0x200 }, |
| { DDRC_FREQ1_INIT7(0), 0x14 }, |
| { DDRC_FREQ1_DRAMTMG0(0), 0x0c0e0604 }, /* t_ras_max=9*7.8us, t_ras_min=35ns */ |
| { DDRC_FREQ1_DRAMTMG1(0), 0x00030314 }, |
| { DDRC_FREQ1_DRAMTMG2(0), 0x0505040a }, |
| { DDRC_FREQ1_DRAMTMG3(0), 0x0000400c }, |
| { DDRC_FREQ1_DRAMTMG4(0), 0x06040307 }, |
| { DDRC_FREQ1_DRAMTMG5(0), 0x090d0202 }, |
| { DDRC_FREQ1_DRAMTMG6(0), 0x0a070008 }, |
| { DDRC_FREQ1_DRAMTMG7(0), 0x00000d09 }, |
| { DDRC_FREQ1_DRAMTMG8(0), 0x08084b09 }, |
| { DDRC_FREQ1_DRAMTMG9(0), 0x00020308 }, |
| { DDRC_FREQ1_DRAMTMG10(0), 0x000f0d06 }, |
| { DDRC_FREQ1_DRAMTMG11(0), 0x12060111 }, |
| { DDRC_FREQ1_DRAMTMG12(0), 0x00000008 }, |
| { DDRC_FREQ1_DRAMTMG13(0), 0x21000000 }, |
| { DDRC_FREQ1_DRAMTMG14(0), 0x00000000 }, |
| { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, |
| { DDRC_FREQ1_DRAMTMG17(0), 0x00c6007d }, |
| { DDRC_FREQ1_ZQCTL0(0), 0x51000040 }, |
| { DDRC_FREQ1_DFITMG0(0), 0x03858204 }, |
| { DDRC_FREQ1_DFITMG1(0), 0x00020103 }, |
| { DDRC_FREQ1_DFITMG2(0), 0x00000504 }, |
| { DDRC_FREQ1_DFITMG3(0), 0x00000001 }, |
| { DDRC_FREQ1_ODTCFG(0), 0x07000601 }, |
| |
| /* p2 100mts */ |
| { DDRC_FREQ2_RFSHCTL0(0), 0x0021a0c0 }, |
| { DDRC_FREQ2_RFSHTMG(0), 0x0006000e }, /* tREFI=7.8us */ |
| { DDRC_FREQ2_INIT3(0), (0x204 << 16) | 0x104 }, |
| { DDRC_FREQ2_INIT4(0), (0x1000 << 16) }, |
| { DDRC_FREQ2_INIT6(0), (0x200 << 16) | 0x200 }, |
| { DDRC_FREQ2_INIT7(0), 0x14 }, |
| { DDRC_FREQ2_DRAMTMG0(0), 0x0c0e0101 }, /* t_ras_max=9*7.8us, t_ras_min=35ns */ |
| { DDRC_FREQ2_DRAMTMG1(0), 0x00030314 }, |
| { DDRC_FREQ2_DRAMTMG2(0), 0x0505040a }, |
| { DDRC_FREQ2_DRAMTMG3(0), 0x0000400c }, |
| { DDRC_FREQ2_DRAMTMG4(0), 0x06040307 }, /* tRP=6 --> 7 */ |
| { DDRC_FREQ2_DRAMTMG5(0), 0x090d0202 }, |
| { DDRC_FREQ2_DRAMTMG6(0), 0x0a070008 }, |
| { DDRC_FREQ2_DRAMTMG7(0), 0x00000d09 }, |
| { DDRC_FREQ2_DRAMTMG8(0), 0x08084b09 }, |
| { DDRC_FREQ2_DRAMTMG9(0), 0x00020308 }, |
| { DDRC_FREQ2_DRAMTMG10(0), 0x000f0d06 }, |
| { DDRC_FREQ2_DRAMTMG11(0), 0x12060111 }, |
| { DDRC_FREQ2_DRAMTMG12(0), 0x00000008 }, |
| { DDRC_FREQ2_DRAMTMG13(0), 0x21000000 }, |
| { DDRC_FREQ2_DRAMTMG14(0), 0x00000000 }, |
| { DDRC_FREQ2_DRAMTMG15(0), 0x00000000 }, |
| { DDRC_FREQ2_DRAMTMG17(0), 0x00c6007d }, |
| { DDRC_FREQ2_ZQCTL0(0), 0x51000040 }, |
| { DDRC_FREQ2_DFITMG0(0), 0x03858204 }, |
| { DDRC_FREQ2_DFITMG1(0), 0x00020103 }, |
| { DDRC_FREQ2_DFITMG2(0), 0x00000504 }, |
| { DDRC_FREQ2_DFITMG3(0), 0x00000001 }, |
| { DDRC_FREQ2_ODTCFG(0), 0x07000601 }, |
| }; |
| |
| /* PHY Initialize Configuration */ |
| struct dram_cfg_param ddr4_ddrphy_cfg[] = { |
| { 0x1005f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 */ |
| { 0x1015f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 */ |
| { 0x1105f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 */ |
| { 0x1115f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 */ |
| { 0x1205f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 */ |
| { 0x1215f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 */ |
| { 0x1305f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 */ |
| { 0x1315f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 */ |
| |
| { 0x11005f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p1 */ |
| { 0x11015f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p1 */ |
| { 0x11105f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p1 */ |
| { 0x11115f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p1 */ |
| { 0x11205f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p1 */ |
| { 0x11215f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p1 */ |
| { 0x11305f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p1 */ |
| { 0x11315f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p1 */ |
| |
| { 0x21005f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p2 */ |
| { 0x21015f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p2 */ |
| { 0x21105f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p2 */ |
| { 0x21115f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p2 */ |
| { 0x21205f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p2 */ |
| { 0x21215f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p2 */ |
| { 0x21305f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p2 */ |
| { 0x21315f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p2 */ |
| |
| { 0x55, 0x355 }, /* DWC_DDRPHYA_ANIB0_ATxSlewRate */ |
| { 0x1055, 0x355 }, /* DWC_DDRPHYA_ANIB1_ATxSlewRate */ |
| { 0x2055, 0x355 }, /* DWC_DDRPHYA_ANIB2_ATxSlewRate */ |
| { 0x3055, 0x355 }, /* DWC_DDRPHYA_ANIB3_ATxSlewRate */ |
| { 0x4055, 0x55 }, /* DWC_DDRPHYA_ANIB4_ATxSlewRate */ |
| { 0x5055, 0x55 }, /* DWC_DDRPHYA_ANIB5_ATxSlewRate */ |
| { 0x6055, 0x355 }, /* DWC_DDRPHYA_ANIB6_ATxSlewRate */ |
| { 0x7055, 0x355 }, /* DWC_DDRPHYA_ANIB7_ATxSlewRate */ |
| { 0x8055, 0x355 }, /* DWC_DDRPHYA_ANIB8_ATxSlewRate */ |
| { 0x9055, 0x355 }, /* DWC_DDRPHYA_ANIB9_ATxSlewRate */ |
| |
| { 0x200c5, 0xa }, /* DWC_DDRPHYA_MASTER0_PllCtrl2_p0 */ |
| { 0x1200c5, 0x7 }, /* DWC_DDRPHYA_MASTER0_PllCtrl2_p1 */ |
| { 0x2200c5, 0x7 }, /* DWC_DDRPHYA_MASTER0_PllCtrl2_p2 */ |
| |
| { 0x2002e, 0x2 }, /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 */ |
| { 0x12002e, 0x2 }, /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p1 */ |
| { 0x22002e, 0x2 }, /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p2 */ |
| |
| { 0x20024, 0x8 }, /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 */ |
| { 0x2003a, 0x2 }, /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ |
| |
| { 0x120024, 0x8 }, /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p1 */ |
| { 0x2003a, 0x2 }, /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ |
| |
| { 0x220024, 0x8 }, /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p2 */ |
| { 0x2003a, 0x2 }, /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ |
| |
| { 0x20056, 0x6 },/* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 */ |
| { 0x120056, 0xa }, /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p1 */ |
| { 0x220056, 0xa }, /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p2 */ |
| |
| { 0x1004d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 */ |
| { 0x1014d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 */ |
| { 0x1104d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 */ |
| { 0x1114d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 */ |
| { 0x1204d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 */ |
| { 0x1214d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 */ |
| { 0x1304d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 */ |
| { 0x1314d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 */ |
| |
| { 0x11004d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p1 */ |
| { 0x11014d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p1 */ |
| { 0x11104d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p1 */ |
| { 0x11114d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p1 */ |
| { 0x11204d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p1 */ |
| { 0x11214d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p1 */ |
| { 0x11304d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p1 */ |
| { 0x11314d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p1 */ |
| |
| { 0x21004d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p2 */ |
| { 0x21014d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p2 */ |
| { 0x21104d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p2 */ |
| { 0x21114d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p2 */ |
| { 0x21204d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p2 */ |
| { 0x21214d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p2 */ |
| { 0x21304d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p2 */ |
| { 0x21314d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p2 */ |
| |
| { 0x10049, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 */ |
| { 0x10149, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 */ |
| { 0x11049, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 */ |
| { 0x11149, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 */ |
| { 0x12049, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 */ |
| { 0x12149, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 */ |
| { 0x13049, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 */ |
| { 0x13149, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 */ |
| |
| { 0x110049, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p1 */ |
| { 0x110149, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p1 */ |
| { 0x111049, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p1 */ |
| { 0x111149, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p1 */ |
| { 0x112049, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p1 */ |
| { 0x112149, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p1 */ |
| { 0x113049, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p1 */ |
| { 0x113149, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p1 */ |
| |
| { 0x210049, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p2 */ |
| { 0x210149, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p2 */ |
| { 0x211049, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p2 */ |
| { 0x211149, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p2 */ |
| { 0x212049, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p2 */ |
| { 0x212149, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p2 */ |
| { 0x213049, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p2 */ |
| { 0x213149, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p2 */ |
| |
| { 0x43, 0x63 }, /* DWC_DDRPHYA_ANIB0_ATxImpedance */ |
| { 0x1043, 0x63 }, /* DWC_DDRPHYA_ANIB1_ATxImpedance */ |
| { 0x2043, 0x63 }, /* DWC_DDRPHYA_ANIB2_ATxImpedance */ |
| { 0x3043, 0x63 }, /* DWC_DDRPHYA_ANIB3_ATxImpedance */ |
| { 0x4043, 0x63 }, /* DWC_DDRPHYA_ANIB4_ATxImpedance */ |
| { 0x5043, 0x63 }, /* DWC_DDRPHYA_ANIB5_ATxImpedance */ |
| { 0x6043, 0x63 }, /* DWC_DDRPHYA_ANIB6_ATxImpedance */ |
| { 0x7043, 0x63 }, /* DWC_DDRPHYA_ANIB7_ATxImpedance */ |
| { 0x8043, 0x63 }, /* DWC_DDRPHYA_ANIB8_ATxImpedance */ |
| { 0x9043, 0x63 }, /* DWC_DDRPHYA_ANIB9_ATxImpedance */ |
| |
| { 0x20018, 0x5 }, /* DWC_DDRPHYA_MASTER0_DfiMode */ |
| { 0x20075, 0x2 }, /* DWC_DDRPHYA_MASTER0_DfiCAMode */ |
| { 0x20050, 0x0 }, /* DWC_DDRPHYA_MASTER0_CalDrvStr0 */ |
| { 0x20008, 0x258 }, /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 */ |
| { 0x120008, 0x64 }, /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p1 */ |
| { 0x220008, 0x19 }, /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p2 */ |
| { 0x20088, 0x9 }, /* DWC_DDRPHYA_MASTER0_CalRate */ |
| |
| { 0x200b2, 0x268 }, /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 */ |
| { 0x10043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 */ |
| { 0x10143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 */ |
| { 0x11043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 */ |
| { 0x11143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 */ |
| { 0x12043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 */ |
| { 0x12143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 */ |
| { 0x13043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 */ |
| { 0x13143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 */ |
| |
| { 0x1200b2, 0x268 }, /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p1 */ |
| { 0x110043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p1 */ |
| { 0x110143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p1 */ |
| { 0x111043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p1 */ |
| { 0x111143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p1 */ |
| { 0x112043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p1 */ |
| { 0x112143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p1 */ |
| { 0x113043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p1 */ |
| { 0x113143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p1 */ |
| |
| { 0x2200b2, 0x268 }, /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p2 */ |
| { 0x210043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p2 */ |
| { 0x210143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p2 */ |
| { 0x211043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p2 */ |
| { 0x211143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p2 */ |
| { 0x212043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p2 */ |
| { 0x212143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p2 */ |
| { 0x213043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p2 */ |
| { 0x213143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p2 */ |
| |
| { 0x2005b, 0x7529 }, /* DWC_DDRPHYA_MASTER0_MemAlertControl */ |
| { 0x2005c, 0x0 }, /* DWC_DDRPHYA_MASTER0_MemAlertControl2 */ |
| { 0x200fa, 0x1 }, /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 */ |
| { 0x1200fa, 0x1 }, /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p1 */ |
| { 0x2200fa, 0x1 }, /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p2 */ |
| { 0x20019, 0x5 }, /* DWC_DDRPHYA_MASTER0_TristateModeCA_p0 */ |
| { 0x120019, 0x5 }, /* DWC_DDRPHYA_MASTER0_TristateModeCA_p1 */ |
| { 0x220019, 0x5 }, /* DWC_DDRPHYA_MASTER0_TristateModeCA_p2 */ |
| |
| { 0x200f0, 0x5665 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */ |
| { 0x200f1, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat1 */ |
| { 0x200f2, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat2 */ |
| { 0x200f3, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat3 */ |
| { 0x200f4, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat4 */ |
| { 0x200f5, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat5 */ |
| { 0x200f6, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat6 */ |
| { 0x200f7, 0xf000 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat7 */ |
| { 0x20025, 0x0 }, /* DWC_DDRPHYA_MASTER0_MasterX4Config */ |
| { 0x2002d, 0x0 }, /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p0 */ |
| { 0x12002d, 0x0 }, /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p1 */ |
| { 0x22002d, 0x0 }, /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p2 */ |
| { 0x200c7, 0x21 }, /* DWC_DDRPHYA_MASTER0_PllCtrl1_p0 */ |
| { 0x200ca, 0x24 }, /* DWC_DDRPHYA_MASTER0_PllTestMode_p0 */ |
| }; |
| |
| /* ddr phy trained csr */ |
| struct dram_cfg_param ddr4_ddrphy_trained_csr[] = { |
| { 0x200b2, 0x0 }, |
| { 0x1200b2, 0x0 }, |
| { 0x2200b2, 0x0 }, |
| { 0x200cb, 0x0 }, |
| { 0x10043, 0x0 }, |
| { 0x110043, 0x0 }, |
| { 0x210043, 0x0 }, |
| { 0x10143, 0x0 }, |
| { 0x110143, 0x0 }, |
| { 0x210143, 0x0 }, |
| { 0x11043, 0x0 }, |
| { 0x111043, 0x0 }, |
| { 0x211043, 0x0 }, |
| { 0x11143, 0x0 }, |
| { 0x111143, 0x0 }, |
| { 0x211143, 0x0 }, |
| { 0x12043, 0x0 }, |
| { 0x112043, 0x0 }, |
| { 0x212043, 0x0 }, |
| { 0x12143, 0x0 }, |
| { 0x112143, 0x0 }, |
| { 0x212143, 0x0 }, |
| { 0x13043, 0x0 }, |
| { 0x113043, 0x0 }, |
| { 0x213043, 0x0 }, |
| { 0x13143, 0x0 }, |
| { 0x113143, 0x0 }, |
| { 0x213143, 0x0 }, |
| { 0x80, 0x0 }, |
| { 0x100080, 0x0 }, |
| { 0x200080, 0x0 }, |
| { 0x1080, 0x0 }, |
| { 0x101080, 0x0 }, |
| { 0x201080, 0x0 }, |
| { 0x2080, 0x0 }, |
| { 0x102080, 0x0 }, |
| { 0x202080, 0x0 }, |
| { 0x3080, 0x0 }, |
| { 0x103080, 0x0 }, |
| { 0x203080, 0x0 }, |
| { 0x4080, 0x0 }, |
| { 0x104080, 0x0 }, |
| { 0x204080, 0x0 }, |
| { 0x5080, 0x0 }, |
| { 0x105080, 0x0 }, |
| { 0x205080, 0x0 }, |
| { 0x6080, 0x0 }, |
| { 0x106080, 0x0 }, |
| { 0x206080, 0x0 }, |
| { 0x7080, 0x0 }, |
| { 0x107080, 0x0 }, |
| { 0x207080, 0x0 }, |
| { 0x8080, 0x0 }, |
| { 0x108080, 0x0 }, |
| { 0x208080, 0x0 }, |
| { 0x9080, 0x0 }, |
| { 0x109080, 0x0 }, |
| { 0x209080, 0x0 }, |
| { 0x10080, 0x0 }, |
| { 0x110080, 0x0 }, |
| { 0x210080, 0x0 }, |
| { 0x10180, 0x0 }, |
| { 0x110180, 0x0 }, |
| { 0x210180, 0x0 }, |
| { 0x11080, 0x0 }, |
| { 0x111080, 0x0 }, |
| { 0x211080, 0x0 }, |
| { 0x11180, 0x0 }, |
| { 0x111180, 0x0 }, |
| { 0x211180, 0x0 }, |
| { 0x12080, 0x0 }, |
| { 0x112080, 0x0 }, |
| { 0x212080, 0x0 }, |
| { 0x12180, 0x0 }, |
| { 0x112180, 0x0 }, |
| { 0x212180, 0x0 }, |
| { 0x13080, 0x0 }, |
| { 0x113080, 0x0 }, |
| { 0x213080, 0x0 }, |
| { 0x13180, 0x0 }, |
| { 0x113180, 0x0 }, |
| { 0x213180, 0x0 }, |
| { 0x10081, 0x0 }, |
| { 0x110081, 0x0 }, |
| { 0x210081, 0x0 }, |
| { 0x10181, 0x0 }, |
| { 0x110181, 0x0 }, |
| { 0x210181, 0x0 }, |
| { 0x11081, 0x0 }, |
| { 0x111081, 0x0 }, |
| { 0x211081, 0x0 }, |
| { 0x11181, 0x0 }, |
| { 0x111181, 0x0 }, |
| { 0x211181, 0x0 }, |
| { 0x12081, 0x0 }, |
| { 0x112081, 0x0 }, |
| { 0x212081, 0x0 }, |
| { 0x12181, 0x0 }, |
| { 0x112181, 0x0 }, |
| { 0x212181, 0x0 }, |
| { 0x13081, 0x0 }, |
| { 0x113081, 0x0 }, |
| { 0x213081, 0x0 }, |
| { 0x13181, 0x0 }, |
| { 0x113181, 0x0 }, |
| { 0x213181, 0x0 }, |
| { 0x100d0, 0x0 }, |
| { 0x1100d0, 0x0 }, |
| { 0x2100d0, 0x0 }, |
| { 0x101d0, 0x0 }, |
| { 0x1101d0, 0x0 }, |
| { 0x2101d0, 0x0 }, |
| { 0x110d0, 0x0 }, |
| { 0x1110d0, 0x0 }, |
| { 0x2110d0, 0x0 }, |
| { 0x111d0, 0x0 }, |
| { 0x1111d0, 0x0 }, |
| { 0x2111d0, 0x0 }, |
| { 0x120d0, 0x0 }, |
| { 0x1120d0, 0x0 }, |
| { 0x2120d0, 0x0 }, |
| { 0x121d0, 0x0 }, |
| { 0x1121d0, 0x0 }, |
| { 0x2121d0, 0x0 }, |
| { 0x130d0, 0x0 }, |
| { 0x1130d0, 0x0 }, |
| { 0x2130d0, 0x0 }, |
| { 0x131d0, 0x0 }, |
| { 0x1131d0, 0x0 }, |
| { 0x2131d0, 0x0 }, |
| { 0x100d1, 0x0 }, |
| { 0x1100d1, 0x0 }, |
| { 0x2100d1, 0x0 }, |
| { 0x101d1, 0x0 }, |
| { 0x1101d1, 0x0 }, |
| { 0x2101d1, 0x0 }, |
| { 0x110d1, 0x0 }, |
| { 0x1110d1, 0x0 }, |
| { 0x2110d1, 0x0 }, |
| { 0x111d1, 0x0 }, |
| { 0x1111d1, 0x0 }, |
| { 0x2111d1, 0x0 }, |
| { 0x120d1, 0x0 }, |
| { 0x1120d1, 0x0 }, |
| { 0x2120d1, 0x0 }, |
| { 0x121d1, 0x0 }, |
| { 0x1121d1, 0x0 }, |
| { 0x2121d1, 0x0 }, |
| { 0x130d1, 0x0 }, |
| { 0x1130d1, 0x0 }, |
| { 0x2130d1, 0x0 }, |
| { 0x131d1, 0x0 }, |
| { 0x1131d1, 0x0 }, |
| { 0x2131d1, 0x0 }, |
| { 0x10068, 0x0 }, |
| { 0x10168, 0x0 }, |
| { 0x10268, 0x0 }, |
| { 0x10368, 0x0 }, |
| { 0x10468, 0x0 }, |
| { 0x10568, 0x0 }, |
| { 0x10668, 0x0 }, |
| { 0x10768, 0x0 }, |
| { 0x10868, 0x0 }, |
| { 0x11068, 0x0 }, |
| { 0x11168, 0x0 }, |
| { 0x11268, 0x0 }, |
| { 0x11368, 0x0 }, |
| { 0x11468, 0x0 }, |
| { 0x11568, 0x0 }, |
| { 0x11668, 0x0 }, |
| { 0x11768, 0x0 }, |
| { 0x11868, 0x0 }, |
| { 0x12068, 0x0 }, |
| { 0x12168, 0x0 }, |
| { 0x12268, 0x0 }, |
| { 0x12368, 0x0 }, |
| { 0x12468, 0x0 }, |
| { 0x12568, 0x0 }, |
| { 0x12668, 0x0 }, |
| { 0x12768, 0x0 }, |
| { 0x12868, 0x0 }, |
| { 0x13068, 0x0 }, |
| { 0x13168, 0x0 }, |
| { 0x13268, 0x0 }, |
| { 0x13368, 0x0 }, |
| { 0x13468, 0x0 }, |
| { 0x13568, 0x0 }, |
| { 0x13668, 0x0 }, |
| { 0x13768, 0x0 }, |
| { 0x13868, 0x0 }, |
| { 0x10069, 0x0 }, |
| { 0x10169, 0x0 }, |
| { 0x10269, 0x0 }, |
| { 0x10369, 0x0 }, |
| { 0x10469, 0x0 }, |
| { 0x10569, 0x0 }, |
| { 0x10669, 0x0 }, |
| { 0x10769, 0x0 }, |
| { 0x10869, 0x0 }, |
| { 0x11069, 0x0 }, |
| { 0x11169, 0x0 }, |
| { 0x11269, 0x0 }, |
| { 0x11369, 0x0 }, |
| { 0x11469, 0x0 }, |
| { 0x11569, 0x0 }, |
| { 0x11669, 0x0 }, |
| { 0x11769, 0x0 }, |
| { 0x11869, 0x0 }, |
| { 0x12069, 0x0 }, |
| { 0x12169, 0x0 }, |
| { 0x12269, 0x0 }, |
| { 0x12369, 0x0 }, |
| { 0x12469, 0x0 }, |
| { 0x12569, 0x0 }, |
| { 0x12669, 0x0 }, |
| { 0x12769, 0x0 }, |
| { 0x12869, 0x0 }, |
| { 0x13069, 0x0 }, |
| { 0x13169, 0x0 }, |
| { 0x13269, 0x0 }, |
| { 0x13369, 0x0 }, |
| { 0x13469, 0x0 }, |
| { 0x13569, 0x0 }, |
| { 0x13669, 0x0 }, |
| { 0x13769, 0x0 }, |
| { 0x13869, 0x0 }, |
| { 0x1008c, 0x0 }, |
| { 0x11008c, 0x0 }, |
| { 0x21008c, 0x0 }, |
| { 0x1018c, 0x0 }, |
| { 0x11018c, 0x0 }, |
| { 0x21018c, 0x0 }, |
| { 0x1108c, 0x0 }, |
| { 0x11108c, 0x0 }, |
| { 0x21108c, 0x0 }, |
| { 0x1118c, 0x0 }, |
| { 0x11118c, 0x0 }, |
| { 0x21118c, 0x0 }, |
| { 0x1208c, 0x0 }, |
| { 0x11208c, 0x0 }, |
| { 0x21208c, 0x0 }, |
| { 0x1218c, 0x0 }, |
| { 0x11218c, 0x0 }, |
| { 0x21218c, 0x0 }, |
| { 0x1308c, 0x0 }, |
| { 0x11308c, 0x0 }, |
| { 0x21308c, 0x0 }, |
| { 0x1318c, 0x0 }, |
| { 0x11318c, 0x0 }, |
| { 0x21318c, 0x0 }, |
| { 0x1008d, 0x0 }, |
| { 0x11008d, 0x0 }, |
| { 0x21008d, 0x0 }, |
| { 0x1018d, 0x0 }, |
| { 0x11018d, 0x0 }, |
| { 0x21018d, 0x0 }, |
| { 0x1108d, 0x0 }, |
| { 0x11108d, 0x0 }, |
| { 0x21108d, 0x0 }, |
| { 0x1118d, 0x0 }, |
| { 0x11118d, 0x0 }, |
| { 0x21118d, 0x0 }, |
| { 0x1208d, 0x0 }, |
| { 0x11208d, 0x0 }, |
| { 0x21208d, 0x0 }, |
| { 0x1218d, 0x0 }, |
| { 0x11218d, 0x0 }, |
| { 0x21218d, 0x0 }, |
| { 0x1308d, 0x0 }, |
| { 0x11308d, 0x0 }, |
| { 0x21308d, 0x0 }, |
| { 0x1318d, 0x0 }, |
| { 0x11318d, 0x0 }, |
| { 0x21318d, 0x0 }, |
| { 0x100c0, 0x0 }, |
| { 0x1100c0, 0x0 }, |
| { 0x2100c0, 0x0 }, |
| { 0x101c0, 0x0 }, |
| { 0x1101c0, 0x0 }, |
| { 0x2101c0, 0x0 }, |
| { 0x102c0, 0x0 }, |
| { 0x1102c0, 0x0 }, |
| { 0x2102c0, 0x0 }, |
| { 0x103c0, 0x0 }, |
| { 0x1103c0, 0x0 }, |
| { 0x2103c0, 0x0 }, |
| { 0x104c0, 0x0 }, |
| { 0x1104c0, 0x0 }, |
| { 0x2104c0, 0x0 }, |
| { 0x105c0, 0x0 }, |
| { 0x1105c0, 0x0 }, |
| { 0x2105c0, 0x0 }, |
| { 0x106c0, 0x0 }, |
| { 0x1106c0, 0x0 }, |
| { 0x2106c0, 0x0 }, |
| { 0x107c0, 0x0 }, |
| { 0x1107c0, 0x0 }, |
| { 0x2107c0, 0x0 }, |
| { 0x108c0, 0x0 }, |
| { 0x1108c0, 0x0 }, |
| { 0x2108c0, 0x0 }, |
| { 0x110c0, 0x0 }, |
| { 0x1110c0, 0x0 }, |
| { 0x2110c0, 0x0 }, |
| { 0x111c0, 0x0 }, |
| { 0x1111c0, 0x0 }, |
| { 0x2111c0, 0x0 }, |
| { 0x112c0, 0x0 }, |
| { 0x1112c0, 0x0 }, |
| { 0x2112c0, 0x0 }, |
| { 0x113c0, 0x0 }, |
| { 0x1113c0, 0x0 }, |
| { 0x2113c0, 0x0 }, |
| { 0x114c0, 0x0 }, |
| { 0x1114c0, 0x0 }, |
| { 0x2114c0, 0x0 }, |
| { 0x115c0, 0x0 }, |
| { 0x1115c0, 0x0 }, |
| { 0x2115c0, 0x0 }, |
| { 0x116c0, 0x0 }, |
| { 0x1116c0, 0x0 }, |
| { 0x2116c0, 0x0 }, |
| { 0x117c0, 0x0 }, |
| { 0x1117c0, 0x0 }, |
| { 0x2117c0, 0x0 }, |
| { 0x118c0, 0x0 }, |
| { 0x1118c0, 0x0 }, |
| { 0x2118c0, 0x0 }, |
| { 0x120c0, 0x0 }, |
| { 0x1120c0, 0x0 }, |
| { 0x2120c0, 0x0 }, |
| { 0x121c0, 0x0 }, |
| { 0x1121c0, 0x0 }, |
| { 0x2121c0, 0x0 }, |
| { 0x122c0, 0x0 }, |
| { 0x1122c0, 0x0 }, |
| { 0x2122c0, 0x0 }, |
| { 0x123c0, 0x0 }, |
| { 0x1123c0, 0x0 }, |
| { 0x2123c0, 0x0 }, |
| { 0x124c0, 0x0 }, |
| { 0x1124c0, 0x0 }, |
| { 0x2124c0, 0x0 }, |
| { 0x125c0, 0x0 }, |
| { 0x1125c0, 0x0 }, |
| { 0x2125c0, 0x0 }, |
| { 0x126c0, 0x0 }, |
| { 0x1126c0, 0x0 }, |
| { 0x2126c0, 0x0 }, |
| { 0x127c0, 0x0 }, |
| { 0x1127c0, 0x0 }, |
| { 0x2127c0, 0x0 }, |
| { 0x128c0, 0x0 }, |
| { 0x1128c0, 0x0 }, |
| { 0x2128c0, 0x0 }, |
| { 0x130c0, 0x0 }, |
| { 0x1130c0, 0x0 }, |
| { 0x2130c0, 0x0 }, |
| { 0x131c0, 0x0 }, |
| { 0x1131c0, 0x0 }, |
| { 0x2131c0, 0x0 }, |
| { 0x132c0, 0x0 }, |
| { 0x1132c0, 0x0 }, |
| { 0x2132c0, 0x0 }, |
| { 0x133c0, 0x0 }, |
| { 0x1133c0, 0x0 }, |
| { 0x2133c0, 0x0 }, |
| { 0x134c0, 0x0 }, |
| { 0x1134c0, 0x0 }, |
| { 0x2134c0, 0x0 }, |
| { 0x135c0, 0x0 }, |
| { 0x1135c0, 0x0 }, |
| { 0x2135c0, 0x0 }, |
| { 0x136c0, 0x0 }, |
| { 0x1136c0, 0x0 }, |
| { 0x2136c0, 0x0 }, |
| { 0x137c0, 0x0 }, |
| { 0x1137c0, 0x0 }, |
| { 0x2137c0, 0x0 }, |
| { 0x138c0, 0x0 }, |
| { 0x1138c0, 0x0 }, |
| { 0x2138c0, 0x0 }, |
| { 0x100c1, 0x0 }, |
| { 0x1100c1, 0x0 }, |
| { 0x2100c1, 0x0 }, |
| { 0x101c1, 0x0 }, |
| { 0x1101c1, 0x0 }, |
| { 0x2101c1, 0x0 }, |
| { 0x102c1, 0x0 }, |
| { 0x1102c1, 0x0 }, |
| { 0x2102c1, 0x0 }, |
| { 0x103c1, 0x0 }, |
| { 0x1103c1, 0x0 }, |
| { 0x2103c1, 0x0 }, |
| { 0x104c1, 0x0 }, |
| { 0x1104c1, 0x0 }, |
| { 0x2104c1, 0x0 }, |
| { 0x105c1, 0x0 }, |
| { 0x1105c1, 0x0 }, |
| { 0x2105c1, 0x0 }, |
| { 0x106c1, 0x0 }, |
| { 0x1106c1, 0x0 }, |
| { 0x2106c1, 0x0 }, |
| { 0x107c1, 0x0 }, |
| { 0x1107c1, 0x0 }, |
| { 0x2107c1, 0x0 }, |
| { 0x108c1, 0x0 }, |
| { 0x1108c1, 0x0 }, |
| { 0x2108c1, 0x0 }, |
| { 0x110c1, 0x0 }, |
| { 0x1110c1, 0x0 }, |
| { 0x2110c1, 0x0 }, |
| { 0x111c1, 0x0 }, |
| { 0x1111c1, 0x0 }, |
| { 0x2111c1, 0x0 }, |
| { 0x112c1, 0x0 }, |
| { 0x1112c1, 0x0 }, |
| { 0x2112c1, 0x0 }, |
| { 0x113c1, 0x0 }, |
| { 0x1113c1, 0x0 }, |
| { 0x2113c1, 0x0 }, |
| { 0x114c1, 0x0 }, |
| { 0x1114c1, 0x0 }, |
| { 0x2114c1, 0x0 }, |
| { 0x115c1, 0x0 }, |
| { 0x1115c1, 0x0 }, |
| { 0x2115c1, 0x0 }, |
| { 0x116c1, 0x0 }, |
| { 0x1116c1, 0x0 }, |
| { 0x2116c1, 0x0 }, |
| { 0x117c1, 0x0 }, |
| { 0x1117c1, 0x0 }, |
| { 0x2117c1, 0x0 }, |
| { 0x118c1, 0x0 }, |
| { 0x1118c1, 0x0 }, |
| { 0x2118c1, 0x0 }, |
| { 0x120c1, 0x0 }, |
| { 0x1120c1, 0x0 }, |
| { 0x2120c1, 0x0 }, |
| { 0x121c1, 0x0 }, |
| { 0x1121c1, 0x0 }, |
| { 0x2121c1, 0x0 }, |
| { 0x122c1, 0x0 }, |
| { 0x1122c1, 0x0 }, |
| { 0x2122c1, 0x0 }, |
| { 0x123c1, 0x0 }, |
| { 0x1123c1, 0x0 }, |
| { 0x2123c1, 0x0 }, |
| { 0x124c1, 0x0 }, |
| { 0x1124c1, 0x0 }, |
| { 0x2124c1, 0x0 }, |
| { 0x125c1, 0x0 }, |
| { 0x1125c1, 0x0 }, |
| { 0x2125c1, 0x0 }, |
| { 0x126c1, 0x0 }, |
| { 0x1126c1, 0x0 }, |
| { 0x2126c1, 0x0 }, |
| { 0x127c1, 0x0 }, |
| { 0x1127c1, 0x0 }, |
| { 0x2127c1, 0x0 }, |
| { 0x128c1, 0x0 }, |
| { 0x1128c1, 0x0 }, |
| { 0x2128c1, 0x0 }, |
| { 0x130c1, 0x0 }, |
| { 0x1130c1, 0x0 }, |
| { 0x2130c1, 0x0 }, |
| { 0x131c1, 0x0 }, |
| { 0x1131c1, 0x0 }, |
| { 0x2131c1, 0x0 }, |
| { 0x132c1, 0x0 }, |
| { 0x1132c1, 0x0 }, |
| { 0x2132c1, 0x0 }, |
| { 0x133c1, 0x0 }, |
| { 0x1133c1, 0x0 }, |
| { 0x2133c1, 0x0 }, |
| { 0x134c1, 0x0 }, |
| { 0x1134c1, 0x0 }, |
| { 0x2134c1, 0x0 }, |
| { 0x135c1, 0x0 }, |
| { 0x1135c1, 0x0 }, |
| { 0x2135c1, 0x0 }, |
| { 0x136c1, 0x0 }, |
| { 0x1136c1, 0x0 }, |
| { 0x2136c1, 0x0 }, |
| { 0x137c1, 0x0 }, |
| { 0x1137c1, 0x0 }, |
| { 0x2137c1, 0x0 }, |
| { 0x138c1, 0x0 }, |
| { 0x1138c1, 0x0 }, |
| { 0x2138c1, 0x0 }, |
| { 0x10020, 0x0 }, |
| { 0x110020, 0x0 }, |
| { 0x210020, 0x0 }, |
| { 0x11020, 0x0 }, |
| { 0x111020, 0x0 }, |
| { 0x211020, 0x0 }, |
| { 0x12020, 0x0 }, |
| { 0x112020, 0x0 }, |
| { 0x212020, 0x0 }, |
| { 0x13020, 0x0 }, |
| { 0x113020, 0x0 }, |
| { 0x213020, 0x0 }, |
| { 0x20072, 0x0 }, |
| { 0x20073, 0x0 }, |
| { 0x20074, 0x0 }, |
| { 0x100aa, 0x0 }, |
| { 0x110aa, 0x0 }, |
| { 0x120aa, 0x0 }, |
| { 0x130aa, 0x0 }, |
| { 0x20010, 0x0 }, |
| { 0x120010, 0x0 }, |
| { 0x220010, 0x0 }, |
| { 0x20011, 0x0 }, |
| { 0x120011, 0x0 }, |
| { 0x220011, 0x0 }, |
| { 0x100ae, 0x0 }, |
| { 0x1100ae, 0x0 }, |
| { 0x2100ae, 0x0 }, |
| { 0x100af, 0x0 }, |
| { 0x1100af, 0x0 }, |
| { 0x2100af, 0x0 }, |
| { 0x110ae, 0x0 }, |
| { 0x1110ae, 0x0 }, |
| { 0x2110ae, 0x0 }, |
| { 0x110af, 0x0 }, |
| { 0x1110af, 0x0 }, |
| { 0x2110af, 0x0 }, |
| { 0x120ae, 0x0 }, |
| { 0x1120ae, 0x0 }, |
| { 0x2120ae, 0x0 }, |
| { 0x120af, 0x0 }, |
| { 0x1120af, 0x0 }, |
| { 0x2120af, 0x0 }, |
| { 0x130ae, 0x0 }, |
| { 0x1130ae, 0x0 }, |
| { 0x2130ae, 0x0 }, |
| { 0x130af, 0x0 }, |
| { 0x1130af, 0x0 }, |
| { 0x2130af, 0x0 }, |
| { 0x20020, 0x0 }, |
| { 0x120020, 0x0 }, |
| { 0x220020, 0x0 }, |
| { 0x100a0, 0x0 }, |
| { 0x100a1, 0x0 }, |
| { 0x100a2, 0x0 }, |
| { 0x100a3, 0x0 }, |
| { 0x100a4, 0x0 }, |
| { 0x100a5, 0x0 }, |
| { 0x100a6, 0x0 }, |
| { 0x100a7, 0x0 }, |
| { 0x110a0, 0x0 }, |
| { 0x110a1, 0x0 }, |
| { 0x110a2, 0x0 }, |
| { 0x110a3, 0x0 }, |
| { 0x110a4, 0x0 }, |
| { 0x110a5, 0x0 }, |
| { 0x110a6, 0x0 }, |
| { 0x110a7, 0x0 }, |
| { 0x120a0, 0x0 }, |
| { 0x120a1, 0x0 }, |
| { 0x120a2, 0x0 }, |
| { 0x120a3, 0x0 }, |
| { 0x120a4, 0x0 }, |
| { 0x120a5, 0x0 }, |
| { 0x120a6, 0x0 }, |
| { 0x120a7, 0x0 }, |
| { 0x130a0, 0x0 }, |
| { 0x130a1, 0x0 }, |
| { 0x130a2, 0x0 }, |
| { 0x130a3, 0x0 }, |
| { 0x130a4, 0x0 }, |
| { 0x130a5, 0x0 }, |
| { 0x130a6, 0x0 }, |
| { 0x130a7, 0x0 }, |
| { 0x2007c, 0x0 }, |
| { 0x12007c, 0x0 }, |
| { 0x22007c, 0x0 }, |
| { 0x2007d, 0x0 }, |
| { 0x12007d, 0x0 }, |
| { 0x22007d, 0x0 }, |
| { 0x400fd, 0x0 }, |
| { 0x400c0, 0x0 }, |
| { 0x90201, 0x0 }, |
| { 0x190201, 0x0 }, |
| { 0x290201, 0x0 }, |
| { 0x90202, 0x0 }, |
| { 0x190202, 0x0 }, |
| { 0x290202, 0x0 }, |
| { 0x90203, 0x0 }, |
| { 0x190203, 0x0 }, |
| { 0x290203, 0x0 }, |
| { 0x90204, 0x0 }, |
| { 0x190204, 0x0 }, |
| { 0x290204, 0x0 }, |
| { 0x90205, 0x0 }, |
| { 0x190205, 0x0 }, |
| { 0x290205, 0x0 }, |
| { 0x90206, 0x0 }, |
| { 0x190206, 0x0 }, |
| { 0x290206, 0x0 }, |
| { 0x90207, 0x0 }, |
| { 0x190207, 0x0 }, |
| { 0x290207, 0x0 }, |
| { 0x90208, 0x0 }, |
| { 0x190208, 0x0 }, |
| { 0x290208, 0x0 }, |
| { 0x10062, 0x0 }, |
| { 0x10162, 0x0 }, |
| { 0x10262, 0x0 }, |
| { 0x10362, 0x0 }, |
| { 0x10462, 0x0 }, |
| { 0x10562, 0x0 }, |
| { 0x10662, 0x0 }, |
| { 0x10762, 0x0 }, |
| { 0x10862, 0x0 }, |
| { 0x11062, 0x0 }, |
| { 0x11162, 0x0 }, |
| { 0x11262, 0x0 }, |
| { 0x11362, 0x0 }, |
| { 0x11462, 0x0 }, |
| { 0x11562, 0x0 }, |
| { 0x11662, 0x0 }, |
| { 0x11762, 0x0 }, |
| { 0x11862, 0x0 }, |
| { 0x12062, 0x0 }, |
| { 0x12162, 0x0 }, |
| { 0x12262, 0x0 }, |
| { 0x12362, 0x0 }, |
| { 0x12462, 0x0 }, |
| { 0x12562, 0x0 }, |
| { 0x12662, 0x0 }, |
| { 0x12762, 0x0 }, |
| { 0x12862, 0x0 }, |
| { 0x13062, 0x0 }, |
| { 0x13162, 0x0 }, |
| { 0x13262, 0x0 }, |
| { 0x13362, 0x0 }, |
| { 0x13462, 0x0 }, |
| { 0x13562, 0x0 }, |
| { 0x13662, 0x0 }, |
| { 0x13762, 0x0 }, |
| { 0x13862, 0x0 }, |
| { 0x20077, 0x0 }, |
| { 0x10001, 0x0 }, |
| { 0x11001, 0x0 }, |
| { 0x12001, 0x0 }, |
| { 0x13001, 0x0 }, |
| { 0x10040, 0x0 }, |
| { 0x10140, 0x0 }, |
| { 0x10240, 0x0 }, |
| { 0x10340, 0x0 }, |
| { 0x10440, 0x0 }, |
| { 0x10540, 0x0 }, |
| { 0x10640, 0x0 }, |
| { 0x10740, 0x0 }, |
| { 0x10840, 0x0 }, |
| { 0x10030, 0x0 }, |
| { 0x10130, 0x0 }, |
| { 0x10230, 0x0 }, |
| { 0x10330, 0x0 }, |
| { 0x10430, 0x0 }, |
| { 0x10530, 0x0 }, |
| { 0x10630, 0x0 }, |
| { 0x10730, 0x0 }, |
| { 0x10830, 0x0 }, |
| { 0x11040, 0x0 }, |
| { 0x11140, 0x0 }, |
| { 0x11240, 0x0 }, |
| { 0x11340, 0x0 }, |
| { 0x11440, 0x0 }, |
| { 0x11540, 0x0 }, |
| { 0x11640, 0x0 }, |
| { 0x11740, 0x0 }, |
| { 0x11840, 0x0 }, |
| { 0x11030, 0x0 }, |
| { 0x11130, 0x0 }, |
| { 0x11230, 0x0 }, |
| { 0x11330, 0x0 }, |
| { 0x11430, 0x0 }, |
| { 0x11530, 0x0 }, |
| { 0x11630, 0x0 }, |
| { 0x11730, 0x0 }, |
| { 0x11830, 0x0 }, |
| { 0x12040, 0x0 }, |
| { 0x12140, 0x0 }, |
| { 0x12240, 0x0 }, |
| { 0x12340, 0x0 }, |
| { 0x12440, 0x0 }, |
| { 0x12540, 0x0 }, |
| { 0x12640, 0x0 }, |
| { 0x12740, 0x0 }, |
| { 0x12840, 0x0 }, |
| { 0x12030, 0x0 }, |
| { 0x12130, 0x0 }, |
| { 0x12230, 0x0 }, |
| { 0x12330, 0x0 }, |
| { 0x12430, 0x0 }, |
| { 0x12530, 0x0 }, |
| { 0x12630, 0x0 }, |
| { 0x12730, 0x0 }, |
| { 0x12830, 0x0 }, |
| { 0x13040, 0x0 }, |
| { 0x13140, 0x0 }, |
| { 0x13240, 0x0 }, |
| { 0x13340, 0x0 }, |
| { 0x13440, 0x0 }, |
| { 0x13540, 0x0 }, |
| { 0x13640, 0x0 }, |
| { 0x13740, 0x0 }, |
| { 0x13840, 0x0 }, |
| { 0x13030, 0x0 }, |
| { 0x13130, 0x0 }, |
| { 0x13230, 0x0 }, |
| { 0x13330, 0x0 }, |
| { 0x13430, 0x0 }, |
| { 0x13530, 0x0 }, |
| { 0x13630, 0x0 }, |
| { 0x13730, 0x0 }, |
| { 0x13830, 0x0 }, |
| }; |
| |
| /* P0 message block paremeter for training firmware */ |
| struct dram_cfg_param ddr4_fsp0_cfg[] = { |
| { 0x20060, 0x2 }, |
| { 0xd0000, 0x0 }, |
| { 0x54000, 0x0 }, |
| { 0x54001, 0x0 }, |
| { 0x54002, 0x0 }, |
| { 0x54003, 0x960 }, |
| { 0x54004, 0x2 }, |
| { 0x54005, 0x0 }, |
| { 0x54006, 0x25e }, |
| { 0x54007, 0x2000 }, |
| { 0x54008, 0x101 }, |
| { 0x54009, 0x0 }, |
| { 0x5400a, 0x0 }, |
| { 0x5400b, 0x31f }, |
| { 0x5400c, 0xc8 }, |
| { 0x5400d, 0x0 }, |
| { 0x5400e, 0x0 }, |
| { 0x5400f, 0x0 }, |
| { 0x54010, 0x0 }, |
| { 0x54011, 0x0 }, |
| { 0x54012, 0x1 }, |
| { 0x5402f, 0xa34 }, |
| { 0x54030, 0x105 }, |
| { 0x54031, 0x1028 }, |
| { 0x54032, 0x200 }, |
| { 0x54033, 0x200 }, |
| { 0x54034, 0x200 }, |
| { 0x54035, 0x814 }, |
| { 0x54036, 0x101 }, |
| { 0x54037, 0x0 }, |
| { 0x54038, 0x0 }, |
| { 0x54039, 0x0 }, |
| { 0x5403a, 0x0 }, |
| { 0x5403b, 0x0 }, |
| { 0x5403c, 0x0 }, |
| { 0x5403d, 0x0 }, |
| { 0x5403e, 0x0 }, |
| { 0x5403f, 0x1221 }, |
| { 0x541fc, 0x100 }, |
| { 0xd0000, 0x1 }, |
| }; |
| |
| /* P1 message block paremeter for training firmware */ |
| struct dram_cfg_param ddr4_fsp1_cfg[] = { |
| { 0xd0000, 0x0 }, |
| { 0x54000, 0x0 }, |
| { 0x54001, 0x0 }, |
| { 0x54002, 0x101 }, |
| { 0x54003, 0x190 }, |
| { 0x54004, 0x2 }, |
| { 0x54005, 0x0 }, |
| { 0x54006, 0x25e }, |
| { 0x54007, 0x2000 }, |
| { 0x54008, 0x101 }, |
| { 0x54009, 0x0 }, |
| { 0x5400a, 0x0 }, |
| { 0x5400b, 0x21f }, |
| { 0x5400c, 0xc8 }, |
| { 0x5400d, 0x0 }, |
| { 0x5400e, 0x0 }, |
| { 0x5400f, 0x0 }, |
| { 0x54010, 0x0 }, |
| { 0x54011, 0x0 }, |
| { 0x54012, 0x1 }, |
| { 0x5402f, 0x204 }, |
| { 0x54030, 0x104 }, |
| { 0x54031, 0x1000 }, |
| { 0x54032, 0x0 }, |
| { 0x54033, 0x200 }, |
| { 0x54034, 0x200 }, |
| { 0x54035, 0x14 }, |
| { 0x54036, 0x101 }, |
| { 0x54037, 0x0 }, |
| { 0x54038, 0x0 }, |
| { 0x54039, 0x0 }, |
| { 0x5403a, 0x0 }, |
| { 0x5403b, 0x0 }, |
| { 0x5403c, 0x0 }, |
| { 0x5403d, 0x0 }, |
| { 0x5403e, 0x0 }, |
| { 0x5403f, 0x1221 }, |
| { 0x541fc, 0x100 }, |
| { 0xd0000, 0x1 }, |
| }; |
| |
| /* P2 message block paremeter for training firmware */ |
| struct dram_cfg_param ddr4_fsp2_cfg[] = { |
| { 0xd0000, 0x0 }, |
| { 0x54000, 0x0 }, |
| { 0x54001, 0x0 }, |
| { 0x54002, 0x102 }, |
| { 0x54003, 0x64 }, |
| { 0x54004, 0x2 }, |
| { 0x54005, 0x0 }, |
| { 0x54006, 0x25e }, |
| { 0x54007, 0x2000 }, |
| { 0x54008, 0x101 }, |
| { 0x54009, 0x0 }, |
| { 0x5400a, 0x0 }, |
| { 0x5400b, 0x21f }, |
| { 0x5400c, 0xc8 }, |
| { 0x5400d, 0x0 }, |
| { 0x5400e, 0x0 }, |
| { 0x5400f, 0x0 }, |
| { 0x54010, 0x0 }, |
| { 0x54011, 0x0 }, |
| { 0x54012, 0x1 }, |
| { 0x5402f, 0x204 }, |
| { 0x54030, 0x104 }, |
| { 0x54031, 0x1000 }, |
| { 0x54032, 0x0 }, |
| { 0x54033, 0x200 }, |
| { 0x54034, 0x200 }, |
| { 0x54035, 0x14 }, |
| { 0x54036, 0x101 }, |
| { 0x54037, 0x0 }, |
| { 0x54038, 0x0 }, |
| { 0x54039, 0x0 }, |
| { 0x5403a, 0x0 }, |
| { 0x5403b, 0x0 }, |
| { 0x5403c, 0x0 }, |
| { 0x5403d, 0x0 }, |
| { 0x5403e, 0x0 }, |
| { 0x5403f, 0x1221 }, |
| { 0x541fc, 0x100 }, |
| { 0xd0000, 0x1 }, |
| |
| }; |
| |
| /* P0 2D message block paremeter for training firmware */ |
| struct dram_cfg_param ddr4_fsp0_2d_cfg[] = { |
| { 0xd0000, 0x0 }, |
| { 0x54000, 0x0 }, |
| { 0x54001, 0x0 }, |
| { 0x54002, 0x0 }, |
| { 0x54003, 0x960 }, |
| { 0x54004, 0x2 }, |
| { 0x54005, 0x0 }, |
| { 0x54006, 0x25e }, |
| { 0x54007, 0x2000 }, |
| { 0x54008, 0x101 }, |
| { 0x54009, 0x0 }, |
| { 0x5400a, 0x0 }, |
| { 0x5400b, 0x61 }, |
| { 0x5400c, 0xc8 }, |
| { 0x5400d, 0x100 }, |
| { 0x5400e, 0x1f7f }, |
| { 0x5400f, 0x0 }, |
| { 0x54010, 0x0 }, |
| { 0x54011, 0x0 }, |
| { 0x54012, 0x1 }, |
| { 0x5402f, 0xa34 }, |
| { 0x54030, 0x105 }, |
| { 0x54031, 0x1028 }, |
| { 0x54032, 0x200 }, |
| { 0x54033, 0x200 }, |
| { 0x54034, 0x200 }, |
| { 0x54035, 0x814 }, |
| { 0x54036, 0x101 }, |
| { 0x54037, 0x0 }, |
| { 0x54038, 0x0 }, |
| { 0x54039, 0x0 }, |
| { 0x5403a, 0x0 }, |
| { 0x5403b, 0x0 }, |
| { 0x5403c, 0x0 }, |
| { 0x5403d, 0x0 }, |
| { 0x5403e, 0x0 }, |
| { 0x5403f, 0x1221 }, |
| { 0x541fc, 0x100 }, |
| { 0xd0000, 0x1 }, |
| }; |
| |
| /* DRAM PHY init engine image */ |
| struct dram_cfg_param ddr4_phy_pie[] = { |
| { 0xd0000, 0x0 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ |
| { 0x90000, 0x10 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */ |
| { 0x90001, 0x400 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */ |
| { 0x90002, 0x10e }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */ |
| { 0x90003, 0x0 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */ |
| { 0x90004, 0x0 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */ |
| { 0x90005, 0x8 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */ |
| { 0x90029, 0xb }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */ |
| { 0x9002a, 0x480 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */ |
| { 0x9002b, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */ |
| { 0x9002c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */ |
| { 0x9002d, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */ |
| { 0x9002e, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */ |
| { 0x9002f, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */ |
| { 0x90030, 0x478 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */ |
| { 0x90031, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */ |
| { 0x90032, 0x2 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */ |
| { 0x90033, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */ |
| { 0x90034, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */ |
| { 0x90035, 0xf }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */ |
| { 0x90036, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */ |
| { 0x90037, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */ |
| { 0x90038, 0x44 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */ |
| { 0x90039, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */ |
| { 0x9003a, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */ |
| { 0x9003b, 0x14f }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */ |
| { 0x9003c, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */ |
| { 0x9003d, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */ |
| { 0x9003e, 0x47 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */ |
| { 0x9003f, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */ |
| { 0x90040, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */ |
| { 0x90041, 0x4f }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */ |
| { 0x90042, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */ |
| { 0x90043, 0x179 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */ |
| { 0x90044, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */ |
| { 0x90045, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */ |
| { 0x90046, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */ |
| { 0x90047, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */ |
| { 0x90048, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */ |
| { 0x90049, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */ |
| { 0x9004a, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */ |
| { 0x9004b, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */ |
| { 0x9004c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */ |
| { 0x9004d, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */ |
| { 0x9004e, 0x45a }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */ |
| { 0x9004f, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */ |
| { 0x90050, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */ |
| { 0x90051, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */ |
| { 0x90052, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */ |
| { 0x90053, 0x40 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */ |
| { 0x90054, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */ |
| { 0x90055, 0x179 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */ |
| { 0x90056, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */ |
| { 0x90057, 0x618 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */ |
| { 0x90058, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */ |
| { 0x90059, 0x40c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */ |
| { 0x9005a, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */ |
| { 0x9005b, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */ |
| { 0x9005c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */ |
| { 0x9005d, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */ |
| { 0x9005e, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */ |
| { 0x9005f, 0x4040 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */ |
| { 0x90060, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */ |
| { 0x90061, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */ |
| { 0x90062, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */ |
| { 0x90063, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */ |
| { 0x90064, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */ |
| { 0x90065, 0x40 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */ |
| { 0x90066, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */ |
| { 0x90067, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */ |
| { 0x90068, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */ |
| { 0x90069, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */ |
| { 0x9006a, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */ |
| { 0x9006b, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */ |
| { 0x9006c, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */ |
| { 0x9006d, 0x78 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */ |
| { 0x9006e, 0x549 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */ |
| { 0x9006f, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */ |
| { 0x90070, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */ |
| { 0x90071, 0xd49 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */ |
| { 0x90072, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */ |
| { 0x90073, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */ |
| { 0x90074, 0x94a }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */ |
| { 0x90075, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */ |
| { 0x90076, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */ |
| { 0x90077, 0x441 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */ |
| { 0x90078, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */ |
| { 0x90079, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */ |
| { 0x9007a, 0x42 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */ |
| { 0x9007b, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */ |
| { 0x9007c, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */ |
| { 0x9007d, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */ |
| { 0x9007e, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */ |
| { 0x9007f, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */ |
| { 0x90080, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */ |
| { 0x90081, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */ |
| { 0x90082, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */ |
| { 0x90083, 0xa }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */ |
| { 0x90084, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */ |
| { 0x90085, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */ |
| { 0x90086, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */ |
| { 0x90087, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */ |
| { 0x90088, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */ |
| { 0x90089, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */ |
| { 0x9008a, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */ |
| { 0x9008b, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */ |
| { 0x9008c, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */ |
| { 0x9008d, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */ |
| { 0x9008e, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */ |
| { 0x9008f, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */ |
| { 0x90090, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */ |
| { 0x90091, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */ |
| { 0x90092, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */ |
| { 0x90093, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */ |
| { 0x90094, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */ |
| { 0x90095, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */ |
| { 0x90096, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */ |
| { 0x90097, 0x58 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */ |
| { 0x90098, 0xa }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */ |
| { 0x90099, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */ |
| { 0x9009a, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */ |
| { 0x9009b, 0x2 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */ |
| { 0x9009c, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */ |
| { 0x9009d, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */ |
| { 0x9009e, 0x7 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */ |
| { 0x9009f, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */ |
| { 0x900a0, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */ |
| { 0x900a1, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */ |
| { 0x900a2, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */ |
| { 0x900a3, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */ |
| { 0x900a4, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */ |
| { 0x900a5, 0x8140 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */ |
| { 0x900a6, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */ |
| { 0x900a7, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */ |
| { 0x900a8, 0x8138 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */ |
| { 0x900a9, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */ |
| { 0x900aa, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */ |
| { 0x900ab, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */ |
| { 0x900ac, 0x101 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */ |
| { 0x900ad, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */ |
| { 0x900ae, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */ |
| { 0x900af, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */ |
| { 0x900b0, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */ |
| { 0x900b1, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */ |
| { 0x900b2, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */ |
| { 0x900b3, 0xf }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */ |
| { 0x900b4, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */ |
| { 0x900b5, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */ |
| { 0x900b6, 0x47 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */ |
| { 0x900b7, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */ |
| { 0x900b8, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */ |
| { 0x900b9, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */ |
| { 0x900ba, 0x618 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */ |
| { 0x900bb, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */ |
| { 0x900bc, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */ |
| { 0x900bd, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */ |
| { 0x900be, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */ |
| { 0x900bf, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */ |
| { 0x900c0, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */ |
| { 0x900c1, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */ |
| { 0x900c2, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */ |
| { 0x900c3, 0x8140 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */ |
| { 0x900c4, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */ |
| { 0x900c5, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */ |
| { 0x900c6, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */ |
| { 0x900c7, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */ |
| { 0x900c8, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */ |
| { 0x900c9, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */ |
| { 0x900ca, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */ |
| { 0x900cb, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */ |
| { 0x900cc, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */ |
| { 0x900cd, 0x101 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */ |
| { 0x90006, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */ |
| { 0x90007, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */ |
| { 0x90008, 0x8 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */ |
| { 0x90009, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */ |
| { 0x9000a, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */ |
| { 0x9000b, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */ |
| { 0xd00e7, 0x400 }, /* DWC_DDRPHYA_APBONLY0_SequencerOverride */ |
| { 0x90017, 0x0 }, /* DWC_DDRPHYA_INITENG0_StartVector0b0 */ |
| { 0x90026, 0x2c }, /* DWC_DDRPHYA_INITENG0_StartVector0b15 */ |
| { 0x2000b, 0x4b }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */ |
| { 0x2000c, 0x96 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */ |
| { 0x2000d, 0x5dc }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */ |
| { 0x2000e, 0x2c }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */ |
| { 0x12000b, 0xc }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p1 */ |
| { 0x12000c, 0x19 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p1 */ |
| { 0x12000d, 0xfa }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p1 */ |
| { 0x12000e, 0x10 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p1 */ |
| { 0x22000b, 0x3 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p2 */ |
| { 0x22000c, 0x6 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p2 */ |
| { 0x22000d, 0x3e }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p2 */ |
| { 0x22000e, 0x10 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p2 */ |
| { 0x9000c, 0x0 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */ |
| { 0x9000d, 0x173 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */ |
| { 0x9000e, 0x60 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */ |
| { 0x9000f, 0x6110 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */ |
| { 0x90010, 0x2152 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */ |
| { 0x90011, 0xdfbd }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */ |
| { 0x90012, 0xffff }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */ |
| { 0x90013, 0x6152 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */ |
| { 0xc0080, 0x0 }, /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */ |
| { 0xd0000, 0x1 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ |
| }; |
| |
| struct dram_fsp_msg ddr4_dram_fsp_msg[] = { |
| { |
| /* P0 3000mts 1D */ |
| .drate = 2400, |
| .fw_type = FW_1D_IMAGE, |
| .fsp_cfg = ddr4_fsp0_cfg, |
| .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp0_cfg), |
| }, |
| { |
| /* P1 400mts 1D */ |
| .drate = 400, |
| .fw_type = FW_1D_IMAGE, |
| .fsp_cfg = ddr4_fsp1_cfg, |
| .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp1_cfg), |
| }, |
| { |
| /* P2 100mts 1D */ |
| .drate = 100, |
| .fw_type = FW_1D_IMAGE, |
| .fsp_cfg = ddr4_fsp2_cfg, |
| .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp2_cfg), |
| }, |
| { |
| /* P0 3000mts 2D */ |
| .drate = 2400, |
| .fw_type = FW_2D_IMAGE, |
| .fsp_cfg = ddr4_fsp0_2d_cfg, |
| .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp0_2d_cfg), |
| }, |
| }; |
| |
| /* ddr4 timing config params on EVK board */ |
| struct dram_timing_info dram_timing = { |
| .ddrc_cfg = ddr4_ddrc_cfg, |
| .ddrc_cfg_num = ARRAY_SIZE(ddr4_ddrc_cfg), |
| .ddrphy_cfg = ddr4_ddrphy_cfg, |
| .ddrphy_cfg_num = ARRAY_SIZE(ddr4_ddrphy_cfg), |
| .fsp_msg = ddr4_dram_fsp_msg, |
| .fsp_msg_num = ARRAY_SIZE(ddr4_dram_fsp_msg), |
| .ddrphy_trained_csr = ddr4_ddrphy_trained_csr, |
| .ddrphy_trained_csr_num = ARRAY_SIZE(ddr4_ddrphy_trained_csr), |
| .ddrphy_pie = ddr4_phy_pie, |
| .ddrphy_pie_num = ARRAY_SIZE(ddr4_phy_pie), |
| }; |
