tree 8985efb98b69b91ad1810a6613f7cc6d63b6546f
parent cb4b221bf11682069c89b1a5bfb378737825d9e7
author Bai Ping <ping.bai@nxp.com> 1542340674 +0800
committer Ye Li <ye.li@nxp.com> 1558697354 -0700

MLK-20394 imx8mq: Update the ddrc QoS setting for B1 chip

Update the ddrc Qos setting for B1 to align with B0'ssetting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Tested-by: Robby Cai <robby.cai@nxp.com>
(cherry picked from commit 566b798213ab9690966f163de2765acdbfe647a7)