tree db4b69355013d55fb3016ad7146ac4075d19d572
parent 14b042e480fb8cbf9a5b6fee6e29eed7e36e11f1
author Fabien Parent <fparent@baylibre.com> 1564131406 +0200
committer Fabien Parent <fparent@baylibre.com> 1571307460 +0200

clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data

1. pcwibits: The integer bits of pcw for PLLs has been extended
   to 8 bits, add a variable to indicate this change in a
   backward-compatible way.

2. fmin: The PLL frequency lower-bound can vary from 1GHz to
   1.5GHz, add a variable to indicate the platform specific value.

This is a port of commit 9d7e1a82b7d195f901c2a18dd5602a1c11e9eefb from
Linux.

Signed-off-by: Fabien Parent <fparent@baylibre.com>