| commit | ed4f004a9d8aef86f0c0fe0bb6958bef5206c465 | [log] [tgz] |
|---|---|---|
| author | Fabien Parent <fparent@baylibre.com> | Fri Jul 26 10:56:46 2019 +0200 |
| committer | Fabien Parent <fparent@baylibre.com> | Thu Oct 17 12:17:40 2019 +0200 |
| tree | db4b69355013d55fb3016ad7146ac4075d19d572 | |
| parent | 14b042e480fb8cbf9a5b6fee6e29eed7e36e11f1 [diff] |
clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data 1. pcwibits: The integer bits of pcw for PLLs has been extended to 8 bits, add a variable to indicate this change in a backward-compatible way. 2. fmin: The PLL frequency lower-bound can vary from 1GHz to 1.5GHz, add a variable to indicate the platform specific value. This is a port of commit 9d7e1a82b7d195f901c2a18dd5602a1c11e9eefb from Linux. Signed-off-by: Fabien Parent <fparent@baylibre.com>