tree 17981124c3cbdb2ae4dd8b2ad3bd0288a31655bc
parent c02ce6e5a1bc65831c8f638268defa9c6ae70bf1
author York Sun <yorksun@freescale.com> 1285712433 -0700
committer Kumar Gala <galak@kernel.crashing.org> 1287559680 -0500

Add memory test feature for mpc85xx POST.

The memory test is performed after DDR initialization when U-boot stills runs
in flash and cache. On recent mpc85xx platforms, the total memory can be more
than 2GB. To cover whole memory, it needs be mapped 2GB at a time using a
sliding TLB window. After the testing, DDR is remapped with up to 2GB memory
from the lowest address as normal.

If memory test fails, DDR DIMM SPD and DDR controller registers are dumped for
further debugging.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>