/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2018 MediaTek Inc.
 */

#ifndef _DT_BINDINGS_MTK_RESET_H_
#define _DT_BINDINGS_MTK_RESET_H_

/* ETHSYS */
#define ETHSYS_PPE_RST			31
#define ETHSYS_EPHY_RST			24
#define ETHSYS_GMAC_RST			23
#define ETHSYS_ESW_RST			16
#define ETHSYS_FE_RST			6
#define ETHSYS_MCM_RST			2
#define ETHSYS_SYS_RST			0

/* HIFSYS resets */
#define HIFSYS_PCIE2_RST		26
#define HIFSYS_PCIE1_RST		25
#define HIFSYS_PCIE0_RST		24
#define HIFSYS_UPHY1_RST		22
#define HIFSYS_UPHY0_RST		21
#define HIFSYS_UHOST1_RST		4
#define HIFSYS_UHOST0_RST		3

#endif /* _DT_BINDINGS_MTK_RESET_H_ */