/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2018 MediaTek Inc.
 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
 */

#ifndef _DT_BINDINGS_CLK_MT8183_H
#define _DT_BINDINGS_CLK_MT8183_H

/* APMIXED */
#define CLK_APMIXED_ARMPLL_LL		0
#define CLK_APMIXED_ARMPLL_L		1
#define CLK_APMIXED_CCIPLL		2
#define CLK_APMIXED_MAINPLL		3
#define CLK_APMIXED_UNIV2PLL		4
#define CLK_APMIXED_MSDCPLL		5
#define CLK_APMIXED_MMPLL		6
#define CLK_APMIXED_MFGPLL		7
#define CLK_APMIXED_TVDPLL		8
#define CLK_APMIXED_APLL1		9
#define CLK_APMIXED_APLL2		10
#define CLK_APMIXED_SSUSB_26M		11
#define CLK_APMIXED_APPLL_26M		12
#define CLK_APMIXED_MIPIC0_26M		13
#define CLK_APMIXED_MDPLLGP_26M		14
#define CLK_APMIXED_MMSYS_26M		15
#define CLK_APMIXED_UFS_26M		16
#define CLK_APMIXED_MIPIC1_26M		17
#define CLK_APMIXED_MEMPLL_26M		18
#define CLK_APMIXED_CLKSQ_LVPLL_26M	19
#define CLK_APMIXED_MIPID0_26M		20
#define CLK_APMIXED_MIPID1_26M		21
#define CLK_APMIXED_NR_CLK		22

/* TOPCKGEN */
#define CLK_TOP_CLK26M			0
#define CLK_TOP_ULPOSC			1
#define CLK_TOP_UNIVP_192M		2
#define CLK_TOP_CLK13M			3
#define CLK_TOP_F26M_CK_D2		4
#define CLK_TOP_SYSPLL_CK		5
#define CLK_TOP_SYSPLL_D2		6
#define CLK_TOP_SYSPLL_D3		7
#define CLK_TOP_SYSPLL_D5		8
#define CLK_TOP_SYSPLL_D7		9
#define CLK_TOP_SYSPLL_D2_D2		10
#define CLK_TOP_SYSPLL_D2_D4		11
#define CLK_TOP_SYSPLL_D2_D8		12
#define CLK_TOP_SYSPLL_D2_D16		13
#define CLK_TOP_SYSPLL_D3_D2		14
#define CLK_TOP_SYSPLL_D3_D4		15
#define CLK_TOP_SYSPLL_D3_D8		16
#define CLK_TOP_SYSPLL_D5_D2		17
#define CLK_TOP_SYSPLL_D5_D4		18
#define CLK_TOP_SYSPLL_D7_D2		19
#define CLK_TOP_SYSPLL_D7_D4		20
#define CLK_TOP_UNIVPLL_CK		21
#define CLK_TOP_UNIVPLL_D2		22
#define CLK_TOP_UNIVPLL_D3		23
#define CLK_TOP_UNIVPLL_D5		24
#define CLK_TOP_UNIVPLL_D7		25
#define CLK_TOP_UNIVPLL_D2_D2		26
#define CLK_TOP_UNIVPLL_D2_D4		27
#define CLK_TOP_UNIVPLL_D2_D8		28
#define CLK_TOP_UNIVPLL_D3_D2		29
#define CLK_TOP_UNIVPLL_D3_D4		30
#define CLK_TOP_UNIVPLL_D3_D8		31
#define CLK_TOP_UNIVPLL_D5_D2		32
#define CLK_TOP_UNIVPLL_D5_D4		33
#define CLK_TOP_UNIVPLL_D5_D8		34
#define CLK_TOP_UNIVP_192M_CK		35
#define CLK_TOP_UNIVP_192M_D2		36
#define CLK_TOP_UNIVP_192M_D4		37
#define CLK_TOP_UNIVP_192M_D8		38
#define CLK_TOP_UNIVP_192M_D16		39
#define CLK_TOP_UNIVP_192M_D32		40
#define CLK_TOP_APLL1_CK		41
#define CLK_TOP_APLL1_D2		42
#define CLK_TOP_APLL1_D4		43
#define CLK_TOP_APLL1_D8		44
#define CLK_TOP_APLL2_CK		45
#define CLK_TOP_APLL2_D2		46
#define CLK_TOP_APLL2_D4		47
#define CLK_TOP_APLL2_D8		48
#define CLK_TOP_TVDPLL_CK		49
#define CLK_TOP_TVDPLL_D2		50
#define CLK_TOP_TVDPLL_D4		51
#define CLK_TOP_TVDPLL_D8		52
#define CLK_TOP_TVDPLL_D16		53
#define CLK_TOP_MMPLL_CK		54
#define CLK_TOP_MMPLL_D4		55
#define CLK_TOP_MMPLL_D4_D2		56
#define CLK_TOP_MMPLL_D4_D4		57
#define CLK_TOP_MMPLL_D5		58
#define CLK_TOP_MMPLL_D5_D2		59
#define CLK_TOP_MMPLL_D5_D4		60
#define CLK_TOP_MMPLL_D6		61
#define CLK_TOP_MMPLL_D7		62
#define CLK_TOP_MFGPLL_CK		63
#define CLK_TOP_MSDCPLL_CK		64
#define CLK_TOP_MSDCPLL_D2		65
#define CLK_TOP_MSDCPLL_D4		66
#define CLK_TOP_MSDCPLL_D8		67
#define CLK_TOP_MSDCPLL_D16		68
#define CLK_TOP_AD_OSC_CK		69
#define CLK_TOP_OSC_D2			70
#define CLK_TOP_OSC_D4			71
#define CLK_TOP_OSC_D8			72
#define CLK_TOP_OSC_D16			73
#define CLK_TOP_UNIVPLL			74
#define CLK_TOP_UNIVPLL_D3_D16		75
#define CLK_TOP_APLL12_DIV0		76
#define CLK_TOP_APLL12_DIV1		77
#define CLK_TOP_APLL12_DIV2		78
#define CLK_TOP_APLL12_DIV3		79
#define CLK_TOP_APLL12_DIV4		80
#define CLK_TOP_APLL12_DIVB		81
#define CLK_TOP_ARMPLL_DIV_PLL1		82
#define CLK_TOP_ARMPLL_DIV_PLL2		83
#define CLK_TOP_MUX_AXI			84
#define CLK_TOP_MUX_MM			85
#define CLK_TOP_MUX_IMG			86
#define CLK_TOP_MUX_CAM			87
#define CLK_TOP_MUX_DSP			88
#define CLK_TOP_MUX_DSP1		89
#define CLK_TOP_MUX_DSP2		90
#define CLK_TOP_MUX_IPU_IF		91
#define CLK_TOP_MUX_MFG			92
#define CLK_TOP_MUX_F52M_MFG		93
#define CLK_TOP_MUX_CAMTG		94
#define CLK_TOP_MUX_CAMTG2		95
#define CLK_TOP_MUX_CAMTG3		96
#define CLK_TOP_MUX_CAMTG4		97
#define CLK_TOP_MUX_UART		98
#define CLK_TOP_MUX_SPI			99
#define CLK_TOP_MUX_MSDC50_0_HCLK	100
#define CLK_TOP_MUX_MSDC50_0		101
#define CLK_TOP_MUX_MSDC30_1		102
#define CLK_TOP_MUX_MSDC30_2		103
#define CLK_TOP_MUX_AUDIO		104
#define CLK_TOP_MUX_AUD_INTBUS		105
#define CLK_TOP_MUX_PMICSPI		106
#define CLK_TOP_MUX_FPWRAP_ULPOSC	107
#define CLK_TOP_MUX_ATB			108
#define CLK_TOP_MUX_SSPM		109
#define CLK_TOP_MUX_DPI0		110
#define CLK_TOP_MUX_SCAM		111
#define CLK_TOP_MUX_DISP_PWM		112
#define CLK_TOP_MUX_USB_TOP		113
#define CLK_TOP_MUX_SSUSB_TOP_XHCI	114
#define CLK_TOP_MUX_SPM			115
#define CLK_TOP_MUX_I2C			116
#define CLK_TOP_MUX_SCP			117
#define CLK_TOP_MUX_SENINF		118
#define CLK_TOP_MUX_DXCC		119
#define CLK_TOP_MUX_AUD_ENG1		120
#define CLK_TOP_MUX_AUD_ENG2		121
#define CLK_TOP_MUX_FAES_UFSFDE		122
#define CLK_TOP_MUX_FUFS		123
#define CLK_TOP_MUX_AUD_1		124
#define CLK_TOP_MUX_AUD_2		125
#define CLK_TOP_MUX_APLL_I2S0		126
#define CLK_TOP_MUX_APLL_I2S1		127
#define CLK_TOP_MUX_APLL_I2S2		128
#define CLK_TOP_MUX_APLL_I2S3		129
#define CLK_TOP_MUX_APLL_I2S4		130
#define CLK_TOP_MUX_APLL_I2S5		131
#define CLK_TOP_NR_CLK			132

/* INFRACFG_AO */
#define CLK_INFRA_PMIC_TMR		0
#define CLK_INFRA_PMIC_AP		1
#define CLK_INFRA_PMIC_MD		2
#define CLK_INFRA_PMIC_CONN		3
#define CLK_INFRA_SCPSYS		4
#define CLK_INFRA_SEJ			5
#define CLK_INFRA_APXGPT		6
#define CLK_INFRA_ICUSB			7
#define CLK_INFRA_GCE			8
#define CLK_INFRA_THERM			9
#define CLK_INFRA_I2C0			10
#define CLK_INFRA_I2C1			11
#define CLK_INFRA_I2C2			12
#define CLK_INFRA_I2C3			13
#define CLK_INFRA_PWM_HCLK		14
#define CLK_INFRA_PWM1			15
#define CLK_INFRA_PWM2			16
#define CLK_INFRA_PWM3			17
#define CLK_INFRA_PWM4			18
#define CLK_INFRA_PWM			19
#define CLK_INFRA_UART0			20
#define CLK_INFRA_UART1			21
#define CLK_INFRA_UART2			22
#define CLK_INFRA_UART3			23
#define CLK_INFRA_GCE_26M		24
#define CLK_INFRA_CQ_DMA_FPC		25
#define CLK_INFRA_BTIF			26
#define CLK_INFRA_SPI0			27
#define CLK_INFRA_MSDC0			28
#define CLK_INFRA_MSDC1			29
#define CLK_INFRA_MSDC2			30
#define CLK_INFRA_MSDC0_SCK		31
#define CLK_INFRA_DVFSRC		32
#define CLK_INFRA_GCPU			33
#define CLK_INFRA_TRNG			34
#define CLK_INFRA_AUXADC		35
#define CLK_INFRA_CPUM			36
#define CLK_INFRA_CCIF1_AP		37
#define CLK_INFRA_CCIF1_MD		38
#define CLK_INFRA_AUXADC_MD		39
#define CLK_INFRA_MSDC1_SCK		40
#define CLK_INFRA_MSDC2_SCK		41
#define CLK_INFRA_AP_DMA		42
#define CLK_INFRA_XIU			43
#define CLK_INFRA_DEVICE_APC		44
#define CLK_INFRA_CCIF_AP		45
#define CLK_INFRA_DEBUGSYS		46
#define CLK_INFRA_AUDIO			47
#define CLK_INFRA_CCIF_MD		48
#define CLK_INFRA_DXCC_SEC_CORE		49
#define CLK_INFRA_DXCC_AO		50
#define CLK_INFRA_DRAMC_F26M		51
#define CLK_INFRA_IRTX			52
#define CLK_INFRA_DISP_PWM		53
#define CLK_INFRA_CLDMA_BCLK		54
#define CLK_INFRA_AUDIO_26M_BCLK	55
#define CLK_INFRA_SPI1			56
#define CLK_INFRA_I2C4			57
#define CLK_INFRA_MODEM_TEMP_SHARE	58
#define CLK_INFRA_SPI2			59
#define CLK_INFRA_SPI3			60
#define CLK_INFRA_UNIPRO_SCK		61
#define CLK_INFRA_UNIPRO_TICK		62
#define CLK_INFRA_UFS_MP_SAP_BCLK	63
#define CLK_INFRA_MD32_BCLK		64
#define CLK_INFRA_SSPM			65
#define CLK_INFRA_UNIPRO_MBIST		66
#define CLK_INFRA_SSPM_BUS_HCLK		67
#define CLK_INFRA_I2C5			68
#define CLK_INFRA_I2C5_ARBITER		69
#define CLK_INFRA_I2C5_IMM		70
#define CLK_INFRA_I2C1_ARBITER		71
#define CLK_INFRA_I2C1_IMM		72
#define CLK_INFRA_I2C2_ARBITER		73
#define CLK_INFRA_I2C2_IMM		74
#define CLK_INFRA_SPI4			75
#define CLK_INFRA_SPI5			76
#define CLK_INFRA_CQ_DMA		77
#define CLK_INFRA_UFS			78
#define CLK_INFRA_AES_UFSFDE		79
#define CLK_INFRA_UFS_TICK		80
#define CLK_INFRA_MSDC0_SELF		81
#define CLK_INFRA_MSDC1_SELF		82
#define CLK_INFRA_MSDC2_SELF		83
#define CLK_INFRA_SSPM_26M_SELF		84
#define CLK_INFRA_SSPM_32K_SELF		85
#define CLK_INFRA_UFS_AXI		86
#define CLK_INFRA_I2C6			87
#define CLK_INFRA_AP_MSDC0		88
#define CLK_INFRA_MD_MSDC0		89
#define CLK_INFRA_USB			90
#define CLK_INFRA_DEVMPU_BCLK		91
#define CLK_INFRA_CCIF2_AP		92
#define CLK_INFRA_CCIF2_MD		93
#define CLK_INFRA_CCIF3_AP		94
#define CLK_INFRA_CCIF3_MD		95
#define CLK_INFRA_SEJ_F13M		96
#define CLK_INFRA_AES_BCLK		97
#define CLK_INFRA_I2C7			98
#define CLK_INFRA_I2C8			99
#define CLK_INFRA_FBIST2FPC		100
#define CLK_INFRA_NR_CLK		101

/* MMSYS_CONFIG */
#define CLK_MM_SMI_COMMON		0
#define CLK_MM_SMI_LARB0		1
#define CLK_MM_SMI_LARB1		2
#define CLK_MM_GALS_COMM0		3
#define CLK_MM_GALS_COMM1		4
#define CLK_MM_GALS_CCU2MM		5
#define CLK_MM_GALS_IPU12MM		6
#define CLK_MM_GALS_IMG2MM		7
#define CLK_MM_GALS_CAM2MM		8
#define CLK_MM_GALS_IPU2MM		9
#define CLK_MM_MDP_DL_TXCK		10
#define CLK_MM_IPU_DL_TXCK		11
#define CLK_MM_MDP_RDMA0		12
#define CLK_MM_MDP_RDMA1		13
#define CLK_MM_MDP_RSZ0			14
#define CLK_MM_MDP_RSZ1			15
#define CLK_MM_MDP_TDSHP		16
#define CLK_MM_MDP_WROT0		17
#define CLK_MM_FAKE_ENG			18
#define CLK_MM_DISP_OVL0		19
#define CLK_MM_DISP_OVL0_2L		20
#define CLK_MM_DISP_OVL1_2L		21
#define CLK_MM_DISP_RDMA0		22
#define CLK_MM_DISP_RDMA1		23
#define CLK_MM_DISP_WDMA0		24
#define CLK_MM_DISP_COLOR0		25
#define CLK_MM_DISP_CCORR0		26
#define CLK_MM_DISP_AAL0		27
#define CLK_MM_DISP_GAMMA0		28
#define CLK_MM_DISP_DITHER0		29
#define CLK_MM_DISP_SPLIT		30
#define CLK_MM_DSI0_MM			31
#define CLK_MM_DSI0_IF			32
#define CLK_MM_DPI_MM			33
#define CLK_MM_DPI_IF			34
#define CLK_MM_FAKE_ENG2		35
#define CLK_MM_MDP_DL_RX		36
#define CLK_MM_IPU_DL_RX		37
#define CLK_MM_26M			38
#define CLK_MM_MMSYS_R2Y		39
#define CLK_MM_DISP_RSZ			40
#define CLK_MM_MDP_WDMA0		41
#define CLK_MM_MDP_AAL			42
#define CLK_MM_MDP_CCORR		43
#define CLK_MM_DBI_MM			44
#define CLK_MM_DBI_IF			45
#define CLK_MM_NR_CLK			46

/* MCUCFG */
#define CLK_MCU_MP0_SEL			0
#define CLK_MCU_MP2_SEL			1
#define CLK_MCU_BUS_SEL			2
#define CLK_MCU_NR_CLK			3

#endif /* _DT_BINDINGS_CLK_MT8183_H */