// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for AM6 SoC Family Main Domain peripherals
 *
 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
 */

#include <dt-bindings/phy/phy-am654-serdes.h>
#include <dt-bindings/phy/phy.h>

&cbass_main {
	gic500: interrupt-controller@1800000 {
		compatible = "arm,gic-v3";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
		      <0x00 0x01880000 0x00 0x90000>;	/* GICR */
		/*
		 * vcpumntirq:
		 * virtual CPU interface maintenance interrupt
		 */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		gic_its: gic-its@18200000 {
			compatible = "arm,gic-v3-its";
			reg = <0x00 0x01820000 0x00 0x10000>;
			msi-controller;
			#msi-cells = <1>;
		};
	};

	secure_proxy_main: mailbox@32c00000 {
		compatible = "ti,am654-secure-proxy";
		#mbox-cells = <1>;
		reg-names = "target_data", "rt", "scfg";
		reg = <0x00 0x32c00000 0x00 0x100000>,
		      <0x00 0x32400000 0x00 0x100000>,
		      <0x00 0x32800000 0x00 0x100000>;
		interrupt-names = "rx_011";
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	};

	main_uart0: serial@2800000 {
		compatible = "ti,am654-uart";
		reg = <0x00 0x02800000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
	};

	main_uart1: serial@2810000 {
		compatible = "ti,am654-uart";
		reg = <0x00 0x02810000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
	};

	main_uart2: serial@2820000 {
		compatible = "ti,am654-uart";
		reg = <0x00 0x02820000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
	};

	main_pmx0: pinmux@11c000 {
		compatible = "pinctrl-single";
		reg = <0x0 0x11c000 0x0 0x2e4>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	main_pmx1: pinmux@11c2e8 {
		compatible = "pinctrl-single";
		reg = <0x0 0x11c2e8 0x0 0x24>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	sdhci0: sdhci@4f80000 {
		compatible = "ti,am654-sdhci-5.1";
		reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
		power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
		clock-names = "clk_ahb", "clk_xin";
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
		mmc-ddr-1_8v;
		mmc-hs200-1_8v;
		ti,otap-del-sel = <0x2>;
		ti,trm-icp = <0x8>;
		dma-coherent;
	};

	main_i2c0: i2c@2000000 {
		compatible = "ti,am654-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2000000 0x0 0x100>;
		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 110 1>;
		power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c1: i2c@2010000 {
		compatible = "ti,am654-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2010000 0x0 0x100>;
		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 111 1>;
		power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c2: i2c@2020000 {
		compatible = "ti,am654-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2020000 0x0 0x100>;
		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 112 1>;
		power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c3: i2c@2030000 {
		compatible = "ti,am654-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2030000 0x0 0x100>;
		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 113 1>;
		power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
	};

	scm_conf: scm_conf@100000 {
		compatible = "syscon", "simple-mfd";
		reg = <0 0x00100000 0 0x1c000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x00100000 0x1c000>;

		serdes_mux: mux-controller {
			compatible = "mmio-mux";
			#mux-control-cells = <1>;
			mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
					<0x4090 0x3>; /* SERDES1 lane select */
		};

		pcie0_mode: pcie-mode@4060 {
			compatible = "syscon";
			reg = <0x00004060 0x4>;
		};

		pcie1_mode: pcie-mode@4070 {
			compatible = "syscon";
			reg = <0x00004070 0x4>;
		};

		serdes0_clk: serdes_clk@4080 {
			compatible = "syscon";
			reg = <0x00004080 0x4>;
		};

		serdes1_clk: serdes_clk@4090 {
			compatible = "syscon";
			reg = <0x00004090 0x4>;
		};

		pcie_devid: pcie-devid@210 {
			compatible = "syscon";
			reg = <0x00000210 0x4>;
		};
	};

	serdes0: serdes@900000 {
		compatible = "ti,phy-am654-serdes";
		reg = <0x0 0x900000 0x0 0x2000>;
		reg-names = "serdes";
		#phy-cells = <2>;
		power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
		clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
		assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
		assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
		ti,serdes-clk = <&serdes0_clk>;
		mux-controls = <&serdes_mux 0>;
		#clock-cells = <1>;
	};

	serdes1: serdes@910000 {
		compatible = "ti,phy-am654-serdes";
		reg = <0x0 0x910000 0x0 0x2000>;
		reg-names = "serdes";
		#phy-cells = <2>;
		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
		clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
		assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
		assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
		ti,serdes-clk = <&serdes1_clk>;
		mux-controls = <&serdes_mux 1>;
		#clock-cells = <1>;
	};

	pcie0_rc: pcie@5500000 {
		compatible = "ti,am654-pcie-rc";
		reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
		reg-names = "app", "dbics", "config", "atu";
		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x81000000 0 0          0x0   0x10020000 0 0x00010000
			  0x82000000 0 0x10030000 0x0   0x10030000 0 0x07FD0000>;
		ti,syscon-pcie-id = <&pcie_devid>;
		ti,syscon-pcie-mode = <&pcie0_mode>;
		bus-range = <0x0 0xff>;
		status = "disabled";
		device_type = "pci";
		num-lanes = <1>;
		num-ob-windows = <16>;
		num-viewport = <16>;
		max-link-speed = <3>;
		interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */
				<0 0 0 2 &pcie0_intc 0>, /* INT B */
				<0 0 0 3 &pcie0_intc 0>, /* INT C */
				<0 0 0 4 &pcie0_intc 0>; /* INT D */
		msi-map = <0x0 &gic_its 0x0 0x10000>;

		pcie0_intc: legacy-interrupt-controller@1 {
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
		};
	};
};