)]}' { "log": [ { "commit": "00cfbdb30a97262c4c90a470c37958a680b4b5a7", "tree": "e6b9da45413a7d366323bd5f1f3d6b434bdeb78e", "parents": [ "27617534736d53c459562294f6ae885ed324c8ad" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Sep 29 15:04:26 2020 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Sep 29 15:04:26 2020 -0700" }, "message": "Set baud rate to 115200\n\nChange-Id: I954b6b6278b3f3928c8cc0751ef8f3380e61959f\n" }, { "commit": "27617534736d53c459562294f6ae885ed324c8ad", "tree": "5e3393e47cc2f14f1a5596dc68476d1b6f27e163", "parents": [ "3c28d05604548267de21a7cf457072e00a6b47e9" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Wed Jul 29 16:58:05 2020 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Thu Jul 30 11:36:02 2020 -0700" }, "message": "Port 4.4 suspend code into TF-A\n\n- Import register layout, flag definitions, etc. from 4.4\n- Import low-power core firmware\n- Copy register settings and control flow from 4.4\n- Fix a bug on resume where the wrong initialization was called for the\ninterrupt controller.\n\nChange-Id: Ia32717f7b6715b85370a382fa343a474d5fbb20a\n" }, { "commit": "3c28d05604548267de21a7cf457072e00a6b47e9", "tree": "dfea62889fba8af58f17422ebaa5b44fe0925a43", "parents": [ "2a0aa165464d765cc2305669ca7f49cf1e88614b" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Mon Jul 27 17:22:04 2020 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Mon Jul 27 17:22:04 2020 -0700" }, "message": "Turn on VCAM_AF regulator in bootloader\n\nTurn on the power rail so we can set LED GPIO in u-boot\n\nChange-Id: I53405b52b573e67a519c40a5b70e4aecacb6ce2c\n" }, { "commit": "2a0aa165464d765cc2305669ca7f49cf1e88614b", "tree": "7fbe2a304910b666d78a294a9b007f3bc1e26715", "parents": [ "9c0893ef5207d9b333b61f7000a6adc3f19d298f" ], "author": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Tue Jul 21 19:53:39 2020 -0700" }, "committer": { "name": "Cindy Liu", "email": "hcindyl@google.com", "time": "Thu Jul 23 19:26:25 2020 -0700" }, "message": "Update BBPU register setting for poweroff\n\nChange BBPU register setting in poweroff for Excelsior board to\navoid reboot.\n\nChange-Id: I809bee29d21347127a4f25292363f39e891c37cf\n" }, { "commit": "9c0893ef5207d9b333b61f7000a6adc3f19d298f", "tree": "79c3fd05381ca6dd69947a34455953b896df3c6f", "parents": [ "a46c5fdeca02b3b1426fdeefad11048c331f9c11" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Thu Jul 16 17:33:11 2020 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Fri Jul 17 10:57:25 2020 -0700" }, "message": "Fix RTC base register\n\n- We were using the base register for MT6397 instead of MT6392.\n\nChange-Id: I7ee15f00c69f70b8c9808093af1b248ddcc0f2b1\n" }, { "commit": "a46c5fdeca02b3b1426fdeefad11048c331f9c11", "tree": "4931855987025a17e01cbab5a596b8aaeae72e21", "parents": [ "c287c4478c7ca871180f2a08f08368d99113b5ae" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Jul 14 12:58:02 2020 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Jul 14 13:27:41 2020 -0700" }, "message": "Fix core offlining\n\n- Shut down the CPU properly when requested, so that we can turn it on\nproperly later.\n\nChange-Id: I24ad354252f8d55a4b4ac2bb45f684964b71149c\n" }, { "commit": "c287c4478c7ca871180f2a08f08368d99113b5ae", "tree": "28fe5b62aee1be6bea0ef1e773886f5324588458", "parents": [ "74fe2c94c11100efbf4b9a5566f0f0310ac976dc" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Mon May 18 12:42:05 2020 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue May 19 16:53:48 2020 -0700" }, "message": "Enable VGP1 regulator\n\n- Turn on VGP1 for the crypto chip. We don\u0027t have a PMIC driver in\nu-boot, so this is a convenient place to enable it.\n\nChange-Id: I8a65e62369209925f9c08b6602fe80397f5bdfd7\n" }, { "commit": "74fe2c94c11100efbf4b9a5566f0f0310ac976dc", "tree": "6d3fac0faac9d4fa9cd343d9cf418e3f645041ef", "parents": [ "a7da017a800759982e522066580205367c9a4531" ], "author": { "name": "Fabien Parent", "email": "fparent@baylibre.com", "time": "Thu Oct 31 17:49:26 2019 +0100" }, "committer": { "name": "Fabien Parent", "email": "fparent@baylibre.com", "time": "Thu Oct 31 17:49:26 2019 +0100" }, "message": "prebuilt: mt8183: don\u0027t require op-tee in fip.bin\n\nSigned-off-by: Fabien Parent \u003cfparent@baylibre.com\u003e\n" }, { "commit": "a7da017a800759982e522066580205367c9a4531", "tree": "97645c3c82fb844b3208d2c0fc290670b7e9b3b2", "parents": [ "01047b090f38600be624f8fdc466d5e2193fd279" ], "author": { "name": "Fabien Parent", "email": "fparent@baylibre.com", "time": "Thu Oct 24 14:40:10 2019 +0200" }, "committer": { "name": "Fabien Parent", "email": "fparent@baylibre.com", "time": "Thu Oct 24 14:40:10 2019 +0200" }, "message": "prebuilt: mt8183: update bl2 to v2.2 release\n\nSigned-off-by: Fabien Parent \u003cfparent@baylibre.com\u003e\n" }, { "commit": "01047b090f38600be624f8fdc466d5e2193fd279", "tree": "49e4fe77b71884d964b3605d2c539ce2ef20c151", "parents": [ "6e9f33b284d4195b208a56c6556a588a610628c6" ], "author": { "name": "Fabien Parent", "email": "fparent@baylibre.com", "time": "Wed Sep 25 14:24:34 2019 +0200" }, "committer": { "name": "Fabien Parent", "email": "fparent@baylibre.com", "time": "Thu Oct 24 14:37:24 2019 +0200" }, "message": "Add prebuilt release binary for MT8516 \u0026 MT8183\n\nAdd the prebuilt binaries for MT8516 and MT8183.\n\nSigned-off-by: Fabien Parent \u003cfparent@baylibre.com\u003e\n" }, { "commit": "6e9f33b284d4195b208a56c6556a588a610628c6", "tree": "faebaa1be535ba8c8f4b8826dbdc567e07bbf7fb", "parents": [ "d06491a7b349e2fb138d7e945e850a70cede6a3a" ], "author": { "name": "Fabien Parent", "email": "fparent@baylibre.com", "time": "Mon Aug 12 16:59:10 2019 +0200" }, "committer": { "name": "Fabien Parent", "email": "fparent@baylibre.com", "time": "Thu Oct 24 14:37:00 2019 +0200" }, "message": "mediatek: mt8183: pm: use WDT to reset the chip\n\nSigned-off-by: Fabien Parent \u003cfparent@baylibre.com\u003e\n" }, { "commit": "d06491a7b349e2fb138d7e945e850a70cede6a3a", "tree": "47dd7746477938b5510f3301f3fcf18abd4eb9e5", "parents": [ "a04808c16cfc126d9fe572ae7c4b5a3d39de5796" ], "author": { "name": "Fabien Parent", "email": "fparent@baylibre.com", "time": "Mon Jan 21 12:19:14 2019 +0100" }, "committer": { "name": "Fabien Parent", "email": "fparent@baylibre.com", "time": "Thu Oct 24 14:37:00 2019 +0200" }, "message": "mediatek: mt8516: Add BL31 support\n\nSigned-off-by: Fabien Parent \u003cfparent@baylibre.com\u003e\n" }, { "commit": "a04808c16cfc126d9fe572ae7c4b5a3d39de5796", "tree": "880680a3c21ce08ba1407347a2041c2397dc69b4", "parents": [ "c381ab6897696ba2411a532445ed57ddc0384c2a", "2ee6b2bc77b6f967d5e28e030c9447e9c0ea9cac" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Tue Oct 22 13:36:23 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 22 13:36:23 2019 +0000" }, "message": "Merge \"Update TF-A version to 2.2\" into integration" }, { "commit": "c381ab6897696ba2411a532445ed57ddc0384c2a", "tree": "d170c7e6184bad5befd015c09cd23115133b21c1", "parents": [ "e654a0e3812f59d46a9c9e72d0a0d44070b6c0be", "77caea29607747f9c75c6293f6b12a9c4cbef3a6" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Tue Oct 22 13:35:44 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 22 13:35:44 2019 +0000" }, "message": "Merge \"Update change log for v2.2 Release\" into integration" }, { "commit": "e654a0e3812f59d46a9c9e72d0a0d44070b6c0be", "tree": "29febf094442f14a87b531d75162615b9a35241a", "parents": [ "0938473aa5001d4b8c3c86abf356ea71170b7d5a", "e69f3500381638eca41152589ea78169f48aa191" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Tue Oct 22 13:35:23 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 22 13:35:23 2019 +0000" }, "message": "Merge \"Update release-information for v2.2 Release\" into integration" }, { "commit": "0938473aa5001d4b8c3c86abf356ea71170b7d5a", "tree": "ef70f74a8ebe1b082b241da658e3f209a2ab185b", "parents": [ "0c2f6854cc79bfa3f94daf50fffeb476b67b8cf9", "bbf0a1e43479ccfcbb0229cca744d17165749dce" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Tue Oct 22 13:34:57 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 22 13:34:57 2019 +0000" }, "message": "Merge \"doc: Final, pre-release fixes and updates\" into integration" }, { "commit": "bbf0a1e43479ccfcbb0229cca744d17165749dce", "tree": "ef70f74a8ebe1b082b241da658e3f209a2ab185b", "parents": [ "0c2f6854cc79bfa3f94daf50fffeb476b67b8cf9" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Mon Oct 21 16:37:13 2019 +0000" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Tue Oct 22 13:15:02 2019 +0000" }, "message": "doc: Final, pre-release fixes and updates\n\nA small set of misc changes to ensure correctness before the v2.2\nrelease tagging.\n\nChange-Id: I888840b9483ea1a1633d204fbbc0f9594072101e\nSigned-off-by: Paul Beesley \u003cpaul.beesley@arm.com\u003e\n" }, { "commit": "e69f3500381638eca41152589ea78169f48aa191", "tree": "5454ebccbadd433f627daa48351cde01b96bbd5c", "parents": [ "0c2f6854cc79bfa3f94daf50fffeb476b67b8cf9" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Wed Oct 16 16:32:16 2019 -0500" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Tue Oct 22 13:05:50 2019 +0000" }, "message": "Update release-information for v2.2 Release\n\nRemoved deprecated interfaces that have been removed from the TF-A\nproject, updated the deprecated list with new deprecations for v2.2\nRelease, added upcoming release information, remove mentions of PR from\ngithub.\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nSigned-off-by: Paul Beesley \u003cpaul.beesley@arm.com\u003e\nChange-Id: I2b59d351cde9860ad0dcb6520a8bd2827ad403cf\n" }, { "commit": "0c2f6854cc79bfa3f94daf50fffeb476b67b8cf9", "tree": "9e5424c879cea746ca2f493f87c522355bbaf9df", "parents": [ "1f96d12868a1355e32bdd0e58898782694fc6b5b", "48730856e8b44bc46f8c0e76ec4d984c5f1844f2" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Tue Oct 22 08:01:35 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 22 08:01:35 2019 +0000" }, "message": "Merge \"doc: Expand contact information in About section\" into integration" }, { "commit": "48730856e8b44bc46f8c0e76ec4d984c5f1844f2", "tree": "9e5424c879cea746ca2f493f87c522355bbaf9df", "parents": [ "1f96d12868a1355e32bdd0e58898782694fc6b5b" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Wed Oct 16 13:48:12 2019 +0000" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Tue Oct 22 08:00:29 2019 +0000" }, "message": "doc: Expand contact information in About section\n\nGiving a bit more background information about the issue tracker\nand mailing lists.\n\nChange-Id: I68921d54e3113d348f1e16c685f74d32df2ca19f\nSigned-off-by: Paul Beesley \u003cpaul.beesley@arm.com\u003e\n" }, { "commit": "1f96d12868a1355e32bdd0e58898782694fc6b5b", "tree": "01aca4354a9d6e2f961b6ede7278041657fe0cdf", "parents": [ "3a90b7c182d586fc37fc4de34764d48eaec5efc2", "5e6b4163905563be5dee7303c66188180af33500" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Tue Oct 22 07:59:47 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 22 07:59:47 2019 +0000" }, "message": "Merge \"doc: Move platform list to the Platform Ports index page\" into integration" }, { "commit": "3a90b7c182d586fc37fc4de34764d48eaec5efc2", "tree": "9676badd2bc3246ea1ae0459cbea8050c529f122", "parents": [ "937f669872b5516c9a0fd3d60f9618ad54a72b5c", "8eb9490b61c65288eaacbf229afbbe0f99484c86" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Tue Oct 22 07:59:19 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 22 07:59:19 2019 +0000" }, "message": "Merge \"doc: Move \"About\" content from index.rst to a new chapter\" into integration" }, { "commit": "77caea29607747f9c75c6293f6b12a9c4cbef3a6", "tree": "75fb3619d65d2a0faa24016aa7bbfec313c43a81", "parents": [ "6f0c77f0c7c224b0e4be2aaf3cfedcbdcba9a144" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Fri Oct 11 14:10:09 2019 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Mon Oct 21 10:20:30 2019 -0500" }, "message": "Update change log for v2.2 Release\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I53a7706016539e7de7fdbe87b786d99665bbe1d8\n" }, { "commit": "5e6b4163905563be5dee7303c66188180af33500", "tree": "01aca4354a9d6e2f961b6ede7278041657fe0cdf", "parents": [ "8eb9490b61c65288eaacbf229afbbe0f99484c86" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Wed Oct 16 13:41:13 2019 +0000" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Mon Oct 21 13:31:49 2019 +0000" }, "message": "doc: Move platform list to the Platform Ports index page\n\nThe list of upstream platforms on the index page is growing\nquite long, especially with all the FVP variants being listed\nindividually.\n\nThis patch leverages the \"Platform Ports\" chapter in the docs\ntable of contents to condense this information. Almost all\nplatform ports now have documentation, so the table of\ncontents serves as the list of upstream platforms by itself.\n\nFor those upstream platforms that do not have corresponding\ndocumentation, the top-level \"Platform Ports\" page mentions\nthem individually. It also mentions each Arm FVP, just as\nthe index page did before.\n\nNote that there is an in-progress patch that creates new\nplatform port documentation for the Arm Juno and Arm FVP\nplatforms, so this list of \"other platforms\" will soon be\nreduced further as those platforms become part of the\ntable of contents as well.\n\nChange-Id: I6b1eab8cba71a599d85a6e22553a34b07f213268\nSigned-off-by: Paul Beesley \u003cpaul.beesley@arm.com\u003e\n" }, { "commit": "8eb9490b61c65288eaacbf229afbbe0f99484c86", "tree": "9676badd2bc3246ea1ae0459cbea8050c529f122", "parents": [ "937f669872b5516c9a0fd3d60f9618ad54a72b5c" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Wed Oct 16 13:35:47 2019 +0000" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Mon Oct 21 13:31:49 2019 +0000" }, "message": "doc: Move \"About\" content from index.rst to a new chapter\n\nThe index.rst page is now the primary landing page for the TF-A\ndocumentation. It contains quite a lot of content these days,\nincluding:\n\n- The project purpose and general intro\n- A list of functionality\n- A list of planned functionality\n- A list of supported platforms\n- \"Getting started\" links to other documents\n- Contact information for raising issues\n\nThis patch creates an \"About\" chapter in the table\nof contents and moves some content there. In order,\nthe above listed content:\n\n- Stayed where it is. This is the right place for it.\n- Moved to About-\u003eFeatures\n- Moved to About-\u003eFeatures (in subsection)\n- Stayed where it is. Moved in a later patch.\n- Was expanded in-place\n- Moved to About-\u003eContact\n\nChange-Id: I254bb87560fd09140b9e485cf15246892aa45943\nSigned-off-by: Paul Beesley \u003cpaul.beesley@arm.com\u003e\n" }, { "commit": "937f669872b5516c9a0fd3d60f9618ad54a72b5c", "tree": "338e4996cecb8db24c268a40715073aac18515d2", "parents": [ "942bb52e99f317579256b5d146b43221b1788fac", "0e7a0540d728122913afbc99df4c4b87a19e8048" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Oct 21 12:10:16 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 21 12:10:16 2019 +0000" }, "message": "Merge \"xlat_table_v2: Fix enable WARMBOOT_ENABLE_DCACHE_EARLY config\" into integration" }, { "commit": "942bb52e99f317579256b5d146b43221b1788fac", "tree": "babe58b92600f291d9d1e1efffc7c216d5547b6f", "parents": [ "879389edd6c0a89854a9c222541c6caba92e7aaf", "89632e6aeba8414c1901eecb5d885363c73448f0" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Oct 21 12:09:52 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 21 12:09:52 2019 +0000" }, "message": "Merge \"Replace deprecated __ASSEMBLY__ macro with __ASSEMBLER__\" into integration" }, { "commit": "0e7a0540d728122913afbc99df4c4b87a19e8048", "tree": "76aca5998c88cb0fcdef1118d91c8c247a2e4268", "parents": [ "19adcb415c313d656324d54e7608cdc7d7a5c414" ], "author": { "name": "Artsem Artsemenka", "email": "artsem.artsemenka@arm.com", "time": "Thu Oct 17 13:51:27 2019 +0100" }, "committer": { "name": "Artsem Artsemenka", "email": "artsem.artsemenka@arm.com", "time": "Fri Oct 18 10:26:34 2019 +0100" }, "message": "xlat_table_v2: Fix enable WARMBOOT_ENABLE_DCACHE_EARLY config\n\nThe WARMBOOT_ENABLE_DCACHE_EARLY allows caches to be turned on early during\nthe boot. But the xlat_change_mem_attributes_ctx() API did not do the required\ncache maintenance after the mmap tables are modified if\nWARMBOOT_ENABLE_DCACHE_EARLY is enabled. This meant that when the caches are turned\noff during power down, the tables in memory are accessed as part of cache\nmaintenance for power down, and the tables are not correct at this point which\nresults in a data abort.\nThis patch removes the optimization within xlat_change_mem_attributes_ctx()\nwhen WARMBOOT_ENABLE_DCACHE_EARLY is enabled.\n\nSigned-off-by: Artsem Artsemenka \u003cartsem.artsemenka@arm.com\u003e\nChange-Id: I82de3decba87dd13e9856b5f3620a1c8571c8d87\n" }, { "commit": "879389edd6c0a89854a9c222541c6caba92e7aaf", "tree": "a7b19ccf60f0bc9af302d3cc63ea161878d183cb", "parents": [ "b8f478b137bfed489b807b887f8ecfcac3257404", "434d93d96ae152ae616c73ef58d3f41d07c750ca" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Fri Oct 18 08:38:23 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 18 08:38:23 2019 +0000" }, "message": "Merge \"Fix documentation\" into integration" }, { "commit": "b8f478b137bfed489b807b887f8ecfcac3257404", "tree": "98d85f30df09b67d0c07d650e96cf13cc73d61e3", "parents": [ "19adcb415c313d656324d54e7608cdc7d7a5c414", "206c077b831870463178b016b5b151bcb5baf913" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Fri Oct 18 08:36:53 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 18 08:36:53 2019 +0000" }, "message": "Merge \"doc: Remove version and release variables from conf.py\" into integration" }, { "commit": "206c077b831870463178b016b5b151bcb5baf913", "tree": "98d85f30df09b67d0c07d650e96cf13cc73d61e3", "parents": [ "19adcb415c313d656324d54e7608cdc7d7a5c414" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Thu Oct 17 13:39:06 2019 +0000" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Thu Oct 17 13:46:38 2019 +0000" }, "message": "doc: Remove version and release variables from conf.py\n\nWe would need to update this version for the release but, in fact,\nit is not required for our publishing workflow; the hosted version\nof the docs uses git commit/tag information in place of these\nvariables anyway.\n\nInstead of updating the version, just remove these variables\nentirely.\n\nChange-Id: I424c4e45786e87604e91c7197b7983579afe4806\nSigned-off-by: Paul Beesley \u003cpaul.beesley@arm.com\u003e\n" }, { "commit": "434d93d96ae152ae616c73ef58d3f41d07c750ca", "tree": "903ad480ae89ba736aae37ee7281478dbba7f926", "parents": [ "4fdad60c34549adb0a420e826394286d1d983df3" ], "author": { "name": "Artsem Artsemenka", "email": "artsem.artsemenka@arm.com", "time": "Tue Oct 15 14:59:04 2019 +0100" }, "committer": { "name": "Artsem Artsemenka", "email": "artsem.artsemenka@arm.com", "time": "Tue Oct 15 22:37:02 2019 +0100" }, "message": "Fix documentation\n\nUser guide:\n1. Remove obsolete note saying only FVP is supported with AArch32\n2. Switch compiler for Juno AArch32 to arm-eabi\n3. Mention SOFTWARE folder in Juno Linaro release\n\nIndex.rst:\n1. Switch default FVP model to Version 11.6 Build 45\n\nSigned-off-by: Artsem Artsemenka \u003cartsem.artsemenka@arm.com\u003e\nChange-Id: Ib47a2ea314e2b8394a20189bf91796de0e17de53\n" }, { "commit": "2ee6b2bc77b6f967d5e28e030c9447e9c0ea9cac", "tree": "4d101f2c1c081c01ab7ed96b2490aee4baff292a", "parents": [ "6f0c77f0c7c224b0e4be2aaf3cfedcbdcba9a144" ], "author": { "name": "Deepika Bhavnani", "email": "deepika.bhavnani@arm.com", "time": "Tue Oct 15 10:47:09 2019 -0500" }, "committer": { "name": "Deepika Bhavnani", "email": "deepika.bhavnani@arm.com", "time": "Tue Oct 15 10:47:09 2019 -0500" }, "message": "Update TF-A version to 2.2\n\nSigned-off-by: Deepika Bhavnani \u003cdeepika.bhavnani@arm.com\u003e\nChange-Id: Ia03701e2e37e3a00a501b144960a4a65aedbfde9\n" }, { "commit": "19adcb415c313d656324d54e7608cdc7d7a5c414", "tree": "f850ae492465fe2e1222f4d29ef8c3f68725874d", "parents": [ "a05c8f873134be55754f67d56b2062b97274cbc5", "38d5e150edc82570e1a3e9dc2e95dce96e6fd94e" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Tue Oct 15 14:05:28 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 15 14:05:28 2019 +0000" }, "message": "Merge \"Correct UART PL011 initialization calculation\" into integration" }, { "commit": "a05c8f873134be55754f67d56b2062b97274cbc5", "tree": "1f51d64dce96921f109fadc60a2058a0abf50250", "parents": [ "7921fe6a764a327b77da5cba8e7eaacaec41fdaa", "9ec4afc8ddb5d415bd5fac2134b4012b32920bcc" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Tue Oct 15 12:46:02 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 15 12:46:02 2019 +0000" }, "message": "Merge \"doc: Update Linaro release mentioned on index page\" into integration" }, { "commit": "9ec4afc8ddb5d415bd5fac2134b4012b32920bcc", "tree": "d77c0211b8f1bdd8265e75cf8657494439800620", "parents": [ "6f0c77f0c7c224b0e4be2aaf3cfedcbdcba9a144" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Tue Oct 15 09:08:12 2019 +0000" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Tue Oct 15 09:14:46 2019 +0000" }, "message": "doc: Update Linaro release mentioned on index page\n\nThe version of the Linaro release that is used for testing was\nupdated in 35010bb8 and the user guide was updated with the\ncorrect version, however the version is also mentioned on the\nindex page and that was missed. Update the index page with the\nnew version.\n\nWe can come back and de-duplicate this content later, to ease\nfuture maintenance.\n\nChange-Id: I3fe83d7a1c59ab8d3ce2b18bcc23e16c93f7af97\nSigned-off-by: Paul Beesley \u003cpaul.beesley@arm.com\u003e\n" }, { "commit": "7921fe6a764a327b77da5cba8e7eaacaec41fdaa", "tree": "e0f14828750f595ee14a7ad836b8a56deea252f4", "parents": [ "6f0c77f0c7c224b0e4be2aaf3cfedcbdcba9a144", "be653a6940b6c7bf3c0c6b7049ae829fa70863c1" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Fri Oct 11 12:52:56 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 11 12:52:56 2019 +0000" }, "message": "Merge \"doc: Misc syntax and spelling fixes\" into integration" }, { "commit": "be653a6940b6c7bf3c0c6b7049ae829fa70863c1", "tree": "e0f14828750f595ee14a7ad836b8a56deea252f4", "parents": [ "6f0c77f0c7c224b0e4be2aaf3cfedcbdcba9a144" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Fri Oct 04 16:17:46 2019 +0000" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Fri Oct 11 12:39:06 2019 +0000" }, "message": "doc: Misc syntax and spelling fixes\n\nTidying up a few Sphinx warnings that had built-up over time.\nNone of these are critical but it cleans up the Sphinx output.\n\nAt the same time, fixing some spelling errors that were detected.\n\nChange-Id: I38209e235481eed287f8008c6de9dedd6b12ab2e\nSigned-off-by: Paul Beesley \u003cpaul.beesley@arm.com\u003e\n" }, { "commit": "89632e6aeba8414c1901eecb5d885363c73448f0", "tree": "54d6d0ad8ff0f1555aa7503f36f44cc1f678df9d", "parents": [ "6f0c77f0c7c224b0e4be2aaf3cfedcbdcba9a144" ], "author": { "name": "Balint Dobszay", "email": "balint.dobszay@arm.com", "time": "Fri Oct 11 14:01:43 2019 +0200" }, "committer": { "name": "Balint Dobszay", "email": "balint.dobszay@arm.com", "time": "Fri Oct 11 14:12:24 2019 +0200" }, "message": "Replace deprecated __ASSEMBLY__ macro with __ASSEMBLER__\n\nChange-Id: I497072575231730a216220f84a6d349a48eaf5e3\nSigned-off-by: Balint Dobszay \u003cbalint.dobszay@arm.com\u003e\n" }, { "commit": "6f0c77f0c7c224b0e4be2aaf3cfedcbdcba9a144", "tree": "e13cae4fee0d02aa5b247b3e65fabcf0c4b80b72", "parents": [ "f8e3340c0e3496a9d5fd685e77870583a1942fdd", "76cf653b8a080029a0376d714b964f4c64da94f7" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Wed Oct 09 16:04:19 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 09 16:04:19 2019 +0000" }, "message": "Merge \"doc: Formatting fixes for readme.rst\" into integration" }, { "commit": "76cf653b8a080029a0376d714b964f4c64da94f7", "tree": "e13cae4fee0d02aa5b247b3e65fabcf0c4b80b72", "parents": [ "f8e3340c0e3496a9d5fd685e77870583a1942fdd" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Wed Oct 09 15:37:59 2019 +0000" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Wed Oct 09 15:37:59 2019 +0000" }, "message": "doc: Formatting fixes for readme.rst\n\nThe readme.rst file in the project root is the front-page that\nis displayed on Github and if viewing the TF-A repository on\ngit.trustedfirmware.org in the \"about\" view. It now contains a\nsmall amount of stub content, and directs readers to the\nReadTheDocs documentation via trustedfirmware.org/docs/tf-a.\n\nThe Github renderer is displaying the content fine but the cgit\nviewer displays some \"backlink\" errors because some content\nsubstitutions were left in place (terms surrounded by pipe\nsymbols), e.g. |TF-A|.\n\nThis patch removes those substitutions, that are not supported\nby cgit, and also updates one heading to clarify where to find\nthe new docs.\n\nChange-Id: I358451df45b8c99975ba0b6db8ea61253a10560d\nSigned-off-by: Paul Beesley \u003cpaul.beesley@arm.com\u003e\n" }, { "commit": "f8e3340c0e3496a9d5fd685e77870583a1942fdd", "tree": "91a0c5ca12e51f47446fab3d2e4d77a6d469f0fc", "parents": [ "4fdad60c34549adb0a420e826394286d1d983df3", "862c764ada876aa1be24bdef00656bcc386ebdca" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Wed Oct 09 13:51:22 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 09 13:51:22 2019 +0000" }, "message": "Merge changes from topic \"pb/readthedocs\" into integration\n\n* changes:\n doc: Add guide for building the docs locally\n doc: De-duplicate readme and license files\n doc: Convert internal links to RST format\n" }, { "commit": "862c764ada876aa1be24bdef00656bcc386ebdca", "tree": "91a0c5ca12e51f47446fab3d2e4d77a6d469f0fc", "parents": [ "8cc36aec9122305f3537fbaa369d0c72ed324314" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Mon Oct 07 10:04:48 2019 +0000" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Wed Oct 09 13:47:38 2019 +0000" }, "message": "doc: Add guide for building the docs locally\n\nThis new page contains instructions for doing a local\nbuild of the documentation, plus information on the environment\nsetup that needs to be done beforehand.\n\nChange-Id: If563145ab40639cabbe25d0f62759981a33692c6\nSigned-off-by: Paul Beesley \u003cpaul.beesley@arm.com\u003e\n" }, { "commit": "8cc36aec9122305f3537fbaa369d0c72ed324314", "tree": "acf533f96317e3cfec65f7a700d04c578f796609", "parents": [ "347609510e30f5cc3f33beaad3cf085e8296b883" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Mon Sep 23 15:40:21 2019 +0000" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Tue Oct 08 16:36:15 2019 +0000" }, "message": "doc: De-duplicate readme and license files\n\nThe readme.rst and license.rst files in the project root overlap\nwith the index.rst and license.rst files in the docs/ folder. We\nneed to use the latter when building the documentation, as Sphinx\nrequires all included files to be under a common root. However,\nthe files in the root are currently used by the cgit and Github\nviewers.\n\nUsing symlinks in Git presents some difficulties so the best\ncourse of action is likely to leave these files but in stub form.\n\nThe license.rst file in the root will simply tell the reader to\nrefer to docs/license.rst.\n\nThe readme.rst file will contain a small amount of content that\nis derived from the docs/index.rst file, so that the Github main\npage will have something valid to show, but it will also contain\na link to the full documentation on ReadTheDocs.\n\nChange-Id: I6dc46f08777e8d7ecb32ca7afc07a28486c9f77a\nSigned-off-by: Paul Beesley \u003cpaul.beesley@arm.com\u003e\n" }, { "commit": "347609510e30f5cc3f33beaad3cf085e8296b883", "tree": "62ad23464d73b66c256d75cc5e276445b35088ac", "parents": [ "4fdad60c34549adb0a420e826394286d1d983df3" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Fri Apr 12 14:19:42 2019 +0100" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Tue Oct 08 15:58:03 2019 +0000" }, "message": "doc: Convert internal links to RST format\n\nCurrently links between documents are using the format:\n\n\u003cpath/to/\u003e\u003cfilename\u003e.rst\n\nThis was required for services like GitHub because they render each\ndocument in isolation - linking to another document is like linking\nto any other file, just provide the full path.\n\nHowever, with the new approach, the .rst files are only the raw\nsource for the documents. Once the documents have been rendered\nthe output is now in another format (HTML in our case) and so,\nwhen linking to another document, the link must point to the\nrendered version and not the .rst file.\n\nThe RST spec provides a few methods for linking between content.\nThe parent of this patch enabled the automatic creation of anchors\nfor document titles - we will use these anchors as the targets for\nour links. Additional anchors can be added by hand if needed, on\nsection and sub-section titles, for example.\n\nAn example of this new format, for a document with the title\n\"Firmware Design\" is :ref:`Firmware Design`.\n\nOne big advantage of this is that anchors are not dependent on\npaths. We can then move documents around, even between directories,\nwithout breaking any links between documents. Links will need to be\nupdated only if the title of a document changes.\n\nChange-Id: I9e2340a61dd424cbd8fd1ecc2dc166f460d81703\nSigned-off-by: Paul Beesley \u003cpaul.beesley@arm.com\u003e\n" }, { "commit": "4fdad60c34549adb0a420e826394286d1d983df3", "tree": "5648bbef55066939a2fe8434a75836fafd527566", "parents": [ "1d880258e1d43340e3d02bbee0a3b248ad8605b1", "e43ed98b801b8d6583d6854cd57d4beec9f314de" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 08 12:59:24 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 08 12:59:24 2019 +0000" }, "message": "Merge \"doc: Add more missing platforms\" into integration" }, { "commit": "1d880258e1d43340e3d02bbee0a3b248ad8605b1", "tree": "b82d07e8b695ee709ca3030847409d4c25e1677f", "parents": [ "80003d86a60272ef82b8bca3c71ee358222b825b", "9d811b856ec1d10a1285aa2c43c3e1f3a411d54b" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 08 12:58:48 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 08 12:58:48 2019 +0000" }, "message": "Merge \"delay: correct timeout_init_us()\" into integration" }, { "commit": "38d5e150edc82570e1a3e9dc2e95dce96e6fd94e", "tree": "05ab416d8306f82af472ba91434cd36f9433a526", "parents": [ "80003d86a60272ef82b8bca3c71ee358222b825b" ], "author": { "name": "Avinash Mehta", "email": "avinash.mehta@arm.com", "time": "Tue Oct 08 12:09:04 2019 +0100" }, "committer": { "name": "Avinash Mehta", "email": "avinash.mehta@arm.com", "time": "Tue Oct 08 13:58:25 2019 +0100" }, "message": "Correct UART PL011 initialization calculation\n\nCurrently for Armv7 plaforms the quotient calculated in pl011\nuart init code is moved to register r1.\n\nThis patch moves the quotient to register r2 as done for other\nplatforms in the udiv instruction. Value of register r2 is then\nused to calculate the values for IBRD and FBRD register\n\nChange-Id: Ie6622f9f0e6d634378b471df5d02823b492c8a24\nSigned-off-by: Avinash Mehta \u003cavinash.mehta@arm.com\u003e\n" }, { "commit": "9d811b856ec1d10a1285aa2c43c3e1f3a411d54b", "tree": "b82d07e8b695ee709ca3030847409d4c25e1677f", "parents": [ "80003d86a60272ef82b8bca3c71ee358222b825b" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Oct 08 11:13:06 2019 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Oct 08 11:13:06 2019 +0200" }, "message": "delay: correct timeout_init_us()\n\nThe function has to use read_cntpct_el0() to update the counter, and not\nread_cntfrq_el0().\n\nChange-Id: I9c676466e784c3122e9ffc2d87e66708797086e7\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "e43ed98b801b8d6583d6854cd57d4beec9f314de", "tree": "16772a8a928503685c6210e417c6b0805e10f124", "parents": [ "80003d86a60272ef82b8bca3c71ee358222b825b" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Fri Oct 04 10:37:48 2019 +0000" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Mon Oct 07 12:24:25 2019 +0000" }, "message": "doc: Add more missing platforms\n\nAdd meson-g12a, qemu-sbsa and rpi4 to the documentation index so\nthat they will have their docs rendered and integrated into the\ntable of contents.\n\nChange-Id: Id972bf2fee67312dd7bff29f92bea67842e62431\nSigned-off-by: Paul Beesley \u003cpaul.beesley@arm.com\u003e\n" }, { "commit": "80003d86a60272ef82b8bca3c71ee358222b825b", "tree": "66e7fabd4dbde3bfa8f36ec0febb96d205752972", "parents": [ "25792ce44332e7d043db2cc2451eb57fb5db7b09", "2a7adf2567aa103ced4a9a9b3ef8344935716d25" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Oct 07 12:06:08 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 07 12:06:08 2019 +0000" }, "message": "Merge \"Explicitly disable the SPME bit in MDCR_EL3\" into integration" }, { "commit": "25792ce44332e7d043db2cc2451eb57fb5db7b09", "tree": "214c8a8f404c81a11638466d4e8b8827c510d2e2", "parents": [ "5b567758bb880d3a4e4db1498cf903a14b504ce2", "80942622fe760c23f0a677eac48aff37e90f4251" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Oct 07 12:05:26 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 07 12:05:26 2019 +0000" }, "message": "Merge \"Neoverse N1 Errata Workaround 1542419\" into integration" }, { "commit": "5b567758bb880d3a4e4db1498cf903a14b504ce2", "tree": "1f7f2dfdf62019c49009e3f52e5d85dc04b437b2", "parents": [ "81da28c2096ffbe3d8f077cf80e0ccc23f2a69db", "c97cba4ea44910df1f7b1af5dba79013fb44c383" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Oct 07 11:43:32 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 07 11:43:32 2019 +0000" }, "message": "Merge \"Fix the CAS spinlock implementation\" into integration" }, { "commit": "2a7adf2567aa103ced4a9a9b3ef8344935716d25", "tree": "5ce3f4cda4573251a7208f8c46f909bbd757d9b4", "parents": [ "cf9319f46a1dd17c842297a8aeb68059f6f3a06f" ], "author": { "name": "Petre-Ionut Tudor", "email": "petre-ionut.tudor@arm.com", "time": "Thu Oct 03 17:09:08 2019 +0100" }, "committer": { "name": "Petre-Ionut Tudor", "email": "petre-ionut.tudor@arm.com", "time": "Mon Oct 07 11:50:07 2019 +0100" }, "message": "Explicitly disable the SPME bit in MDCR_EL3\n\nCurrently the MDCR_EL3 initialisation implicitly disables\nMDCR_EL3.SPME by using mov_imm.\n\nThis patch makes the SPME bit more visible by explicitly\ndisabling it and documenting its use in different versions\nof the architecture.\n\nSigned-off-by: Petre-Ionut Tudor \u003cpetre-ionut.tudor@arm.com\u003e\nChange-Id: I221fdf314f01622f46ac5aa43388f59fa17a29b3\n" }, { "commit": "80942622fe760c23f0a677eac48aff37e90f4251", "tree": "7950a0f8c0d417e2f3519ccfb136ec48ca9b9717", "parents": [ "5f38b5362cff958225c6ad9b3d45a56b3d613fbf" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Tue Aug 20 15:51:24 2019 -0500" }, "committer": { "name": "Deepika Bhavnani", "email": "deepika.bhavnani@arm.com", "time": "Fri Oct 04 19:31:24 2019 +0300" }, "message": "Neoverse N1 Errata Workaround 1542419\n\nCoherent I-cache is causing a prefetch violation where when the core\nexecutes an instruction that has recently been modified, the core might\nfetch a stale instruction which violates the ordering of instruction\nfetches.\n\nThe workaround includes an instruction sequence to implementation\ndefined registers to trap all EL0 IC IVAU instructions to EL3 and a trap\nhandler to execute a TLB inner-shareable invalidation to an arbitrary\naddress followed by a DSB.\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6\n" }, { "commit": "81da28c2096ffbe3d8f077cf80e0ccc23f2a69db", "tree": "53471c214343cd22e8edb4dfb98b145365ac4a0d", "parents": [ "cf9319f46a1dd17c842297a8aeb68059f6f3a06f", "0711ee5cbc5645b55de1a751bd52dc8ce02ae037" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Oct 04 13:47:40 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 04 13:47:40 2019 +0000" }, "message": "Merge \"delay: timeout detection support\" into integration" }, { "commit": "c97cba4ea44910df1f7b1af5dba79013fb44c383", "tree": "9d2965a2b9610413dea548a95e2f5094fc84b6e8", "parents": [ "ace23683beb81354d6edbc61c087ab8c384d0631" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 25 14:03:41 2019 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Oct 04 10:19:35 2019 +0200" }, "message": "Fix the CAS spinlock implementation\n\nMake the spinlock implementation use ARMv8.1-LSE CAS instruction based\non a platform build option. The CAS-based implementation used to be\nunconditionally selected for all ARM8.1+ platforms.\n\nThe previous CAS spinlock implementation had a bug wherein the spin_unlock()\nimplementation had an `sev` after `stlr` which is not sufficient. A dsb is\nneeded to ensure that the stlr completes prior to the sev. Having a dsb is\nheavyweight and a better solution would be to use load exclusive semantics\nto monitor the lock and wake up from wfe when a store happens to the lock.\nThe patch implements the same.\n\nChange-Id: I5283ce4a889376e4cc01d1b9d09afa8229a2e522\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\n" }, { "commit": "0711ee5cbc5645b55de1a751bd52dc8ce02ae037", "tree": "53471c214343cd22e8edb4dfb98b145365ac4a0d", "parents": [ "cf9319f46a1dd17c842297a8aeb68059f6f3a06f" ], "author": { "name": "Lionel Debieve", "email": "lionel.debieve@st.com", "time": "Tue Sep 24 16:59:56 2019 +0200" }, "committer": { "name": "Lionel Debieve", "email": "lionel.debieve@st.com", "time": "Thu Oct 03 18:57:25 2019 +0000" }, "message": "delay: timeout detection support\n\nIntroduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT.\n\ntimeout_init_us(some_timeout_us); returns a reference to detect\ntimeout for the provided microsecond delay value from current time.\n\ntimeout_elapsed(reference) return true/false whether the reference\ntimeout is elapsed.\n\nCherry picked from OP-TEE implementation [1].\n [1] commit 33d30a74502b (\"core: timeout detection support\")\n\nMinor:\n- Remove stm32mp platform duplicated implementation.\n- Add new include in marvell ble.mk\n\nSigned-off-by: Etienne Carriere \u003cetienne.carriere@linaro.org\u003e\nSigned-off-by: Lionel Debieve \u003clionel.debieve@st.com\u003e\nChange-Id: Iaef6d43c11a2e6992fb48efdc674a0552755ad9c\n" }, { "commit": "cf9319f46a1dd17c842297a8aeb68059f6f3a06f", "tree": "cee2a7e8a5904cda825ffb7d9b11ec97086d2c11", "parents": [ "8326aad7be972a66e6fbcc4b1128929fec0cb242", "530ceda57288aa931d0c8ba7b3066340d587cc9b" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Oct 03 16:22:41 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 03 16:22:41 2019 +0000" }, "message": "Merge \"TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U\" into integration" }, { "commit": "530ceda57288aa931d0c8ba7b3066340d587cc9b", "tree": "2dce6c07bcf6675c39b9455481f275f36f83b7e4", "parents": [ "ace23683beb81354d6edbc61c087ab8c384d0631" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Oct 01 13:58:23 2019 +0100" }, "committer": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Thu Oct 03 14:43:55 2019 +0100" }, "message": "TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U\n\nThis patch adds support for ARMv8.3-PAuth in BL1 SMC calls and\nBL2U image for firmware updates by programming APIAKey_EL1 registers\nand enabling Pointer Authentication in EL3 and EL1 respectively.\n\nChange-Id: I875d952aba8242caf74fb5f4f2d2af6f0c768c08\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "8326aad7be972a66e6fbcc4b1128929fec0cb242", "tree": "424d6a1b5bcd1320b0b6971b3f52253fc0975277", "parents": [ "2d35bc1386ee80904be0df7dd5b3eb958dc685e2", "78f02ae2968dd0a78e0e686f8cf0886fa296f4eb" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Oct 03 13:43:51 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 03 13:43:51 2019 +0000" }, "message": "Merge \"Introducing support for Cortex-A65AE\" into integration" }, { "commit": "78f02ae2968dd0a78e0e686f8cf0886fa296f4eb", "tree": "424d6a1b5bcd1320b0b6971b3f52253fc0975277", "parents": [ "2d35bc1386ee80904be0df7dd5b3eb958dc685e2" ], "author": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Mon Jul 22 14:36:30 2019 +0200" }, "committer": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Thu Oct 03 15:38:31 2019 +0200" }, "message": "Introducing support for Cortex-A65AE\n\nChange-Id: I1ea2bf088f1e001cdbd377cbfb7c6a2866af0422\nSigned-off-by: Imre Kis \u003cimre.kis@arm.com\u003e\n" }, { "commit": "2d35bc1386ee80904be0df7dd5b3eb958dc685e2", "tree": "46d9234a1d8608967f1e522d3a3a8f5badb1010a", "parents": [ "34c4f86a627f79b1f827e65d46675fca21987b62", "243b61d15aaa59794e73769de7be64f02223cfad" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Oct 03 13:32:45 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 03 13:32:45 2019 +0000" }, "message": "Merge changes from topic \"stm32mp_corrections_w40\" into integration\n\n* changes:\n gpio: stm32_gpio: do not mix error code types\n fdts: stm32mp1: move FDCAN to PLL4_R\n mmc: increase delay between ACMD41 retries\n crypto: stm32_hash: align stm32_hash_update() prototype\n" }, { "commit": "34c4f86a627f79b1f827e65d46675fca21987b62", "tree": "b575bb06fb1477d7f7f14154649b76ce1aad5166", "parents": [ "efcf951f6113d1ee0f47af883130512edaeaeeeb", "0a12302c3ff290fd5925313d7ba834209eeed671" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Oct 03 13:32:13 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 03 13:32:13 2019 +0000" }, "message": "Merge \"Add missing support for BL2_AT_EL3 in XIP memory\" into integration" }, { "commit": "efcf951f6113d1ee0f47af883130512edaeaeeeb", "tree": "5fa778384c8f9920a6d06b447189e9d2d3e3864e", "parents": [ "82d8d4ab59986b2747fd329405c57e21dcbf6055", "fa405e3b82ae9ed764e6f37745e612c86a8be183" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Oct 03 13:23:37 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 03 13:23:37 2019 +0000" }, "message": "Merge changes from topic \"qemu_sbsa\" into integration\n\n* changes:\n qemu/qemu_sbsa: Adding memory mapping for both FLASH0/FLASH1\n qemu/qemu_sbsa: Adding Qemu SBSA platform\n" }, { "commit": "82d8d4ab59986b2747fd329405c57e21dcbf6055", "tree": "aa08628b61f562af63786da3ed9c98605be7a168", "parents": [ "251b2643fc932a776466881d79f144daa5e905ad", "f25ea7e3ac3626ded4b89120376b2e5ce959f6d3" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Oct 03 10:30:40 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 03 10:30:40 2019 +0000" }, "message": "Merge changes I0355e084,I6a6dd1c0 into integration\n\n* changes:\n mediatek: mt8183: add EMI MPU driver for DRAM protection\n mediatek: mt8183: add DEVAPC driver to control protection\n" }, { "commit": "251b2643fc932a776466881d79f144daa5e905ad", "tree": "f2696dade90cd98c32170d8bfa8149eed3c0bceb", "parents": [ "b81167d318f944d0687860e527c9869977b79515", "59ffec157ca8d675165f122c901c1ff198a810bc" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Oct 03 10:22:06 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 03 10:22:06 2019 +0000" }, "message": "Merge \"a5ds: Add handler for when user tries to switch off secondary cores\" into integration" }, { "commit": "243b61d15aaa59794e73769de7be64f02223cfad", "tree": "ba4c18f43411cad01c2a6f4abb67195a3994e8a0", "parents": [ "2dc9fe70da6788ff69856ed247b10a59173431c3" ], "author": { "name": "Nicolas Le Bayon", "email": "nicolas.le.bayon@st.com", "time": "Wed Sep 11 15:58:31 2019 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Oct 03 11:17:48 2019 +0200" }, "message": "gpio: stm32_gpio: do not mix error code types\n\nChange-Id: I84f8a99be2dcdf7c51fbecdb324df8e2f32cc855\nSigned-off-by: Nicolas Le Bayon \u003cnicolas.le.bayon@st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "2dc9fe70da6788ff69856ed247b10a59173431c3", "tree": "bf9ccdb0c877be6a4d43a097d19f42ad811a21c5", "parents": [ "57f4b6f83974b17e0aae04e17f9d95a5659ac88b" ], "author": { "name": "Antonio Borneo", "email": "antonio.borneo@st.com", "time": "Mon Jul 29 14:46:16 2019 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Oct 03 11:17:40 2019 +0200" }, "message": "fdts: stm32mp1: move FDCAN to PLL4_R\n\nLTDC modifies the clock frequency to adapt it to the display. Such\nfrequency change is not detected by the FDCAN driver that instead\ncaches the value at probe and pretends to use it later.\n\nThis change fixes the issue by moving the FDCAN to PLL4_R,\nleaving the LTDC alone on PLL4_Q.\n\nSigned-off-by: Antonio Borneo \u003cantonio.borneo@st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: I8230868b2b5fd6deb6e3f9dc3911030d8d484c58\n" }, { "commit": "57f4b6f83974b17e0aae04e17f9d95a5659ac88b", "tree": "635e10da897184da0a5f899ac7608ddb39c64ef9", "parents": [ "19e2af7977937b13513f448e0e162df9847b4068" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Aug 16 16:49:41 2019 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Oct 03 11:17:31 2019 +0200" }, "message": "mmc: increase delay between ACMD41 retries\n\nIn the SD Specification, Power Up Diagram of Card figure, the Timeout\nvalue for initialization process (ACMD41 command retries) is 1 second.\nAlign to match MMC cards (in mmc_send_op_cond()) and Linux kernel code,\nand set the delay between ACMD41 command retries to 10ms.\n\nChange-Id: I2e07cb9944e7d7b72f2d4b13e0505e6751458091\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "19e2af7977937b13513f448e0e162df9847b4068", "tree": "e713625060b9f37d95aca763bb02c4ebb1be2e29", "parents": [ "5f38b5362cff958225c6ad9b3d45a56b3d613fbf" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Oct 02 16:33:41 2019 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Oct 03 11:17:15 2019 +0200" }, "message": "crypto: stm32_hash: align stm32_hash_update() prototype\n\nUse size_t for length parameter in header file, as in .c file.\n\nChange-Id: I310f2a6159cde1c069b4f814f6558c2488c203ec\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "59ffec157ca8d675165f122c901c1ff198a810bc", "tree": "7b98f70c616bab85b3698ebd3f1b8bb4587a83cf", "parents": [ "ace23683beb81354d6edbc61c087ab8c384d0631" ], "author": { "name": "Usama Arif", "email": "usama.arif@arm.com", "time": "Thu Sep 26 16:07:53 2019 +0100" }, "committer": { "name": "Usama Arif", "email": "usama.arif@arm.com", "time": "Thu Oct 03 10:09:04 2019 +0100" }, "message": "a5ds: Add handler for when user tries to switch off secondary cores\n\na5ds only has always-on power domain and there is no power control\npresent. However, without the pwr_domain_off handler, the kernel\npanics when the user will try to switch off secondary cores. The\na5ds_pwr_domain_off handler will prevent kernel from crashing,\ni.e. the kernel will attempt but fail to shut down the secondary CPUs\nif the user tries to switch them offline.\n\nChange-Id: I3c2239a1b6f035113ddbdda063c8495000cbe30c\nSigned-off-by: Usama Arif \u003cusama.arif@arm.com\u003e\n" }, { "commit": "f25ea7e3ac3626ded4b89120376b2e5ce959f6d3", "tree": "428df814c546849d8f46f46dbb4428c2a4c5d9f4", "parents": [ "1b0174efdb9f7f2a998864a015b16980a19e7803" ], "author": { "name": "kenny liang", "email": "kenny.liang@mediatek.com", "time": "Fri Aug 23 15:50:58 2019 +0800" }, "committer": { "name": "kenny liang", "email": "kenny.liang@mediatek.com", "time": "Thu Oct 03 10:46:09 2019 +0800" }, "message": "mediatek: mt8183: add EMI MPU driver for DRAM protection\n\nAdd EMI MPU driver for DRAM protection.\n\nSigned-off-by: kenny liang \u003ckenny.liang@mediatek.com\u003e\nChange-Id: I0355e084184b5396ad8ac99fff6ef9d050fb5e96\n" }, { "commit": "1b0174efdb9f7f2a998864a015b16980a19e7803", "tree": "a813b945c379ffb18c3b803a7af824b3523e91eb", "parents": [ "5f38b5362cff958225c6ad9b3d45a56b3d613fbf" ], "author": { "name": "kenny liang", "email": "kenny.liang@mediatek.com", "time": "Fri Aug 23 10:23:34 2019 +0800" }, "committer": { "name": "kenny liang", "email": "kenny.liang@mediatek.com", "time": "Thu Oct 03 10:45:16 2019 +0800" }, "message": "mediatek: mt8183: add DEVAPC driver to control protection\n\nAdd DEVAPC driver to control protection.\n\nSigned-off-by: kenny liang \u003ckenny.liang@mediatek.com\u003e\nChange-Id: I6a6dd1c0bffa372b6df2cb604ca5e02eabbb9d26\n" }, { "commit": "b81167d318f944d0687860e527c9869977b79515", "tree": "bbd31955d0b50cb0d473a9d4f80a2de078f45d04", "parents": [ "5f38b5362cff958225c6ad9b3d45a56b3d613fbf", "6ad216dca5e388f9aa1518a20a81c836c7eb2d21" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Oct 02 20:12:37 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 02 20:12:37 2019 +0000" }, "message": "Merge \"Introducing support for Cortex-A65\" into integration" }, { "commit": "6ad216dca5e388f9aa1518a20a81c836c7eb2d21", "tree": "bbd31955d0b50cb0d473a9d4f80a2de078f45d04", "parents": [ "5f38b5362cff958225c6ad9b3d45a56b3d613fbf" ], "author": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Thu Jul 18 14:30:03 2019 +0200" }, "committer": { "name": "Imre Kis", "email": "imre.kis@arm.com", "time": "Wed Oct 02 18:12:28 2019 +0200" }, "message": "Introducing support for Cortex-A65\n\nChange-Id: I645442d52a295706948e2cac88c36c1a3cb0bc47\nSigned-off-by: Imre Kis \u003cimre.kis@arm.com\u003e\n" }, { "commit": "0a12302c3ff290fd5925313d7ba834209eeed671", "tree": "ad6721a2d2d6264b982a1e877b7120d3f3338359", "parents": [ "c5235cae8e0c7c70ae9b4a8c41d77db17c885418" ], "author": { "name": "Lionel Debieve", "email": "lionel.debieve@st.com", "time": "Mon May 27 09:32:00 2019 +0200" }, "committer": { "name": "Lionel Debieve", "email": "lionel.debieve@st.com", "time": "Wed Oct 02 09:06:39 2019 +0200" }, "message": "Add missing support for BL2_AT_EL3 in XIP memory\n\nAdd the missing flag for aarch32 XIP memory mode. It was\npreviously added in aarch64 only.\nMinor: Correct the aarch64 missing flag.\n\nSigned-off-by: Lionel Debieve \u003clionel.debieve@st.com\u003e\nChange-Id: Iac0a7581a1fd580aececa75f97deb894858f776f\n" }, { "commit": "5f38b5362cff958225c6ad9b3d45a56b3d613fbf", "tree": "ad4fb9f4473caa0fb37c036dbb9c886dfc8950a6", "parents": [ "3bdade5d33d4abc50e6b016343a33030fd67e993", "b48691eda0f414654f94d871febd1035add1d22f" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Oct 02 06:41:05 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 02 06:41:05 2019 +0000" }, "message": "Merge \"doc: Fix GCC version to 8.3-2019.03\" into integration" }, { "commit": "b48691eda0f414654f94d871febd1035add1d22f", "tree": "ad4fb9f4473caa0fb37c036dbb9c886dfc8950a6", "parents": [ "3bdade5d33d4abc50e6b016343a33030fd67e993" ], "author": { "name": "Louis Mayencourt", "email": "louis.mayencourt@arm.com", "time": "Thu Sep 26 11:29:21 2019 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Oct 02 06:38:33 2019 +0000" }, "message": "doc: Fix GCC version to 8.3-2019.03\n\nChange-Id: I3b866e927d93f4b690aa4891940fc8afabf4146e\nSigned-off-by: Louis Mayencourt \u003clouis.mayencourt@arm.com\u003e\n" }, { "commit": "3bdade5d33d4abc50e6b016343a33030fd67e993", "tree": "9fb676cfceb750ab84f7355fdf9780eb23e741eb", "parents": [ "2f625c5e5c17ec4d9702c0910df8b1cbfdf6a175", "a4668c36f1fca75bce99cb706ba7c27e0c16454d" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Tue Oct 01 20:15:23 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 01 20:15:23 2019 +0000" }, "message": "Merge \"Cortex_hercules: Add support for Hercules-AE\" into integration" }, { "commit": "2f625c5e5c17ec4d9702c0910df8b1cbfdf6a175", "tree": "3d806b81d9c62e545e2442e163076061e56503f2", "parents": [ "c5235cae8e0c7c70ae9b4a8c41d77db17c885418", "35010bb80390bca016110cced25b41ad2b355919" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Oct 01 15:49:54 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 01 15:49:54 2019 +0000" }, "message": "Merge \"doc: Migrate to Linaro release 19.06\" into integration" }, { "commit": "fa405e3b82ae9ed764e6f37745e612c86a8be183", "tree": "3b676afb988b8d4656ae55178de1b0ae4a70f726", "parents": [ "558a6f444d54f419e90ead976bf28cf25797f4e4" ], "author": { "name": "Radoslaw Biernacki", "email": "radoslaw.biernacki@linaro.org", "time": "Thu Jun 07 20:14:36 2018 +0200" }, "committer": { "name": "Radoslaw Biernacki", "email": "rad@semihalf.com", "time": "Tue Oct 01 17:24:06 2019 +0200" }, "message": "qemu/qemu_sbsa: Adding memory mapping for both FLASH0/FLASH1\n\nThis patch adds mapping for secure FLASH0 for qemu/virt and\nqemu/qemu_sbsa platforms. This change is targeted for sbsa but since both\nplatforms share common code, changes in common defines was necessary.\n\nFor qemu_sbsa, this patch adds necessary mapping in order to boot without\nsemi-hosting from secure FLASH0. EFI need to stay in FLASH1 (share it with\nvariables) since it need to \"run in place\" in non secure domain. Changes\nfor this are under RFC at edk2-platforms mailing list:\nhttps://patches.linaro.org/patch/171327/\n(edk2-platforms/Platform/Qemu/SbsaQemu/SbsaQemu.dsc).\n\nIn docs qemu/virt is described as using semi-hosting, therefore this change\nshould be orthogonal to existing assumptions while giving possibility to\nstore both bl1 and fip in FLASH0 at some point (additional changes required\nfor that).\n\nSigned-off-by: Radoslaw Biernacki \u003cradoslaw.biernacki@linaro.org\u003e\nChange-Id: I782bc3637c91c01eaee680b3c5c408e24b4b6e28\n" }, { "commit": "558a6f444d54f419e90ead976bf28cf25797f4e4", "tree": "e255b03407f300390cbf1a4eff6bc3f99628cf53", "parents": [ "c5235cae8e0c7c70ae9b4a8c41d77db17c885418" ], "author": { "name": "Radoslaw Biernacki", "email": "radoslaw.biernacki@linaro.org", "time": "Thu May 17 22:52:49 2018 +0200" }, "committer": { "name": "Radoslaw Biernacki", "email": "rad@semihalf.com", "time": "Tue Oct 01 17:23:56 2019 +0200" }, "message": "qemu/qemu_sbsa: Adding Qemu SBSA platform\n\nThis patch introduces Qemu SBSA platform.\nBoth platform specific files where copied from qemu/qemu with changes for\nDRAM base above 32bit and removal of ARMv7 conditional defines/code.\nDocumentation is aligned to rest of SBSA patches along the series and\nplaned changes in edk2-platform repo.\n\nFixes ARM-software/tf-issues#602\n\nSigned-off-by: Radoslaw Biernacki \u003cradoslaw.biernacki@linaro.org\u003e\nChange-Id: I8ebc34eedb2268365e479ef05654b2df1b99128c\n" }, { "commit": "35010bb80390bca016110cced25b41ad2b355919", "tree": "526e693b3923e92822b8506a492aacd61c54230e", "parents": [ "6129e9a643274e658a0e6f5428ad976676c7bb7a" ], "author": { "name": "zelalem-aweke", "email": "zelalem.aweke@arm.com", "time": "Fri Sep 20 11:15:20 2019 -0500" }, "committer": { "name": "zelalem-aweke", "email": "zelalem.aweke@arm.com", "time": "Mon Sep 30 12:15:16 2019 -0500" }, "message": "doc: Migrate to Linaro release 19.06\n\n- Updated Linaro release version number to 19.06\n- Updated links to Linaro instructions and releases\n- Removed the Linaro old releases link\n\nSigned-off-by: zelalem-aweke \u003czelalem.aweke@arm.com\u003e\nChange-Id: Ib786728106961e89182b42183e7b889f6fc74190\n" }, { "commit": "a4668c36f1fca75bce99cb706ba7c27e0c16454d", "tree": "4dd7fd7ce3004d9edc775f8ec81a3830ea47632d", "parents": [ "ace23683beb81354d6edbc61c087ab8c384d0631" ], "author": { "name": "Artsem Artsemenka", "email": "artsem.artsemenka@arm.com", "time": "Mon Sep 16 15:11:21 2019 +0100" }, "committer": { "name": "Artsem Artsemenka", "email": "artsem.artsemenka@arm.com", "time": "Mon Sep 30 12:55:31 2019 +0100" }, "message": "Cortex_hercules: Add support for Hercules-AE\n\nNot tested on FVP Model.\n\nChange-Id: Iedebc5c1fbc7ea577e94142b7feafa5546f1f4f9\nSigned-off-by: Artsem Artsemenka \u003cartsem.artsemenka@arm.com\u003e\n" }, { "commit": "c5235cae8e0c7c70ae9b4a8c41d77db17c885418", "tree": "e692795235ae210a47a0cdab5b968fb7727f1631", "parents": [ "ace23683beb81354d6edbc61c087ab8c384d0631", "c3e8b0be9bde36d220beea5d0452ecd04dcd94c6" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Sep 27 10:55:15 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 27 10:55:15 2019 +0000" }, "message": "Merge \"AArch32: Disable Secure Cycle Counter\" into integration" }, { "commit": "ace23683beb81354d6edbc61c087ab8c384d0631", "tree": "7d38b9f16a08d4ff65dfe9017abf72f4574c2f19", "parents": [ "32d514e5c685bf7d425629a6021d4f2f20df159c", "4bdb1a7a6a1325343b0f0c375b43e9b874e31fca" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Sep 27 09:54:27 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 27 09:54:27 2019 +0000" }, "message": "Merge changes from topic \"ld/stm32-authentication\" into integration\n\n* changes:\n stm32mp1: add authentication support for stm32image\n bsec: move bsec_mode_is_closed_device() service to platform\n crypto: stm32_hash: Add HASH driver\n" }, { "commit": "32d514e5c685bf7d425629a6021d4f2f20df159c", "tree": "a926538c5581d89c2e8ec4498731dcabca09459c", "parents": [ "f7fa5289176068d0d54cd0b218eae3394b47f8c1", "f1e0f15262cf3f19bf2edd93a0d70d6903e2733c" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Sep 27 09:54:07 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 27 09:54:07 2019 +0000" }, "message": "Merge \"doc: Fix platform port inclusion\" into integration" }, { "commit": "f7fa5289176068d0d54cd0b218eae3394b47f8c1", "tree": "684affc71a92802dd7c831e50c2b08e023710840", "parents": [ "757d904b2f5ddde6e1537d04e6d1b87f541ba737", "cdb8c52f922b5c4d972e398a72ac89d100937507" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Sep 27 09:53:40 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 27 09:53:40 2019 +0000" }, "message": "Merge changes from topic \"amlogic-g12a\" into integration\n\n* changes:\n amlogic: g12a: Add support for the S905X2 (G12A) platform\n amlogic: makefile: Use PLAT variable when possible\n amlogic: sha_dma: Move register mappings to platform header\n" }, { "commit": "757d904b2f5ddde6e1537d04e6d1b87f541ba737", "tree": "39dc2df8a4ab19442dfb8e64f470a0446c8ccbd8", "parents": [ "1ec391932653b2ac452834ed3317ff3bd3cac82f", "ec885bacb247e9a88c0e21406bdf42821eb340c7" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Sep 27 09:49:23 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 27 09:49:23 2019 +0000" }, "message": "Merge changes from topic \"a5ds-multicore\" into integration\n\n* changes:\n a5ds: add multicore support\n a5ds: Hold the secondary cpus in pen rather than panic\n" }, { "commit": "1ec391932653b2ac452834ed3317ff3bd3cac82f", "tree": "abc4678a34759efde6421fbf213fc89abd22ef1a", "parents": [ "95982ffc98b8189209e307098f281c132715084a", "eb5f0ba41eaead241efad2bc1e0502211fdca93b" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Sep 27 09:49:05 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 27 09:49:05 2019 +0000" }, "message": "Merge \"GICv3 driver: Fix support for full SPI range\" into integration" }, { "commit": "95982ffc98b8189209e307098f281c132715084a", "tree": "a72dc50e0cadc37d5b0f7493e2b8be084e52e5d9", "parents": [ "17b0bb6cf53cd9cd904ac6551f3552bd884e8159", "019b03a3001a61f7d42fa70abee6c284f542b2d2" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Sep 27 09:46:59 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 27 09:46:59 2019 +0000" }, "message": "Merge \"Fix MTE support from causing unused variable warnings\" into integration" }, { "commit": "17b0bb6cf53cd9cd904ac6551f3552bd884e8159", "tree": "21da0d0594f14103f7f3baaeae50d017c09c13f9", "parents": [ "41bda863305eae92db2e4e18cd057797765d261c", "e0dea671dceebe935201f1c4796cac5774af152f" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Sep 27 09:45:42 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 27 09:45:42 2019 +0000" }, "message": "Merge changes from topic \"raspberry-pi-4-support\" into integration\n\n* changes:\n rpi4: Add initial documentation file\n rpi4: Add stdout-path to device tree\n rpi4: Add GIC maintenance interrupt to GIC DT node\n rpi4: Cleanup memory regions, move pens to first page\n rpi4: Reserve resident BL31 region from non-secure world\n rpi4: Amend DTB to advertise PSCI\n rpi4: Determine BL33 entry point at runtime\n rpi4: Accommodate \"armstub8.bin\" header at the beginning of BL31 image\n Add basic support for Raspberry Pi 4\n rpi3: Allow runtime determination of UART base clock rate\n FDT helper functions: Respect architecture in PSCI function IDs\n FDT helper functions: Add function documentation\n" }, { "commit": "41bda863305eae92db2e4e18cd057797765d261c", "tree": "4446d13e90dfb14e67abf7510e0eb8c9de1c74bc", "parents": [ "69ef7b7ffe66b64bdffee0a387774e7088022503", "6806cd2381901d424b40ba3f17d23f5ffa4ca57e" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Sep 27 09:42:37 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 27 09:42:37 2019 +0000" }, "message": "Merge changes from topic \"mp/giv3-discovery\" into integration\n\n* changes:\n Migrate ARM platforms to use the new GICv3 API\n Adding new optional PSCI hook pwr_domain_on_finish_late\n GICv3: Enable multi socket GIC redistributor frame discovery\n" }, { "commit": "c3e8b0be9bde36d220beea5d0452ecd04dcd94c6", "tree": "2f5efa0f2fc2f922e19abd9e1eadebc0c8eb8f85", "parents": [ "69ef7b7ffe66b64bdffee0a387774e7088022503" ], "author": { "name": "Alexei Fedorov", "email": "Alexei.Fedorov@arm.com", "time": "Tue Aug 20 15:22:44 2019 +0100" }, "committer": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Thu Sep 26 15:36:02 2019 +0000" }, "message": "AArch32: Disable Secure Cycle Counter\n\nThis patch changes implementation for disabling Secure Cycle\nCounter. For ARMv8.5 the counter gets disabled by setting\nSDCR.SCCD bit on CPU cold/warm boot. For the earlier\narchitectures PMCR register is saved/restored on secure\nworld entry/exit from/to Non-secure state, and cycle counting\ngets disabled by setting PMCR.DP bit.\nIn \u0027include\\aarch32\\arch.h\u0027 header file new\nARMv8.5-PMU related definitions were added.\n\nChange-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8\nSigned-off-by: Alexei Fedorov \u003cAlexei.Fedorov@arm.com\u003e\n" }, { "commit": "69ef7b7ffe66b64bdffee0a387774e7088022503", "tree": "976b35b009ee6f13cfcc0a00267b47de7f4b348e", "parents": [ "80a624d1a3d7e052df1c7848aa275f1ac09a743b", "deb330cb3837cddf251cea5d804634ad75d48c19" ], "author": { "name": "Paul Beesley", "email": "paul.beesley@arm.com", "time": "Thu Sep 26 13:40:38 2019 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 26 13:40:38 2019 +0000" }, "message": "Merge changes I0283fc2e,Ib476d024,Iada05f7c into integration\n\n* changes:\n hikey: fix to load FIP by partition table.\n hikey960: fix to load FIP by partition table\n drivers: partition: support different block size\n" }, { "commit": "cdb8c52f922b5c4d972e398a72ac89d100937507", "tree": "1b6e3a29a0970f53a9a7100ce671ae44bd353711", "parents": [ "edcadeb7b83b772ae1d9ff072a960ddf573befc2" ], "author": { "name": "Carlo Caione", "email": "ccaione@baylibre.com", "time": "Wed Sep 18 11:29:48 2019 +0100" }, "committer": { "name": "Carlo Caione", "email": "ccaione@baylibre.com", "time": "Thu Sep 26 09:27:45 2019 +0100" }, "message": "amlogic: g12a: Add support for the S905X2 (G12A) platform\n\nIntroduce the preliminary support for the Amlogic S905X2 (G12A) SoC.\n\nThis port is a minimal implementation of BL31 capable of booting\nmainline U-Boot and Linux. Tested on a SEI510 board.\n\nSigned-off-by: Carlo Caione \u003cccaione@baylibre.com\u003e\nChange-Id: Ife958f10e815a4530292c45446adb71239f3367f\n" }, { "commit": "6806cd2381901d424b40ba3f17d23f5ffa4ca57e", "tree": "08a0d98798ec86006bc97de914180dd3f56362cc", "parents": [ "10107707196d67731de57126b846169c5b29aac0" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Jun 10 16:54:36 2019 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Sep 25 22:06:49 2019 -0500" }, "message": "Migrate ARM platforms to use the new GICv3 API\n\nThis patch invokes the new function gicv3_rdistif_probe() in the\nARM platform specific gicv3 driver. Since this API modifies the\nshared GIC related data structure, it must be invoked coherently\nby using the platform specific pwr_domain_on_finish_late hook.\n\nChange-Id: I6efb17d5da61545a1c5a6641b8f58472b31e62a8\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\n" }, { "commit": "10107707196d67731de57126b846169c5b29aac0", "tree": "1e94f76e5c174cd6538a7750d0eaa5af1e7b72e6", "parents": [ "ec834925f3cb5cb3934010bbc8077293e610d2ac" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Aug 12 18:31:33 2019 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Sep 25 22:06:44 2019 -0500" }, "message": "Adding new optional PSCI hook pwr_domain_on_finish_late\n\nThis PSCI hook is similar to pwr_domain_on_finish but is\nguaranteed to be invoked with the respective core and cluster are\nparticipating in coherency. This will be necessary to safely invoke\nthe new GICv3 API which modifies shared GIC data structures concurrently.\n\nChange-Id: I8e54f05c9d4ef5712184c9c18ba45ac97a29eb7a\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\n" }, { "commit": "ec834925f3cb5cb3934010bbc8077293e610d2ac", "tree": "30bca110fff7c07459cc63c1a710ca3a8708b4aa", "parents": [ "6a7cbfd56837409b85c26df0206177e59fc95a79" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed May 15 18:25:41 2019 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Sep 25 22:01:28 2019 -0500" }, "message": "GICv3: Enable multi socket GIC redistributor frame discovery\n\nThis patch provides declaration and definition of new GICv3 driver\nAPI: gicv3_rdistif_probe().This function delegates the responsibility\nof discovering the corresponding Redistributor base frame to each CPU\nitself. It is a modified version of gicv3_rdistif_base_addrs_probe()\nand is executed by each CPU in the platform unlike the previous\napproach in which only the Primary CPU did the discovery of all the\nRedistributor frames for every CPU.\n\nThe flush operations as part of gicv3_driver_init() function are\nmade necessary even for platforms with WARMBOOT_ENABLE_DCACHE_EARLY\nbecause the GICv3 driver data structure contents are accessed by CPU\nwith D-Cache turned off during power down operations.\n\nChange-Id: I1833e81d3974b32a3e4a3df4766a33d070982268\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\n" } ], "next": "f1e0f15262cf3f19bf2edd93a0d70d6903e2733c" }