diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 07983a9..6b524c2 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -226,6 +226,9 @@
 -  ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76
    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
 
+-  ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
+
 DSU Errata Workarounds
 ----------------------
 
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h
index ed5f136..b66aeb8 100644
--- a/include/lib/cpus/aarch64/neoverse_n1.h
+++ b/include/lib/cpus/aarch64/neoverse_n1.h
@@ -35,7 +35,8 @@
  ******************************************************************************/
 #define NEOVERSE_N1_CPUACTLR2_EL1	S3_0_C15_C1_1
 
-#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2	(ULL(1) << 2)
+#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2		(ULL(1) << 2)
+#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16	(ULL(1) << 16)
 
 /* Instruction patching registers */
 #define CPUPSELR_EL3	S3_6_C15_C8_0
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index dadaf98..d685b7e 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -21,7 +21,7 @@
 #endif
 
 /* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata
+ * Errata Workaround for Neoverse N1 Erratum 1043202.
  * This applies to revision r0p0 and r1p0 of Neoverse N1.
  * Inputs:
  * x0: variant[4:7] and revision[0:3] of current cpu.
@@ -75,6 +75,35 @@
 	ret
 endfunc neoverse_n1_disable_speculative_loads
 
+/* --------------------------------------------------
+ * Errata Workaround for Neoverse N1 Erratum 1315703.
+ * This applies to revision <= r3p0 of Neoverse N1.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_n1_1315703_wa
+	/* Compare x0 against revision r3p1 */
+	mov	x17, x30
+	bl	check_errata_1315703
+	cbz	x0, 1f
+
+	mrs	x0, NEOVERSE_N1_CPUACTLR2_EL1
+	orr	x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16
+	msr	NEOVERSE_N1_CPUACTLR2_EL1, x0
+	isb
+
+1:
+	ret	x17
+endfunc errata_n1_1315703_wa
+
+func check_errata_1315703
+	/* Applies to everything <= r3p0. */
+	mov	x1, #0x30
+	b	cpu_rev_var_ls
+endfunc check_errata_1315703
+
 func neoverse_n1_reset_func
 	mov	x19, x30
 
@@ -94,6 +123,11 @@
 	bl	errata_n1_1043202_wa
 #endif
 
+#if ERRATA_N1_1315703
+	mov	x0, x18
+	bl	errata_n1_1315703_wa
+#endif
+
 #if ENABLE_AMU
 	/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
 	mrs	x0, actlr_el3
@@ -146,6 +180,7 @@
 	 * checking functions of each errata.
 	 */
 	report_errata ERRATA_N1_1043202, neoverse_n1, 1043202
+	report_errata ERRATA_N1_1315703, neoverse_n1, 1315703
 
 	ldp	x8, x30, [sp], #16
 	ret
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 599e11e..db45375 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -238,6 +238,10 @@
 # only to r0p0 and r1p0 of the Neoverse N1 cpu.
 ERRATA_N1_1043202	?=1
 
+# Flag to apply erratum 1315703 workaround during reset. This erratum applies
+# to revisions before r3p1 of the Neoverse N1 cpu.
+ERRATA_N1_1315703	?=1
+
 # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
 # Applying the workaround results in higher DSU power consumption on idle.
 ERRATA_DSU_798953	?=0
@@ -427,6 +431,10 @@
 $(eval $(call assert_boolean,ERRATA_N1_1043202))
 $(eval $(call add_define,ERRATA_N1_1043202))
 
+# Process ERRATA_N1_1315703 flag
+$(eval $(call assert_boolean,ERRATA_N1_1315703))
+$(eval $(call add_define,ERRATA_N1_1315703))
+
 # Process ERRATA_DSU_798953 flag
 $(eval $(call assert_boolean,ERRATA_DSU_798953))
 $(eval $(call add_define,ERRATA_DSU_798953))
diff --git a/plat/arm/board/fvp/aarch64/fvp_helpers.S b/plat/arm/board/fvp/aarch64/fvp_helpers.S
index 09f19f6..8efc238 100644
--- a/plat/arm/board/fvp/aarch64/fvp_helpers.S
+++ b/plat/arm/board/fvp/aarch64/fvp_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,14 +16,6 @@
 	.globl	plat_is_my_cpu_primary
 	.globl	plat_arm_calc_core_pos
 
-	.macro	fvp_choose_gicmmap  param1, param2, x_tmp, w_tmp, res
-	mov_imm	\x_tmp, V2M_SYSREGS_BASE + V2M_SYS_ID
-	ldr	\w_tmp, [\x_tmp]
-	ubfx	\w_tmp, \w_tmp, #V2M_SYS_ID_BLD_SHIFT, #V2M_SYS_ID_BLD_LENGTH
-	cmp	\w_tmp, #BLD_GIC_VE_MMAP
-	csel	\res, \param1, \param2, eq
-	.endm
-
 	/* -----------------------------------------------------
 	 * void plat_secondary_cold_boot_setup (void);
 	 *
@@ -50,35 +42,6 @@
 	str	w0, [x1, #PPOFFR_OFF]
 
 	/* ---------------------------------------------
-	 * Disable GIC bypass as well
-	 * ---------------------------------------------
-	 */
-	/* Check for GICv3 system register access */
-	mrs	x0, id_aa64pfr0_el1
-	ubfx	x0, x0, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
-	cmp	x0, #1
-	b.ne	gicv2_bypass_disable
-
-	/* Check for SRE enable */
-	mrs	x1, ICC_SRE_EL3
-	tst	x1, #ICC_SRE_SRE_BIT
-	b.eq	gicv2_bypass_disable
-
-	mrs	x2, ICC_SRE_EL3
-	orr	x2, x2, #(ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)
-	msr	ICC_SRE_EL3, x2
-	b	secondary_cold_boot_wait
-
-gicv2_bypass_disable:
-	mov_imm	x0, VE_GICC_BASE
-	mov_imm	x1, BASE_GICC_BASE
-	fvp_choose_gicmmap	x0, x1, x2, w2, x1
-	mov	w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1)
-	orr	w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
-	str	w0, [x1, #GICC_CTLR]
-
-secondary_cold_boot_wait:
-	/* ---------------------------------------------
 	 * There is no sane reason to come out of this
 	 * wfi so panic if we do. This cpu will be pow-
 	 * ered on and reset by the cpu_on pm api
diff --git a/readme.rst b/readme.rst
index 6846419..84c8020 100644
--- a/readme.rst
+++ b/readme.rst
@@ -222,7 +222,7 @@
 
 This release also contains the following platform support:
 
--  Allwinner sun50i_a64 and sun50i_h6
+-  Allwinner sun50i (A64, H5, and H6) SoCs
 -  Amlogic Meson S905 (GXBB)
 -  Amlogic Meson S905x (GXL)
 -  Arm Juno Software Development Platform