commit f38e5182f7e60d8c193cbf7712982c0ed7f47cdb
author Soby Mathew <soby.mathew@arm.com> Thu Sep 12 11:11:34 2019 +0000
committer TrustedFirmware Code Review <review@review.trustedfirmware.org> Thu Sep 12 11:11:34 2019 +0000
tree afa29cef48c483d60aa4252ba5c41403682689ad
parent 9af73b36883010a4dc4f0b0640dcc7dced895770
parent fbee88fbb039c2d2a5f5c78fac74a1942146de95

Merge changes I072c0f61,I798401f4,I9648ef55,I7225d9fa,Ife682288, ... into integration

* changes:
  rcar_gen3: drivers: ddr_b: Update DDR setting for H3, M3, M3N
  rcar_gen3: drivers: qos: update QoS setting
  rcar_gen3: drivers: ddr_b: Fix checkpatch errors in headers
  rcar_gen3: drivers: ddr_b: Fix line-over-80s
  rcar_gen3: drivers: ddr_b: Further checkpatch cleanups
  rcar_gen3: drivers: ddr_b: Clean up camel case
  rcar_get3: drivers: ddr_b: Basic checkpatch fixes
  rcar_get3: drivers: ddr: Partly unify register macros between DDR A and B
  rcar_get3: drivers: ddr: Clean up common code