diff --git a/bl31/aarch64/crash_reporting.S b/bl31/aarch64/crash_reporting.S
index 4050678..2c41029 100644
--- a/bl31/aarch64/crash_reporting.S
+++ b/bl31/aarch64/crash_reporting.S
@@ -28,7 +28,7 @@
 	 */
 .section .rodata.crash_prints, "aS"
 print_spacer:
-	.asciz	" =\t\t0x"
+	.asciz	"             = 0x"
 
 gp_regs:
 	.asciz	"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",\
@@ -55,11 +55,11 @@
 #endif /* CTX_INCLUDE_AARCH32_REGS */
 
 panic_msg:
-	.asciz "PANIC in EL3 at x30 = 0x"
+	.asciz "PANIC in EL3.\nx30"
 excpt_msg:
-	.asciz "Unhandled Exception in EL3.\nx30 =\t\t0x"
+	.asciz "Unhandled Exception in EL3.\nx30"
 intr_excpt_msg:
-	.asciz "Unhandled Interrupt Exception in EL3.\nx30 =\t\t0x"
+	.asciz "Unhandled Interrupt Exception in EL3.\nx30"
 
 	/*
 	 * Helper function to print newline to console.
@@ -94,10 +94,11 @@
 	mov	x4, x6
 	/* asm_print_str updates x4 to point to next entry in list */
 	bl	asm_print_str
+	/* x0 = number of symbols printed + 1 */
+	sub	x0, x4, x6
 	/* update x6 with the updated list pointer */
 	mov	x6, x4
-	adr	x4, print_spacer
-	bl	asm_print_str
+	bl	print_alignment
 	ldr	x4, [x7], #REGSZ
 	bl	asm_print_hex
 	bl	print_newline
@@ -107,6 +108,20 @@
 	ret
 endfunc size_controlled_print
 
+	/* -----------------------------------------------------
+	 * This function calculates and prints required number
+	 * of space characters followed by "= 0x", based on the
+	 * length of ascii register name.
+ 	 * x0: length of ascii register name + 1
+	 * ------------------------------------------------------
+ 	 */
+func print_alignment
+	/* The minimum ascii length is 3, e.g. for "x0" */
+	adr	x4, print_spacer - 3
+	add	x4, x4, x0
+	b	asm_print_str
+endfunc print_alignment
+
 	/*
 	 * Helper function to store x8 - x15 registers to
 	 * the crash buf. The system registers values are
@@ -189,7 +204,7 @@
 	 * -----------------------------------------------------
 	 */
 func el3_panic
-	msr	spsel, #1
+	msr	spsel, #MODE_SP_ELX
 	prepare_crash_buf_save_x0_x1
 	adr	x0, panic_msg
 	mov	sp, x0
@@ -230,6 +245,9 @@
 	/* Print the crash message. sp points to the crash message */
 	mov	x4, sp
 	bl	asm_print_str
+	/* Print spaces to align "x30" string */
+	mov	x0, #4
+	bl	print_alignment
 	/* load the crash buf address */
 	mrs	x0, tpidr_el3
 	/* report x30 first from the crash buf */
diff --git a/common/aarch64/debug.S b/common/aarch64/debug.S
index da740ef..ac47cbe 100644
--- a/common/aarch64/debug.S
+++ b/common/aarch64/debug.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +10,7 @@
 
 	.globl	asm_print_str
 	.globl	asm_print_hex
+	.globl	asm_print_hex_bits
 	.globl	asm_assert
 	.globl	do_panic
 
@@ -107,8 +108,11 @@
  * Clobber: x30, x0 - x3, x5
  */
 func asm_print_hex
-	mov	x3, x30
 	mov	x5, #64  /* No of bits to convert to ascii */
+
+	/* Convert to ascii number of bits in x5 */
+asm_print_hex_bits:
+	mov	x3, x30
 1:
 	sub	x5, x5, #4
 	lsrv	x0, x4, x5
diff --git a/include/plat/arm/common/aarch64/arm_macros.S b/include/plat/arm/common/aarch64/arm_macros.S
index 0bd0daf..d47e4e0 100644
--- a/include/plat/arm/common/aarch64/arm_macros.S
+++ b/include/plat/arm/common/aarch64/arm_macros.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,11 +22,13 @@
 
 /* Registers common to both GICv2 and GICv3 */
 gicd_pend_reg:
-	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
+	.asciz "gicd_ispendr regs (Offsets 0x200-0x278)\nOffset\t\t\tValue\n"
 newline:
 	.asciz "\n"
 spacer:
-	.asciz ":\t\t0x"
+	.asciz ":\t\t 0x"
+prefix:
+	.asciz "0x"
 
 	/* ---------------------------------------------
 	 * The below utility macro prints out relevant GIC
@@ -77,7 +79,15 @@
 	sub	x4, x7, x16
 	cmp	x4, #0x280
 	b.eq	exit_print_gic_regs
-	bl	asm_print_hex
+
+	/* Print "0x" */
+	adr	x4, prefix
+	bl	asm_print_str
+
+	/* Print offset */
+	sub	x4, x7, x16
+	mov	x5, #12
+	bl	asm_print_hex_bits
 
 	adr	x4, spacer
 	bl	asm_print_str
diff --git a/lib/aarch32/arm32_aeabi_divmod.c b/lib/aarch32/arm32_aeabi_divmod.c
index 0b36cb6..ea8e2bb 100644
--- a/lib/aarch32/arm32_aeabi_divmod.c
+++ b/lib/aarch32/arm32_aeabi_divmod.c
@@ -33,13 +33,11 @@
 unsigned int __aeabi_uidivmod(unsigned int numerator, unsigned int denominator);
 
 unsigned int __aeabi_uidiv(unsigned int numerator, unsigned int denominator);
-unsigned int __aeabi_uimod(unsigned int numerator, unsigned int denominator);
 
 /* returns in R0 and R1 by tail calling an asm function */
 signed int __aeabi_idivmod(signed int numerator, signed int denominator);
 
 signed int __aeabi_idiv(signed int numerator, signed int denominator);
-signed int __aeabi_imod(signed int numerator, signed int denominator);
 
 /*
  * __ste_idivmod_ret_t __aeabi_idivmod(signed numerator, signed denominator)
@@ -106,15 +104,6 @@
 	return qr.q;
 }
 
-unsigned int __aeabi_uimod(unsigned int numerator, unsigned int denominator)
-{
-	struct qr qr = { .q_n = 0, .r_n = 0 };
-
-	uint_div_qr(numerator, denominator, &qr);
-
-	return qr.r;
-}
-
 unsigned int __aeabi_uidivmod(unsigned int numerator, unsigned int denominator)
 {
 	struct qr qr = { .q_n = 0, .r_n = 0 };
@@ -145,42 +134,6 @@
 	return qr.q;
 }
 
-signed int __aeabi_imod(signed int numerator, signed int denominator)
-{
-	signed int s;
-	signed int i;
-	signed int j;
-	signed int h;
-	struct qr qr = { .q_n = 0, .r_n = 0 };
-
-	/* in case modulo of a power of 2 */
-	for (i = 0, j = 0, h = 0, s = denominator; (s != 0) || (h > 1); i++) {
-		if (s & 1) {
-			j = i;
-			h++;
-		}
-		s = s >> 1;
-	}
-	if (h == 1)
-		return numerator >> j;
-
-	if (((numerator < 0) && (denominator > 0)) ||
-	    ((numerator > 0) && (denominator < 0)))
-		qr.q_n = 1;	/* quotient shall be negate */
-
-	if (numerator < 0) {
-		numerator = -numerator;
-		qr.r_n = 1;	/* remainder shall be negate */
-	}
-
-	if (denominator < 0)
-		denominator = -denominator;
-
-	uint_div_qr(numerator, denominator, &qr);
-
-	return qr.r;
-}
-
 signed int __aeabi_idivmod(signed int numerator, signed int denominator)
 {
 	struct qr qr = { .q_n = 0, .r_n = 0 };
diff --git a/lib/extensions/ras/ras_common.c b/lib/extensions/ras/ras_common.c
index be8bece..64a4852 100644
--- a/lib/extensions/ras/ras_common.c
+++ b/lib/extensions/ras/ras_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -83,7 +83,8 @@
 {
 	struct ras_interrupt *ras_inrs = ras_interrupt_mappings.intrs;
 	struct ras_interrupt *selected = NULL;
-	int start, end, mid, probe_data, ret __unused;
+	int probe_data = 0;
+	int start, end, mid, ret __unused;
 
 	const struct err_handler_data err_data = {
 		.version = ERR_HANDLER_VERSION,
diff --git a/lib/xlat_tables/aarch32/nonlpae_tables.c b/lib/xlat_tables/aarch32/nonlpae_tables.c
index e31f9d8..bd6b152 100644
--- a/lib/xlat_tables/aarch32/nonlpae_tables.c
+++ b/lib/xlat_tables/aarch32/nonlpae_tables.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016-2017, Linaro Limited. All rights reserved.
- * Copyright (c) 2014-2017, Arm Limited. All rights reserved.
+ * Copyright (c) 2014-2019, Arm Limited. All rights reserved.
  * Copyright (c) 2014, STMicroelectronics International N.V.
  * All rights reserved.
  *
@@ -445,7 +445,8 @@
 			} else {
 				xlat_table = (unsigned long)mmu_l2_base +
 					next_xlat * MMU32B_L2_TABLE_SIZE;
-				assert(++next_xlat <= MAX_XLAT_TABLES);
+				next_xlat++;
+				assert(next_xlat <= MAX_XLAT_TABLES);
 				memset((char *)xlat_table, 0,
 					MMU32B_L2_TABLE_SIZE);
 
diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c
index 385065f..e9ab928 100644
--- a/plat/intel/soc/agilex/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex/bl2_plat_setup.c
@@ -69,9 +69,9 @@
 	deassert_peripheral_reset();
 	config_hps_hs_before_warm_reset();
 
-	watchdog_init(get_wdt_clk(&reverse_handoff_ptr));
+	watchdog_init(get_wdt_clk());
 
-	console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
+	console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE,
 		&console);
 
 	socfpga_delay_timer_init();
@@ -105,7 +105,7 @@
 
 	enable_mmu_el3(0);
 
-	dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000);
+	dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk());
 
 	info.mmc_dev_type = MMC_IS_SD;
 	info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
diff --git a/plat/intel/soc/agilex/include/agilex_clock_manager.h b/plat/intel/soc/agilex/include/agilex_clock_manager.h
index c1a7546..73e6c4e 100644
--- a/plat/intel/soc/agilex/include/agilex_clock_manager.h
+++ b/plat/intel/soc/agilex/include/agilex_clock_manager.h
@@ -80,41 +80,38 @@
 #define CLKMGR_STAT_PERPLLLOCKED(x)		(((x) & 0x00010000) >> 16)
 #define CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK	0x00000004
 #define CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK	0x00000008
+#define CLKMGR_INTOSC_HZ			460000000
 
 /* Main PLL Macros */
 #define CLKMGR_MAINPLL_EN_RESET			0x000000ff
-#define CLKMGR_MAINPLL_PLLM_MDIV(x)		((x) & 0x000003ff)
-#define CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK	0x00000001
-#define CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK	0x00000002
-
-#define CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV(x)	(((x) & 0x00003f00) >> 8)
-#define CLKMGR_MAINPLL_PLLGLOB_AREFCLKDIV(x)	(((x) & 0x00000f00) >> 8)
-#define CLKMGR_MAINPLL_PLLGLOB_DREFCLKDIV(x)	(((x) & 0x00003000) >> 12)
-
-#define CLKMGR_MAINPLL_PLLGLOB_PSRC(x)		(((x) & 0x00030000) >> 16)
-#define CLKMGR_MAINPLL_PLLGLOB_PSRC_EOSC1	0x0
-#define CLKMGR_MAINPLL_PLLGLOB_PSRC_INTOSC	0x1
-#define CLKMGR_MAINPLL_PLLGLOB_PSRC_F2S		0x2
-#define CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(x)	(((x) << 0) & 0x000003ff)
-#define CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(x)	(((x) << 16) & 0x00ff0000)
 
 /* Peripheral PLL Macros */
 #define CLKMGR_PERPLL_EN_RESET			0x00000fff
-#define CLKMGR_PERPLL_PLLM_MDIV(x)		((x) & 0x000003ff)
 #define CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x)	(((x) << 0) & 0x0000ffff)
-#define CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK	0x00000001
-
-#define CLKMGR_PERPLL_PLLGLOB_REFCLKDIV(x)	(((x) & 0x00003f00) >> 8)
-#define CLKMGR_PERPLL_PLLGLOB_AREFCLKDIV(x)	(((x) & 0x00000f00) >> 8)
-#define CLKMGR_PERPLL_PLLGLOB_DREFCLKDIV(x)	(((x) & 0x00003000) >> 12)
-
-#define CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK	0x00000002
-#define CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(x)	(((x) << 0) & 0x000003ff)
-#define CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(x)	(((x) << 16) & 0x00ff0000)
 
 /* Altera Macros */
 #define CLKMGR_ALTERA_EXTCNTRST_RESET		0xff
 
+/* Shared Macros */
+#define CLKMGR_PSRC(x)				(((x) & 0x00030000) >> 16)
+#define CLKMGR_PSRC_MAIN			0
+#define CLKMGR_PSRC_PER				1
+
+#define CLKMGR_PLLGLOB_PSRC_EOSC1		0x0
+#define CLKMGR_PLLGLOB_PSRC_INTOSC		0x1
+#define CLKMGR_PLLGLOB_PSRC_F2S			0x2
+
+#define CLKMGR_PLLM_MDIV(x)			((x) & 0x000003ff)
+#define CLKMGR_PLLGLOB_PD_SET_MSK		0x00000001
+#define CLKMGR_PLLGLOB_RST_SET_MSK		0x00000002
+
+#define CLKMGR_PLLGLOB_REFCLKDIV(x)		(((x) & 0x00003f00) >> 8)
+#define CLKMGR_PLLGLOB_AREFCLKDIV(x)		(((x) & 0x00000f00) >> 8)
+#define CLKMGR_PLLGLOB_DREFCLKDIV(x)		(((x) & 0x00003000) >> 12)
+
+#define CLKMGR_VCOCALIB_HSCNT_SET(x)		(((x) << 0) & 0x000003ff)
+#define CLKMGR_VCOCALIB_MSCNT_SET(x)		(((x) << 16) & 0x00ff0000)
+
 
 typedef struct {
 	uint32_t  clk_freq_of_eosc1;
@@ -123,6 +120,8 @@
 } CLOCK_SOURCE_CONFIG;
 
 void config_clkmgr_handoff(handoff *hoff_ptr);
-int get_wdt_clk(handoff *hoff_ptr);
+uint32_t get_wdt_clk(void);
+uint32_t get_uart_clk(void);
+uint32_t get_mmc_clk(void);
 
 #endif
diff --git a/plat/intel/soc/agilex/include/agilex_private.h b/plat/intel/soc/agilex/include/agilex_private.h
index 5ccbc8c..fc0e9fd 100644
--- a/plat/intel/soc/agilex/include/agilex_private.h
+++ b/plat/intel/soc/agilex/include/agilex_private.h
@@ -11,14 +11,13 @@
 #define AGX_MMC_REG_BASE	0xff808000
 
 #define EMMC_DESC_SIZE		(1<<20)
-#define EMMC_INIT_PARAMS(base)			\
+#define EMMC_INIT_PARAMS(base, clk)		\
 	{	.bus_width = MMC_BUS_WIDTH_4,	\
-		.clk_rate = 50000000,		\
+		.clk_rate = (clk),		\
 		.desc_base = (base),		\
 		.desc_size = EMMC_DESC_SIZE,	\
 		.flags = 0,			\
-		.reg_base = AGX_MMC_REG_BASE,	\
-		\
+		.reg_base = AGX_MMC_REG_BASE	\
 	}
 
 typedef enum {
@@ -26,7 +25,7 @@
 	BOOT_SOURCE_SDMMC,
 	BOOT_SOURCE_NAND,
 	BOOT_SOURCE_RSVD,
-	BOOT_SOURCE_QSPI,
+	BOOT_SOURCE_QSPI
 } boot_source_type;
 
 void enable_nonsecure_access(void);
diff --git a/plat/intel/soc/agilex/include/agilex_system_manager.h b/plat/intel/soc/agilex/include/agilex_system_manager.h
index 6ec2084..381c2d3 100644
--- a/plat/intel/soc/agilex/include/agilex_system_manager.h
+++ b/plat/intel/soc/agilex/include/agilex_system_manager.h
@@ -65,6 +65,11 @@
 #define AGX_CCU_NOC_CPU0_RAMSPACE0_0		0xf7004688
 #define AGX_CCU_NOC_IOM_RAMSPACE0_0		0xf7018628
 
+#define AGX_SYSMGR_CORE(x)                      (0xffd12000 + (x))
+#define SYSMGR_BOOT_SCRATCH_COLD_0		0x200
+#define SYSMGR_BOOT_SCRATCH_COLD_1		0x204
+#define SYSMGR_BOOT_SCRATCH_COLD_2		0x208
+
 #define DISABLE_BRIDGE_FIREWALL			0x0ffe0101
 #define DISABLE_L4_FIREWALL	(BIT(0) | BIT(16) | BIT(24))
 
diff --git a/plat/intel/soc/agilex/soc/agilex_clock_manager.c b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
index 6e7b43e..218676a 100644
--- a/plat/intel/soc/agilex/soc/agilex_clock_manager.c
+++ b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
@@ -12,15 +12,8 @@
 
 #include "agilex_clock_manager.h"
 #include "agilex_handoff.h"
+#include "agilex_system_manager.h"
 
-static const CLOCK_SOURCE_CONFIG  clk_source = {
-	/* clk_freq_of_eosc1 */
-	(uint32_t) 25000000,
-	/* clk_freq_of_f2h_free */
-	(uint32_t) 400000000,
-	/* clk_freq_of_cb_intosc_ls */
-	(uint32_t) 50000000,
-};
 
 uint32_t wait_pll_lock(void)
 {
@@ -114,18 +107,18 @@
 
 	/* Put both PLL in reset and power down */
 	mmio_clrbits_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB,
-			CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK |
-			CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK);
+			CLKMGR_PLLGLOB_PD_SET_MSK |
+			CLKMGR_PLLGLOB_RST_SET_MSK);
 	mmio_clrbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB,
-			CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK |
-			CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK);
+			CLKMGR_PLLGLOB_PD_SET_MSK |
+			CLKMGR_PLLGLOB_RST_SET_MSK);
 
 	/* Setup main PLL dividers */
-	mdiv = CLKMGR_MAINPLL_PLLM_MDIV(hoff_ptr->main_pll_pllm);
+	mdiv = CLKMGR_PLLM_MDIV(hoff_ptr->main_pll_pllm);
 
-	arefclk_div = CLKMGR_MAINPLL_PLLGLOB_AREFCLKDIV(
+	arefclk_div = CLKMGR_PLLGLOB_AREFCLKDIV(
 			hoff_ptr->main_pll_pllglob);
-	drefclk_div = CLKMGR_MAINPLL_PLLGLOB_DREFCLKDIV(
+	drefclk_div = CLKMGR_PLLGLOB_DREFCLKDIV(
 			hoff_ptr->main_pll_pllglob);
 
 	mscnt = 100 / (mdiv / BIT(drefclk_div));
@@ -134,8 +127,8 @@
 	hscnt = (mdiv * mscnt * BIT(drefclk_div) / arefclk_div) - 4;
 
 	mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_VCOCALIB,
-			CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(hscnt) |
-			CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(mscnt));
+			CLKMGR_VCOCALIB_HSCNT_SET(hscnt) |
+			CLKMGR_VCOCALIB_MSCNT_SET(mscnt));
 
 	mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_NOCDIV,
 			hoff_ptr->main_pll_nocdiv);
@@ -159,11 +152,11 @@
 			hoff_ptr->main_pll_nocclk);
 
 	/* Setup peripheral PLL dividers */
-	mdiv = CLKMGR_PERPLL_PLLM_MDIV(hoff_ptr->per_pll_pllm);
+	mdiv = CLKMGR_PLLM_MDIV(hoff_ptr->per_pll_pllm);
 
-	arefclk_div = CLKMGR_PERPLL_PLLGLOB_AREFCLKDIV(
+	arefclk_div = CLKMGR_PLLGLOB_AREFCLKDIV(
 			hoff_ptr->per_pll_pllglob);
-	drefclk_div = CLKMGR_PERPLL_PLLGLOB_DREFCLKDIV(
+	drefclk_div = CLKMGR_PLLGLOB_DREFCLKDIV(
 			hoff_ptr->per_pll_pllglob);
 
 	mscnt = 100 / (mdiv / BIT(drefclk_div));
@@ -172,8 +165,8 @@
 	hscnt = (mdiv * mscnt * BIT(drefclk_div) / arefclk_div) - 4;
 
 	mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_VCOCALIB,
-			CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(hscnt) |
-			CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(mscnt));
+			CLKMGR_VCOCALIB_HSCNT_SET(hscnt) |
+			CLKMGR_VCOCALIB_MSCNT_SET(mscnt));
 
 	mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EMACCTL,
 			hoff_ptr->per_pll_emacctl);
@@ -197,11 +190,11 @@
 
 	/* Take both PLL out of reset and power up */
 	mmio_setbits_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB,
-			CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK |
-			CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK);
+			CLKMGR_PLLGLOB_PD_SET_MSK |
+			CLKMGR_PLLGLOB_RST_SET_MSK);
 	mmio_setbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB,
-			CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK |
-			CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK);
+			CLKMGR_PLLGLOB_PD_SET_MSK |
+			CLKMGR_PLLGLOB_RST_SET_MSK);
 
 	wait_pll_lock();
 
@@ -256,24 +249,31 @@
 			CLKMGR_MAINPLL_EN_RESET);
 	mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EN,
 			CLKMGR_PERPLL_EN_RESET);
+
+	/* Pass clock source frequency into scratch register */
+	mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1),
+		hoff_ptr->hps_osc_clk_h);
+	mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2),
+		hoff_ptr->fpga_clk_hz);
 }
 
-int get_wdt_clk(handoff *hoff_ptr)
+/* Extract reference clock from platform clock source */
+uint32_t get_ref_clk(uint32_t pllglob)
 {
-	int main_noc_base_clk, l3_main_free_clk, l4_sys_free_clk;
-	int data32, mdiv, arefclkdiv, ref_clk;
+	uint32_t arefclkdiv, ref_clk;
+	uint32_t scr_reg;
 
-	data32 = mmio_read_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB);
-
-	switch (CLKMGR_MAINPLL_PLLGLOB_PSRC(data32)) {
-	case CLKMGR_MAINPLL_PLLGLOB_PSRC_EOSC1:
-		ref_clk = clk_source.clk_freq_of_eosc1;
+	switch (CLKMGR_PSRC(pllglob)) {
+	case CLKMGR_PLLGLOB_PSRC_EOSC1:
+		scr_reg = AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1);
+		ref_clk = mmio_read_32(scr_reg);
 		break;
-	case CLKMGR_MAINPLL_PLLGLOB_PSRC_INTOSC:
-		ref_clk = clk_source.clk_freq_of_cb_intosc_ls;
+	case CLKMGR_PLLGLOB_PSRC_INTOSC:
+		ref_clk = CLKMGR_INTOSC_HZ;
 		break;
-	case CLKMGR_MAINPLL_PLLGLOB_PSRC_F2S:
-		ref_clk = clk_source.clk_freq_of_f2h_free;
+	case CLKMGR_PLLGLOB_PSRC_F2S:
+		scr_reg = AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2);
+		ref_clk = mmio_read_32(scr_reg);
 		break;
 	default:
 		ref_clk = 0;
@@ -281,13 +281,91 @@
 		break;
 	}
 
-	arefclkdiv = CLKMGR_MAINPLL_PLLGLOB_AREFCLKDIV(data32);
-	mdiv = CLKMGR_MAINPLL_PLLM_MDIV(hoff_ptr->main_pll_pllm);
+	arefclkdiv = CLKMGR_PLLGLOB_AREFCLKDIV(pllglob);
+	ref_clk /= arefclkdiv;
 
-	ref_clk = (ref_clk / arefclkdiv) * mdiv;
-	main_noc_base_clk = ref_clk / (hoff_ptr->main_pll_pllc1 & 0x7ff);
-	l3_main_free_clk = main_noc_base_clk / (hoff_ptr->main_pll_nocclk + 1);
-	l4_sys_free_clk = l3_main_free_clk / 4;
+	return ref_clk;
+}
 
-	return l4_sys_free_clk;
+/* Calculate clock frequency based on parameter */
+uint32_t get_clk_freq(uint32_t psrc_reg, uint32_t main_pllc, uint32_t per_pllc)
+{
+	uint32_t clk_psrc, mdiv, ref_clk;
+	uint32_t pllm_reg, pllc_reg, pllc_div, pllglob_reg;
+
+	clk_psrc = mmio_read_32(CLKMGR_MAINPLL + psrc_reg);
+
+	switch (CLKMGR_PSRC(clk_psrc)) {
+	case CLKMGR_PSRC_MAIN:
+		pllm_reg = CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLM;
+		pllc_reg = CLKMGR_MAINPLL + main_pllc;
+		pllglob_reg = CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB;
+		break;
+	case CLKMGR_PSRC_PER:
+		pllm_reg = CLKMGR_PERPLL + CLKMGR_PERPLL_PLLM;
+		pllc_reg = CLKMGR_PERPLL + per_pllc;
+		pllglob_reg = CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB;
+		break;
+	default:
+		return 0;
+	}
+
+	ref_clk = get_ref_clk(mmio_read_32(pllglob_reg));
+	mdiv = CLKMGR_PLLM_MDIV(mmio_read_32(pllm_reg));
+	ref_clk *= mdiv;
+
+	pllc_div = mmio_read_32(pllc_reg) & 0x7ff;
+
+	return ref_clk / pllc_div;
+}
+
+/* Return L3 interconnect clock */
+uint32_t get_l3_clk(void)
+{
+	uint32_t l3_clk;
+
+	l3_clk = get_clk_freq(CLKMGR_MAINPLL_NOCCLK, CLKMGR_MAINPLL_PLLC1,
+				CLKMGR_PERPLL_PLLC1);
+	return l3_clk;
+}
+
+/* Calculate clock frequency to be used for watchdog timer */
+uint32_t get_wdt_clk(void)
+{
+	uint32_t l3_clk, l4_sys_clk;
+
+	l3_clk = get_l3_clk();
+	l4_sys_clk = l3_clk / 4;
+
+	return l4_sys_clk;
+}
+
+/* Calculate clock frequency to be used for UART driver */
+uint32_t get_uart_clk(void)
+{
+	uint32_t data32, l3_clk, l4_sp_clk;
+
+	l3_clk = get_l3_clk();
+
+	data32 = mmio_read_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_NOCDIV);
+	data32 = (data32 >> 16) & 0x3;
+
+	l4_sp_clk = l3_clk >> data32;
+
+	return l4_sp_clk;
+}
+
+/* Calculate clock frequency to be used for SDMMC driver */
+uint32_t get_mmc_clk(void)
+{
+	uint32_t data32, mmc_clk;
+
+	mmc_clk = get_clk_freq(CLKMGR_ALTERA_SDMMCCTR,
+		CLKMGR_MAINPLL_PLLC3, CLKMGR_PERPLL_PLLC3);
+
+	data32 = mmio_read_32(CLKMGR_ALTERA + CLKMGR_ALTERA_SDMMCCTR);
+	data32 = (data32 & 0x7ff) + 1;
+	mmc_clk = (mmc_clk / data32) / 4;
+
+	return mmc_clk;
 }
diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c
index a13ee49..c4a0359 100644
--- a/plat/rockchip/common/bl31_plat_setup.c
+++ b/plat/rockchip/common/bl31_plat_setup.c
@@ -14,7 +14,6 @@
 #include <drivers/console.h>
 #include <drivers/generic_delay_timer.h>
 #include <drivers/ti/uart/uart_16550.h>
-#include <lib/coreboot.h>
 #include <lib/mmio.h>
 #include <plat_private.h>
 #include <plat/common/platform.h>
@@ -62,16 +61,10 @@
 
 	params_early_setup(arg1);
 
-#if COREBOOT
-	if (coreboot_serial.type)
-		console_16550_register(coreboot_serial.baseaddr,
-				       coreboot_serial.input_hertz,
-				       coreboot_serial.baud,
-				       &console);
-#else
-	console_16550_register(rockchip_get_uart_base(), PLAT_RK_UART_CLOCK,
-			       PLAT_RK_UART_BAUDRATE, &console);
-#endif
+	if (rockchip_get_uart_base() != 0)
+		console_16550_register(rockchip_get_uart_base(),
+				       rockchip_get_uart_clock(),
+				       rockchip_get_uart_baudrate(), &console);
 
 	VERBOSE("bl31_setup\n");
 
diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h
index 714a8bf..990d106 100644
--- a/plat/rockchip/common/include/plat_private.h
+++ b/plat/rockchip/common/include/plat_private.h
@@ -139,6 +139,8 @@
 extern const mmap_region_t plat_rk_mmap[];
 
 uint32_t rockchip_get_uart_base(void);
+uint32_t rockchip_get_uart_baudrate(void);
+uint32_t rockchip_get_uart_clock(void);
 
 #endif /* __ASSEMBLER__ */
 
diff --git a/plat/rockchip/common/params_setup.c b/plat/rockchip/common/params_setup.c
index d0fea4f..8c2e5e9 100644
--- a/plat/rockchip/common/params_setup.c
+++ b/plat/rockchip/common/params_setup.c
@@ -26,12 +26,6 @@
 static struct bl_aux_gpio_info suspend_gpio[10];
 uint32_t suspend_gpio_cnt;
 static struct bl_aux_rk_apio_info suspend_apio;
-static uint32_t rk_uart_base = PLAT_RK_UART_BASE;
-
-uint32_t rockchip_get_uart_base(void)
-{
-	return rk_uart_base;
-}
 
 #if COREBOOT
 static int dt_process_fdt(u_register_t param_from_bl2)
@@ -39,6 +33,9 @@
 	return -ENODEV;
 }
 #else
+static uint32_t rk_uart_base = PLAT_RK_UART_BASE;
+static uint32_t rk_uart_baudrate = PLAT_RK_UART_BAUDRATE;
+static uint32_t rk_uart_clock = PLAT_RK_UART_CLOCK;
 static uint8_t fdt_buffer[0x10000];
 
 void *plat_get_fdt(void)
@@ -53,9 +50,12 @@
 	int node_offset;
 	int stdout_path_len;
 	const char *stdout_path;
+	const char *separator;
+	const char *baud_start;
 	char serial_char;
 	int serial_no;
 	uint32_t uart_base;
+	uint32_t baud;
 
 	node_offset = fdt_path_offset(fdt, path_name);
 	if (node_offset < 0)
@@ -68,7 +68,7 @@
 
 	/*
 	 * We expect something like:
-	 *   "serial0:...""
+	 *   "serial0:baudrate"
 	 */
 	if (strncmp("serial", stdout_path, 6) != 0)
 		return;
@@ -96,11 +96,38 @@
 		uart_base = UART4_BASE;
 		break;
 #endif
+#ifdef UART5_BASE
+	case 5:
+		uart_base = UART5_BASE;
+		break;
+#endif
 	default:
 		return;
 	}
 
 	rk_uart_base = uart_base;
+
+	separator = strchr(stdout_path, ':');
+	if (!separator)
+		return;
+
+	baud = 0;
+	baud_start = separator + 1;
+	while (*baud_start != '\0') {
+		/*
+		 * uart binding is <baud>{<parity>{<bits>{...}}}
+		 * So the baudrate either is the whole string, or
+		 * we end in the parity characters.
+		 */
+		if (*baud_start == 'n' || *baud_start == 'o' ||
+		    *baud_start == 'e')
+			break;
+
+		baud = baud * 10 + (*baud_start - '0');
+		baud_start++;
+	}
+
+	rk_uart_baudrate = baud;
 }
 
 static int dt_process_fdt(u_register_t param_from_bl2)
@@ -118,6 +145,33 @@
 }
 #endif
 
+uint32_t rockchip_get_uart_base(void)
+{
+#if COREBOOT
+	return coreboot_serial.baseaddr;
+#else
+	return rk_uart_base;
+#endif
+}
+
+uint32_t rockchip_get_uart_baudrate(void)
+{
+#if COREBOOT
+	return coreboot_serial.baud;
+#else
+	return rk_uart_baudrate;
+#endif
+}
+
+uint32_t rockchip_get_uart_clock(void)
+{
+#if COREBOOT
+	return coreboot_serial.input_hertz;
+#else
+	return rk_uart_clock;
+#endif
+}
+
 struct bl_aux_gpio_info *plat_get_rockchip_gpio_reset(void)
 {
 	return &rst_gpio;
diff --git a/plat/rockchip/common/sp_min_plat_setup.c b/plat/rockchip/common/sp_min_plat_setup.c
index 7b1a0b5..6d15075 100644
--- a/plat/rockchip/common/sp_min_plat_setup.c
+++ b/plat/rockchip/common/sp_min_plat_setup.c
@@ -15,7 +15,6 @@
 #include <drivers/console.h>
 #include <drivers/generic_delay_timer.h>
 #include <drivers/ti/uart/uart_16550.h>
-#include <lib/coreboot.h>
 #include <lib/mmio.h>
 #include <plat_private.h>
 #include <plat/common/platform.h>
@@ -57,16 +56,11 @@
 
 	params_early_setup(arg1);
 
-#if COREBOOT
-	if (coreboot_serial.type)
-		console_16550_register(coreboot_serial.baseaddr,
-				       coreboot_serial.input_hertz,
-				       coreboot_serial.baud,
-				       &console);
-#else
-	console_16550_register(rockchip_get_uart_base(), PLAT_RK_UART_CLOCK,
-			       PLAT_RK_UART_BAUDRATE, &console);
-#endif
+	if (rockchip_get_uart_base() != 0)
+		console_16550_register(rockchip_get_uart_base(),
+				       rockchip_get_uart_clock(),
+				       rockchip_get_uart_baudrate(), &console);
+
 	VERBOSE("sp_min_setup\n");
 
 	bl31_params_parse_helper(arg0, NULL, &bl33_ep_info);
diff --git a/plat/rockchip/px30/px30_def.h b/plat/rockchip/px30/px30_def.h
index 021165a..9b8ccfc 100644
--- a/plat/rockchip/px30/px30_def.h
+++ b/plat/rockchip/px30/px30_def.h
@@ -54,6 +54,9 @@
 #define UART2_BASE		0xff160000
 #define UART2_SIZE		SIZE_K(64)
 
+#define UART5_BASE		0xff178000
+#define UART5_SIZE		SIZE_K(64)
+
 #define I2C0_BASE		0xff180000
 #define I2C0_SIZE		SIZE_K(64)
 
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index a6b5973..30941fd 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -1125,32 +1125,41 @@
 
 void suspend_uart(void)
 {
-	uart_save.uart_lcr = mmio_read_32(PLAT_RK_UART_BASE + UART_LCR);
-	uart_save.uart_ier = mmio_read_32(PLAT_RK_UART_BASE + UART_IER);
-	uart_save.uart_mcr = mmio_read_32(PLAT_RK_UART_BASE + UART_MCR);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_LCR,
+	uint32_t uart_base = rockchip_get_uart_base();
+
+	if (uart_base == 0)
+		return;
+
+	uart_save.uart_lcr = mmio_read_32(uart_base + UART_LCR);
+	uart_save.uart_ier = mmio_read_32(uart_base + UART_IER);
+	uart_save.uart_mcr = mmio_read_32(uart_base + UART_MCR);
+	mmio_write_32(uart_base + UART_LCR,
 		      uart_save.uart_lcr | UARTLCR_DLAB);
-	uart_save.uart_dll = mmio_read_32(PLAT_RK_UART_BASE + UART_DLL);
-	uart_save.uart_dlh = mmio_read_32(PLAT_RK_UART_BASE + UART_DLH);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_save.uart_lcr);
+	uart_save.uart_dll = mmio_read_32(uart_base + UART_DLL);
+	uart_save.uart_dlh = mmio_read_32(uart_base + UART_DLH);
+	mmio_write_32(uart_base + UART_LCR, uart_save.uart_lcr);
 }
 
 void resume_uart(void)
 {
+	uint32_t uart_base = rockchip_get_uart_base();
 	uint32_t uart_lcr;
 
-	mmio_write_32(PLAT_RK_UART_BASE + UARTSRR,
+	if (uart_base == 0)
+		return;
+
+	mmio_write_32(uart_base + UARTSRR,
 		      XMIT_FIFO_RESET | RCVR_FIFO_RESET | UART_RESET);
 
-	uart_lcr = mmio_read_32(PLAT_RK_UART_BASE + UART_LCR);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_MCR, DIAGNOSTIC_MODE);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_lcr | UARTLCR_DLAB);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_DLL, uart_save.uart_dll);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_DLH, uart_save.uart_dlh);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_save.uart_lcr);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_IER, uart_save.uart_ier);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_FCR, UARTFCR_FIFOEN);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_MCR, uart_save.uart_mcr);
+	uart_lcr = mmio_read_32(uart_base + UART_LCR);
+	mmio_write_32(uart_base + UART_MCR, DIAGNOSTIC_MODE);
+	mmio_write_32(uart_base + UART_LCR, uart_lcr | UARTLCR_DLAB);
+	mmio_write_32(uart_base + UART_DLL, uart_save.uart_dll);
+	mmio_write_32(uart_base + UART_DLH, uart_save.uart_dlh);
+	mmio_write_32(uart_base + UART_LCR, uart_save.uart_lcr);
+	mmio_write_32(uart_base + UART_IER, uart_save.uart_ier);
+	mmio_write_32(uart_base + UART_FCR, UARTFCR_FIFOEN);
+	mmio_write_32(uart_base + UART_MCR, uart_save.uart_mcr);
 }
 
 void save_usbphy(void)
diff --git a/services/spd/opteed/opteed.mk b/services/spd/opteed/opteed.mk
index b1b2175..643b054 100644
--- a/services/spd/opteed/opteed.mk
+++ b/services/spd/opteed/opteed.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -13,3 +13,6 @@
 				services/spd/opteed/opteed_pm.c
 
 NEED_BL32		:=	yes
+
+# required so that optee code can control access to the timer registers
+NS_TIMER_SWITCH		:=	1
diff --git a/services/std_svc/spm/spm_buffers.c b/services/std_svc/spm/spm_buffers.c
index 3e0c949..79398ba 100644
--- a/services/std_svc/spm/spm_buffers.c
+++ b/services/std_svc/spm/spm_buffers.c
@@ -38,6 +38,8 @@
 		struct sprt_response *resp = &(responses[i]);
 
 		if ((resp->is_valid == 1) && (resp->token == token)) {
+			spin_unlock(&responses_lock);
+
 			return -1;
 		}
 	}