tree 2f5efa0f2fc2f922e19abd9e1eadebc0c8eb8f85
parent 69ef7b7ffe66b64bdffee0a387774e7088022503
author Alexei Fedorov <Alexei.Fedorov@arm.com> 1566310964 +0100
committer Paul Beesley <paul.beesley@arm.com> 1569512162 +0000

AArch32: Disable Secure Cycle Counter

This patch changes implementation for disabling Secure Cycle
Counter. For ARMv8.5 the counter gets disabled by setting
SDCR.SCCD bit on CPU cold/warm boot. For the earlier
architectures PMCR register is saved/restored on secure
world entry/exit from/to Non-secure state, and cycle counting
gets disabled by setting PMCR.DP bit.
In 'include\aarch32\arch.h' header file new
ARMv8.5-PMU related definitions were added.

Change-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>