commit ac1adfde3f6b34455c66698ec1e8d69cf00b39af
author Soby Mathew <soby.mathew@arm.com> Fri Jul 26 10:26:37 2019 +0000
committer TrustedFirmware Code Review <review@review.trustedfirmware.org> Fri Jul 26 10:26:37 2019 +0000
tree 93b266e669057b1a59f126a8f00dca6f8c44fe18
parent 4129340717c215f3cc3841e32ed0b6cd5baf7ffb
parent 8a079e88d12860382193328e883e775765a6777f

Merge "rockchip: px30: Fix build error" into integration

plat/rockchip/px30/drivers/pmu/pmu.c

diff --git a/plat/rockchip/px30/drivers/pmu/pmu.c b/plat/rockchip/px30/drivers/pmu/pmu.c
index a5ed766..0a2515d 100644
--- a/plat/rockchip/px30/drivers/pmu/pmu.c
+++ b/plat/rockchip/px30/drivers/pmu/pmu.c
@@ -626,13 +626,13 @@
 
 	/* select pvtm as 32k source */
 	mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKSELS_CON(0),
-		      BITS_WITH_WMASK(1, 0x3, 14));
+		      BITS_WITH_WMASK(1, 0x3U, 14));
 }
 
 static void pvtm_32k_config_restore(void)
 {
 	mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKSELS_CON(0),
-		      ddr_data.pmu_cru_clksel_con0 | BITS_WMSK(0x3, 14));
+		      ddr_data.pmu_cru_clksel_con0 | BITS_WMSK(0x3U, 14));
 
 	mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0,
 		      WITH_16BITS_WMSK(ddr_data.pgrf_pvtm_con[0]));
@@ -869,7 +869,7 @@
 static inline void pll_pwr_ctr(uint32_t pll_base, uint32_t pll_id, uint32_t pd)
 {
 	mmio_write_32(pll_base + PLL_CON(1),
-		      BITS_WITH_WMASK(1, 1, 15));
+		      BITS_WITH_WMASK(1, 1U, 15));
 	if (pd)
 		mmio_write_32(pll_base + PLL_CON(1),
 			      BITS_WITH_WMASK(1, 1, 14));