diff --git a/.editorconfig b/.editorconfig
index b14e025..f523ca1 100644
--- a/.editorconfig
+++ b/.editorconfig
@@ -54,13 +54,10 @@
 trim_trailing_whitespace = true
 
 
-# Adjustment for existing .rst files with different format
-[*.{rst,md}]
+# Adjustment for ReStructuredText (RST) documentation
+[*.{rst}]
 indent_size = 4
 indent_style = space
-max_line_length = 180
-# 180 only selected to prevent changes to existing text.
-tab_width = 4
 
 
 # Adjustment for python which prefers a different style
diff --git a/docs/acknowledgements.rst b/docs/about/acknowledgements.rst
similarity index 74%
rename from docs/acknowledgements.rst
rename to docs/about/acknowledgements.rst
index 74b77ff..dfc66c8 100644
--- a/docs/acknowledgements.rst
+++ b/docs/about/acknowledgements.rst
@@ -6,7 +6,8 @@
    specific contributors referred to in "Arm Limited and Contributors" copyright
    notices. As contributors are now encouraged to put their name or company name
    directly into the copyright notices, this file is not relevant for new
-   contributions.
+   contributions. See the :ref:`License` document for the correct template to
+   use for new contributions.
 
 - Linaro Limited
 - Marvell International Ltd.
@@ -15,3 +16,7 @@
 - Socionext Inc.
 - STMicroelectronics
 - Xilinx, Inc.
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*
diff --git a/docs/about/contact.rst b/docs/about/contact.rst
new file mode 100644
index 0000000..9cb25ef
--- /dev/null
+++ b/docs/about/contact.rst
@@ -0,0 +1,47 @@
+Support & Contact
+-----------------
+
+We welcome any feedback on |TF-A| and there are several methods for providing
+it or for obtaining support.
+
+.. warning::
+  If you think you have found a security vulnerability, please report this using
+  the process defined in the :ref:`Security Handling` document.
+
+Mailing Lists
+^^^^^^^^^^^^^
+
+Public mailing lists for TF-A and the wider Trusted Firmware project are
+hosted on TrustedFirmware.org. The mailing lists can be used for general
+enquiries, enhancement requests and issue reports, or to follow and participate
+in technical or organizational discussions around the project. These discussions
+include design proposals, advance notice of changes and upcoming events.
+
+The relevant lists for the TF-A project are:
+
+-  `TF-A development`_
+-  `TF-A-Tests development`_
+
+You can see a `summary of all the lists`_ on the TrustedFirmware.org website.
+
+Issue Tracker
+^^^^^^^^^^^^^
+
+Specific issues may be raised using the `issue tracker`_ on the
+TrustedFirmware.org website. Using this tracker makes it easy for the
+maintainers to prioritise and respond to your ticket.
+
+Arm Licensees
+^^^^^^^^^^^^^
+
+Arm licensees have an additional support conduit - they may contact Arm directly
+via their partner managers.
+
+.. _`issue tracker`: https://developer.trustedfirmware.org
+.. _`TF-A development`: https://lists.trustedfirmware.org/pipermail/tf-a/
+.. _`TF-A-Tests development`: https://lists.trustedfirmware.org/pipermail/tf-a-tests/
+.. _`summary of all the lists`: https://lists.trustedfirmware.org
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*
diff --git a/docs/about/features.rst b/docs/about/features.rst
new file mode 100644
index 0000000..3441c5e
--- /dev/null
+++ b/docs/about/features.rst
@@ -0,0 +1,127 @@
+Feature Overview
+================
+
+This page provides an overview of the current |TF-A| feature set. For a full
+description of these features and their implementation details, please see
+the documents that are part of the *Components* and *System Design* chapters.
+
+The :ref:`Change Log & Release Notes` provides details of changes made since the
+last release.
+
+Current features
+----------------
+
+-  Initialization of the secure world, for example exception vectors, control
+   registers and interrupts for the platform.
+
+-  Library support for CPU specific reset and power down sequences. This
+   includes support for errata workarounds and the latest Arm DynamIQ CPUs.
+
+-  Drivers to enable standard initialization of Arm System IP, for example
+   Generic Interrupt Controller (GIC), Cache Coherent Interconnect (CCI),
+   Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone
+   Controller (TZC).
+
+-  A generic |SCMI| driver to interface with conforming power controllers, for
+   example the Arm System Control Processor (SCP).
+
+-  SMC (Secure Monitor Call) handling, conforming to the `SMC Calling
+   Convention`_ using an EL3 runtime services framework.
+
+-  |PSCI| library support for CPU, cluster and system power management
+   use-cases.
+   This library is pre-integrated with the AArch64 EL3 Runtime Software, and
+   is also suitable for integration with other AArch32 EL3 Runtime Software,
+   for example an AArch32 Secure OS.
+
+-  A minimal AArch32 Secure Payload (*SP_MIN*) to demonstrate |PSCI| library
+   integration with AArch32 EL3 Runtime Software.
+
+-  Secure Monitor library code such as world switching, EL1 context management
+   and interrupt routing.
+   When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the
+   AArch64 EL3 Runtime Software must be integrated with a Secure Payload
+   Dispatcher (SPD) component to customize the interaction with the SP.
+
+-  A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP
+   interaction with PSCI.
+
+-  SPDs for the `OP-TEE Secure OS`_, `NVIDIA Trusted Little Kernel`_
+   and `Trusty Secure OS`_.
+
+-  A Trusted Board Boot implementation, conforming to all mandatory TBBR
+   requirements. This includes image authentication, Firmware Update (or
+   recovery mode), and packaging of the various firmware images into a
+   Firmware Image Package (FIP).
+
+-  Pre-integration of TBB with the Arm CryptoCell product, to take advantage of
+   its hardware Root of Trust and crypto acceleration services.
+
+-  Reliability, Availability, and Serviceability (RAS) functionality, including
+
+   -  A Secure Partition Manager (SPM) to manage Secure Partitions in
+      Secure-EL0, which can be used to implement simple management and
+      security services.
+
+   -  An |SDEI| dispatcher to route interrupt-based |SDEI| events.
+
+   -  An Exception Handling Framework (EHF) that allows dispatching of EL3
+      interrupts to their registered handlers, to facilitate firmware-first
+      error handling.
+
+-  A dynamic configuration framework that enables each of the firmware images
+   to be configured at runtime if required by the platform. It also enables
+   loading of a hardware configuration (for example, a kernel device tree)
+   as part of the FIP, to be passed through the firmware stages.
+
+-  Support for alternative boot flows, for example to support platforms where
+   the EL3 Runtime Software is loaded using other firmware or a separate
+   secure system processor, or where a non-TF-A ROM expects BL2 to be loaded
+   at EL3.
+
+-  Support for the GCC, LLVM and Arm Compiler 6 toolchains.
+
+-  Support for combining several libraries into a "romlib" image that may be
+   shared across images to reduce memory footprint. The romlib image is stored
+   in ROM but is accessed through a jump-table that may be stored
+   in read-write memory, allowing for the library code to be patched.
+
+-  A prototype implementation of a Secure Partition Manager (SPM) that is based
+   on the SPCI Alpha 1 and SPRT draft specifications.
+
+-  Support for ARMv8.3 pointer authentication in the normal and secure worlds.
+   The use of pointer authentication in the normal world is enabled whenever
+   architectural support is available, without the need for additional build
+   flags. Use of pointer authentication in the secure world remains an
+   experimental configuration at this time and requires the
+   ``BRANCH_PROTECTION`` option to be set to non-zero.
+
+-  Position-Independent Executable (PIE) support. Initially for BL31 only, with
+   further support to be added in a future release.
+
+Still to come
+-------------
+
+-  Support for additional platforms.
+
+-  Refinements to Position Independent Executable (PIE) support.
+
+-  Continued support for the draft SPCI specification, to enable the use of
+   secure partition management in the secure world.
+
+-  Documentation enhancements.
+
+-  Ongoing support for new architectural features, CPUs and System IP.
+
+-  Ongoing support for new Arm system architecture specifications.
+
+-  Ongoing security hardening, optimization and quality improvements.
+
+.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
+.. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os
+.. _NVIDIA Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary
+.. _Trusty Secure OS: https://source.android.com/security/trusty
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*
diff --git a/docs/about/index.rst b/docs/about/index.rst
new file mode 100644
index 0000000..3a10266
--- /dev/null
+++ b/docs/about/index.rst
@@ -0,0 +1,13 @@
+About
+=====
+
+.. toctree::
+   :maxdepth: 1
+   :caption: Contents
+   :numbered:
+
+   features
+   release-information
+   maintainers
+   contact
+   acknowledgements
diff --git a/docs/maintainers.rst b/docs/about/maintainers.rst
similarity index 96%
rename from docs/maintainers.rst
rename to docs/about/maintainers.rst
index d997baa..68f84ea 100644
--- a/docs/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -19,8 +19,8 @@
 :G: `AlexeiFedorov`_
 :M: Paul Beesley <paul.beesley@arm.com>
 :G: `pbeesley-arm`_
-:M: John Tsichritzis <john.tsichritzis@arm.com>
-:G: `jts-arm`_
+:M: György Szing <gyorgy.szing@arm.com>
+:G: `gyuri-szing`_
 
 Allwinner ARMv8 platform port
 -----------------------------
@@ -49,9 +49,9 @@
 :F: plat/amlogic/gxl/
 
 Amlogic Meson S905X2 (G12A) platform port
----------------------------------------
+-----------------------------------------
 :M: Carlo Caione <ccaione@baylibre.com>
-:G: `carlo.caione`_
+:G: `carlocaione`_
 :F: docs/plat/meson-g12a.rst
 :F: drivers/amlogic/g12a
 :F: plat/amlogic/g12a/
@@ -122,7 +122,7 @@
 :M: Tien Hock Loh <tien.hock.loh@intel.com>
 :G: `thloh85-intel`_
 :M: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
-:G: `mabdulha`_
+:G: mabdulha
 :F: plat/intel/soc
 :F: drivers/intel/soc/
 
@@ -282,14 +282,15 @@
 .. _Anson-Huang: https://github.com/Anson-Huang
 .. _bryanodonoghue: https://github.com/bryanodonoghue
 .. _b49020: https://github.com/b49020
+.. _carlocaione: https://github.com/carlocaione
 .. _danh-arm: https://github.com/danh-arm
 .. _etienne-lms: https://github.com/etienne-lms
 .. _glneo: https://github.com/glneo
 .. _grandpaul: https://github.com/grandpaul
+.. _gyuri-szing: https://github.com/gyuri-szing
 .. _hzhuang1: https://github.com/hzhuang1
 .. _JackyBai: https://github.com/JackyBai
 .. _jenswi-linaro: https://github.com/jenswi-linaro
-.. _jts-arm: https://github.com/jts-arm
 .. _jwerner-chromium: https://github.com/jwerner-chromium
 .. _kostapr: https://github.com/kostapr
 .. _ldts: https://github.com/ldts
@@ -308,6 +309,7 @@
 .. _sivadur: https://github.com/sivadur
 .. _smaeul: https://github.com/smaeul
 .. _soby-mathew: https://github.com/soby-mathew
+.. _thloh85-intel: https://github.com/thloh85-intel
 .. _thomas-arm: https://github.com/thomas-arm
 .. _TonyXie06: https://github.com/TonyXie06
 .. _vwadekar: https://github.com/vwadekar
diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
new file mode 100644
index 0000000..c230e60
--- /dev/null
+++ b/docs/about/release-information.rst
@@ -0,0 +1,68 @@
+Release Processes
+=================
+
+Project Release Cadence
+-----------------------
+
+The project currently aims to do a release once every 6 months which will be
+tagged on the master branch. There will be a code freeze (stop merging
+non-essential changes) up to 4 weeks prior to the target release date. The release
+candidates will start appearing after this and only bug fixes or updates
+required for the release will be merged. The maintainers are free to use their
+judgement on what changes are essential for the release. A release branch may be
+created after code freeze if there are significant changes that need merging onto
+the integration branch during the merge window.
+
+The release testing will be performed on release candidates and depending on
+issues found, additional release candidates may be created to fix the issues.
+
+::
+
+                            |<----------6 months---------->|
+            |<---4 weeks--->|              |<---4 weeks--->|
+       +-----------------------------------------------------------> time
+            |               |              |               |
+         code freeze       ver w.x       code freeze     ver y.z
+
+
+Upcoming Releases
+~~~~~~~~~~~~~~~~~
+
+These are the estimated dates for the upcoming release. These may change
+depending on project requirement and partner feedback.
+
++-----------------+---------------------------+------------------------------+
+| Release Version |  Target Date              | Expected Code Freeze         |
++=================+===========================+==============================+
+| v2.0            | 1st week of Oct '18       | 1st week of Sep '18          |
++-----------------+---------------------------+------------------------------+
+| v2.1            | 5th week of Mar '19       | 1st week of Mar '19          |
++-----------------+---------------------------+------------------------------+
+| v2.2            | 4th week of Oct '19       | 1st week of Oct '19          |
++-----------------+---------------------------+------------------------------+
+| v2.3            | 4th week of Mar '20       | 1st week of Mar '20          |
++-----------------+---------------------------+------------------------------+
+
+Removal of Deprecated Interfaces
+--------------------------------
+
+As mentioned in the :ref:`Platform Compatibility Policy`, this is a live
+document cataloging all the deprecated interfaces in TF-A project and the
+Release version after which it will be removed.
+
++--------------------------------+-------------+---------+---------------------------------------------------------+
+| Interface                      | Deprecation | Removed | Comments                                                |
+|                                | Date        | after   |                                                         |
+|                                |             | Release |                                                         |
++================================+=============+=========+=========================================================+
+| ``AARCH32``/``AARCH64`` macros | Oct '19     | v2.3    | Deprecated in favor of ``__aarch64__``                  |
++--------------------------------+-------------+---------+---------------------------------------------------------+
+| ``__ASSEMBLY__`` macro         | Oct '19     | v2.3    | Deprecated in favor of ``__ASSEMBLER__``                |
++--------------------------------+-------------+---------+---------------------------------------------------------+
+| Prototype SPCI-based SPM       | Oct '19     | v2.2    | Based on outdated Alpha 1 spec. Will be replaced with   |
+| (services/std_svc/spm)         |             |         | alternative methods of secure partitioning support.     |
++--------------------------------+-------------+---------+---------------------------------------------------------+
+
+--------------
+
+*Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/change-log.rst b/docs/change-log.rst
index 0a89aa6..a0db2a9 100644
--- a/docs/change-log.rst
+++ b/docs/change-log.rst
@@ -4,6 +4,422 @@
 This document contains a summary of the new features, changes, fixes and known
 issues in each release of Trusted Firmware-A.
 
+Version 2.2
+-----------
+
+New Features
+^^^^^^^^^^^^
+
+- Architecture
+   - Enable Pointer Authentication (PAuth) support for Secure World
+       - Adds support for ARMv8.3-PAuth in BL1 SMC calls and
+         BL2U image for firmware updates.
+
+   - Enable Memory Tagging Extension (MTE) support in both secure and non-secure
+     worlds
+       - Adds support for the new Memory Tagging Extension arriving in
+         ARMv8.5. MTE support is now enabled by default on systems that
+         support it at EL0.
+       - To enable it at ELx for both the non-secure and the secure
+         world, the compiler flag ``CTX_INCLUDE_MTE_REGS`` includes register
+         saving and restoring when necessary in order to prevent information
+         leakage between the worlds.
+
+   - Add support for Branch Target Identification (BTI)
+
+- Build System
+   - Modify FVP makefile for CPUs that support both AArch64/32
+
+   - AArch32: Allow compiling with soft-float toolchain
+
+   - Makefile: Add default warning flags
+
+   - Add Makefile check for PAuth and AArch64
+
+   - Add compile-time errors for HW_ASSISTED_COHERENCY flag
+
+   - Apply compile-time check for AArch64-only CPUs
+
+   - build_macros: Add mechanism to prevent bin generation.
+
+   - Add support for default stack-protector flag
+
+   - spd: opteed: Enable NS_TIMER_SWITCH
+
+   - plat/arm: Skip BL2U if RESET_TO_SP_MIN flag is set
+
+   - Add new build option to let each platform select which implementation of spinlocks
+     it wants to use
+
+- CPU Support
+   - DSU: Workaround for erratum 798953 and 936184
+
+   - Neoverse N1: Force cacheable atomic to near atomic
+   - Neoverse N1: Workaround for erratum 1073348, 1130799, 1165347, 1207823,
+     1220197, 1257314, 1262606, 1262888, 1275112, 1315703, 1542419
+
+   - Neoverse Zeus: Apply the MSR SSBS instruction
+
+   - cortex-a76AE: Support added for Cortex-A76AE CPU
+   - cortex-a76: Workaround for erratum 1257314, 1262606, 1262888, 1275112,
+     1286807
+
+   - cortex-a65/a65AE: Support added for  Cortex-A65 and  Cortex-A65AE CPUs
+   - cortex-a65: Enable AMU for  Cortex-A65
+
+   - cortex-a55: Workaround for erratum 1221012
+
+   - cortex-a35: Workaround for erratum 855472
+
+   - cortex-a9: Workaround for erratum 794073
+
+- Drivers
+   - console: Allow the console to register multiple times
+
+   - delay: Timeout detection support
+
+   - gicv3: Enabled multi-socket GIC redistributor frame discovery and migrated
+     ARM platforms to the new API
+       - Adds ``gicv3_rdistif_probe`` function that delegates the responsibility
+         of discovering the corresponding redistributor base frame to each CPU
+         itself.
+
+   - sbsa: Add SBSA watchdog driver
+
+   - st/stm32_hash: Add HASH driver
+
+   - ti/uart: Add an AArch32 variant
+
+- Library at ROM (romlib)
+   - Introduce BTI support in Library at ROM (romlib)
+
+- New Platforms Support
+   - amlogic: g12a: New platform support added for the S905X2 (G12A) platform
+   - amlogic: meson/gxl: New platform support added for Amlogic Meson
+     S905x (GXL)
+
+   - arm/a5ds: New platform support added for A5 DesignStart
+
+   - arm/corstone: New platform support added for Corstone-700
+
+   - intel: New platform support added for Agilex
+
+   - mediatek:  New platform support added for MediaTek mt8183
+
+   - qemu/qemu_sbsa: New platform support added for QEMU SBSA platform
+
+   - renesas/rcar_gen3: plat: New platform support added for D3
+
+   - rockchip: New platform support added for px30
+   - rockchip: New platform support added for rk3288
+
+   - rpi: New platform support added for Raspberry Pi 4
+
+- Platforms
+   - arm/common: Introduce wrapper functions to setup secure watchdog
+
+   - arm/fvp: Add Delay Timer driver to BL1 and BL31 and option for defining
+     platform DRAM2 base
+   - arm/fvp: Add Linux DTS files for 32 bit threaded FVPs
+
+   - arm/n1sdp: Add code for DDR ECC enablement and BL33 copy to DDR, Initialise CNTFRQ
+     in Non Secure CNTBaseN
+
+   - arm/juno: Use shared mbedtls heap between BL1 and BL2 and add basic support for
+     dynamic config
+
+   - imx: Basic support for PicoPi iMX7D, rdc module init, caam module init,
+     aipstz init, IMX_SIP_GET_SOC_INFO, IMX_SIP_BUILDINFO added
+
+   - intel: Add ncore ccu driver
+
+   - mediatek/mt81*: Use new bl31_params_parse() helper
+
+   - nvidia: tegra: Add support for multi console interface
+
+   - qemu/qemu_sbsa: Adding memory mapping for both FLASH0/FLASH1
+   - qemu: Added gicv3 support, new console interface in AArch32, and sub-platforms
+
+   - renesas/rcar_gen3: plat: Add R-Car V3M support, new board revision for H3ULCB, DBSC4
+     setting before self-refresh mode
+
+   - socionext/uniphier: Support console based on  multi-console
+
+   - st: stm32mp1: Add OP-TEE, Avenger96, watchdog, LpDDR3, authentication support
+     and general SYSCFG management
+
+   - ti/k3: common: Add support for J721E, Use coherent memory for shared data, Trap all
+     asynchronous bus errors to EL3
+
+   - xilinx/zynqmp: Add support for multi console interface, Initialize IPI table from
+     zynqmp_config_setup()
+
+- PSCI
+   - Adding new optional PSCI hook ``pwr_domain_on_finish_late``
+      - This PSCI hook ``pwr_domain_on_finish_late`` is similar to
+        ``pwr_domain_on_finish`` but is guaranteed to be invoked when the
+        respective core and cluster are participating in coherency.
+
+- Security
+   - Speculative Store Bypass Safe (SSBS): Further enhance protection against Spectre
+     variant 4 by disabling speculative loads/stores (SPSR.SSBS bit) by default.
+
+   - UBSAN support and handlers
+      - Adds support for the Undefined Behaviour sanitizer. There are two types of
+        support offered - minimalistic trapping support which essentially immediately
+        crashes on undefined behaviour and full support with full debug messages.
+
+- Tools
+   - cert_create: Add support for bigger RSA key sizes (3KB and 4KB),
+     previously the maximum size was 2KB.
+
+   - fiptool: Add support to build fiptool on Windows.
+
+
+Changed
+^^^^^^^
+
+- Architecture
+   - Refactor ARMv8.3 Pointer Authentication support code
+
+   - backtrace: Strip PAC field when PAUTH is enabled
+
+   - Prettify crash reporting output on AArch64.
+
+   - Rework smc_unknown return code path in smc_handler
+      - Leverage the existing ``el3_exit()`` return routine for smc_unknown return
+        path rather than a custom set of instructions.
+
+- BL-Specific
+   - Invalidate dcache build option for BL2 entry at EL3
+
+   - Add missing support for BL2_AT_EL3 in XIP memory
+
+- Boot Flow
+   - Add helper to parse BL31 parameters (both versions)
+
+   - Factor out cross-BL API into export headers suitable for 3rd party code
+
+   - Introduce lightweight BL platform parameter library
+
+- Drivers
+   - auth: Memory optimization for Chain of Trust (CoT) description
+
+   - bsec: Move bsec_mode_is_closed_device() service to platform
+
+   - cryptocell: Move Cryptocell specific API into driver
+
+   - gicv3: Prevent pending G1S interrupt from becoming G0 interrupt
+
+   - mbedtls: Remove weak heap implementation
+
+   - mmc: Increase delay between ACMD41 retries
+   - mmc: stm32_sdmmc2: Correctly manage block size
+   - mmc: stm32_sdmmc2: Manage max-frequency property from DT
+
+   - synopsys/emmc: Do not change FIFO TH as this breaks some platforms
+   - synopsys: Update synopsys drivers to not rely on undefined overflow behaviour
+
+   - ufs: Extend the delay after reset to wait for some slower chips
+
+- Platforms
+   - amlogic/meson/gxl: Remove BL2 dependency from BL31
+
+   - arm/common: Shorten the Firmware Update (FWU) process
+
+   - arm/fvp: Remove GIC initialisation from secondary core cold boot
+
+   - arm/sgm: Temporarily disable shared Mbed TLS heap for SGM
+
+   - hisilicon: Update hisilicon drivers to not rely on undefined overflow behaviour
+
+   - imx: imx8: Replace PLAT_IMX8* with PLAT_imx8*, remove duplicated linker symbols and
+     deprecated code include, keep only IRQ 32 unmasked, enable all power domain by default
+
+   - marvell: Prevent SError accessing PCIe link, Switch to xlat_tables_v2, do not rely on
+     argument passed via smc, make sure that comphy init will use correct address
+
+   - mediatek: mt8173: Refactor RTC and PMIC drivers
+   - mediatek: mt8173: Apply MULTI_CONSOLE framework
+
+   - nvidia: Tegra: memctrl_v2: fix "overflow before widen" coverity issue
+
+   - qemu: Simplify the image size calculation, Move and generalise FDT PSCI fixup, move
+     gicv2 codes to separate file
+
+   - renesas/rcar_gen3: Convert to multi-console API, update QoS setting, Update IPL and
+     Secure Monitor Rev2.0.4, Change to restore timer counter value at resume, Update DDR
+     setting rev.0.35, qos: change subslot cycle, Change periodic write DQ training option.
+
+   - rockchip: Allow SOCs with undefined wfe check bits, Streamline and complete UARTn_BASE
+     macros, drop rockchip-specific imported linker symbols for bl31, Disable binary generation
+     for all SOCs, Allow console device to be set by DTB, Use new bl31_params_parse functions
+
+   - rpi/rpi3: Move shared rpi3 files into common directory
+
+   - socionext/uniphier: Set CONSOLE_FLAG_TRANSLATE_CRLF and clean up console driver
+   - socionext/uniphier: Replace DIV_ROUND_UP() with div_round_up() from utils_def.h
+
+   - st/stm32mp: Split stm32mp_io_setup function, move stm32_get_gpio_bank_clock() to private
+     file, correctly handle Clock Spreading Generator, move oscillator functions to generic file,
+     realign device tree files with internal devs, enable RTCAPB clock for dual-core chips, use a
+     common function to check spinlock is available, move check_header() to common code
+
+   - ti/k3: Enable SEPARATE_CODE_AND_RODATA by default, Remove shared RAM space,
+     Drop _ADDRESS from K3_USART_BASE to match other defines, Remove MSMC port
+     definitions, Allow USE_COHERENT_MEM for K3, Set L2 latency on A72 cores
+
+- PSCI
+   - PSCI: Lookup list of parent nodes to lock only once
+
+- Secure Partition Manager (SPM): SPCI Prototype
+   - Fix service UUID lookup
+
+   - Adjust size of virtual address space per partition
+
+   - Refactor xlat context creation
+
+   - Move shim layer to TTBR1_EL1
+
+   - Ignore empty regions in resource description
+
+- Security
+   - Refactor SPSR initialisation code
+
+   - SMMUv3: Abort DMA transactions
+      - For security DMA should be blocked at the SMMU by default unless explicitly
+        enabled for a device. SMMU is disabled after reset with all streams bypassing
+        the SMMU, and abortion of all incoming transactions implements a default deny
+        policy on reset.
+      - Moves ``bl1_platform_setup()`` function from arm_bl1_setup.c to FVP platforms'
+        fvp_bl1_setup.c and fvp_ve_bl1_setup.c files.
+
+- Tools
+   - cert_create: Remove RSA PKCS#1 v1.5 support
+
+
+Resolved Issues
+^^^^^^^^^^^^^^^
+
+- Architecture
+   - Fix the CAS spinlock implementation by adding a missing DSB in ``spin_unlock()``
+
+   - AArch64: Fix SCTLR bit definitions
+      - Removes incorrect ``SCTLR_V_BIT`` definition and adds definitions for
+        ARMv8.3-Pauth `EnIB`, `EnDA` and `EnDB` bits.
+
+   - Fix restoration of PAuth context
+      - Replace call to ``pauth_context_save()`` with ``pauth_context_restore()`` in
+        case of unknown SMC call.
+
+- BL-Specific Issues
+   - Fix BL31 crash reporting on AArch64 only platforms
+
+- Build System
+   - Remove several warnings reported with W=2 and W=1
+
+- Code Quality Issues
+   - SCTLR and ACTLR are 32-bit for AArch32 and 64-bit for AArch64
+   - Unify type of "cpu_idx" across PSCI module.
+   - Assert if power level value greater then PSCI_INVALID_PWR_LVL
+   - Unsigned long should not be used as per coding guidelines
+   - Reduce the number of memory leaks in cert_create
+   - Fix type of cot_desc_ptr
+   - Use explicit-width data types in AAPCS parameter structs
+   - Add python configuration for editorconfig
+   - BL1: Fix type consistency
+
+   - Enable -Wshift-overflow=2 to check for undefined shift behavior
+   - Updated upstream platforms to not rely on undefined overflow behaviour
+
+- Coverity Quality Issues
+   - Remove GGC ignore -Warray-bounds
+   - Fix Coverity #261967, Infinite loop
+   - Fix Coverity #343017, Missing unlock
+   - Fix Coverity #343008, Side affect in assertion
+   - Fix Coverity #342970, Uninitialized scalar variable
+
+- CPU Support
+   - cortex-a12: Fix MIDR mask
+
+- Drivers
+   - console: Remove Arm console unregister on suspend
+
+   - gicv3: Fix support for full SPI range
+
+   - scmi: Fix wrong payload length
+
+- Library Code
+   - libc: Fix sparse warning for __assert()
+
+   - libc: Fix memchr implementation
+
+- Platforms
+   - rpi: rpi3: Fix compilation error when stack protector is enabled
+
+   - socionext/uniphier: Fix compilation fail for SPM support build config
+
+   - st/stm32mp1: Fix TZC400 configuration against non-secure DDR
+
+   - ti/k3: common: Fix RO data area size calculation
+
+- Security
+   - AArch32: Disable Secure Cycle Counter
+      - Changes the implementation for disabling Secure Cycle Counter.
+        For ARMv8.5 the counter gets disabled by setting ``SDCR.SCCD`` bit on
+        CPU cold/warm boot. For the earlier architectures PMCR register is
+        saved/restored on secure world entry/exit from/to Non-secure state,
+        and cycle counting gets disabled by setting PMCR.DP bit.
+   - AArch64: Disable Secure Cycle Counter
+      - For ARMv8.5 the counter gets disabled by setting ``MDCR_El3.SCCD`` bit on
+        CPU cold/warm boot. For the earlier architectures PMCR_EL0 register is
+        saved/restored on secure world entry/exit from/to Non-secure state,
+        and cycle counting gets disabled by setting PMCR_EL0.DP bit.
+
+Deprecations
+^^^^^^^^^^^^
+
+- Common Code
+   - Remove MULTI_CONSOLE_API flag and references to it
+
+   - Remove deprecated `plat_crash_console_*`
+
+   - Remove deprecated interfaces `get_afflvl_shift`, `mpidr_mask_lower_afflvls`, `eret`
+
+   - AARCH32/AARCH64 macros are now deprecated in favor of ``__aarch64__``
+
+   - ``__ASSEMBLY__`` macro is now deprecated in favor of ``__ASSEMBLER__``
+
+- Drivers
+   - console: Removed legacy console API
+   - console: Remove deprecated finish_console_register
+
+   - tzc: Remove deprecated types `tzc_action_t` and `tzc_region_attributes_t`
+
+- Secure Partition Manager (SPM):
+   - Prototype SPCI-based SPM (services/std_svc/spm) will be replaced with alternative
+     methods of secure partitioning support.
+
+Known Issues
+^^^^^^^^^^^^
+
+- Build System Issues
+   - dtb: DTB creation not supported when building on a Windows host.
+
+     This step in the build process is skipped when running on a Windows host. A
+     known issue from the 1.6 release.
+
+- Platform Issues
+   - arm/juno: System suspend from Linux does not function as documented in the
+     user guide
+
+     Following the instructions provided in the user guide document does not
+     result in the platform entering system suspend state as expected. A message
+     relating to the hdlcd driver failing to suspend will be emitted on the
+     Linux terminal.
+
+   - mediatek/mt6795: This platform does not build in this release
+
 Version 2.1
 -----------
 
diff --git a/docs/components/firmware-update.rst b/docs/components/firmware-update.rst
index 2bff00f..a591565 100644
--- a/docs/components/firmware-update.rst
+++ b/docs/components/firmware-update.rst
@@ -7,7 +7,7 @@
 This document describes the design of the Firmware Update (FWU) feature, which
 enables authenticated firmware to update firmware images from external
 interfaces such as USB, UART, SD-eMMC, NAND, NOR or Ethernet to SoC Non-Volatile
-memories such as NAND Flash, LPPDR2-NVM or any memory determined by the
+memories such as NAND Flash, LPDDR2-NVM or any memory determined by the
 platform. This feature functions even when the current firmware in the system
 is corrupt or missing; it therefore may be used as a recovery mode. It may also
 be complemented by other, higher level firmware update software.
diff --git a/docs/conf.py b/docs/conf.py
index b267de0..a100241 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -15,9 +15,6 @@
 
 project = 'Trusted Firmware-A'
 
-version = '2.1'
-release = version # We don't need these to be distinct
-
 # -- General configuration ---------------------------------------------------
 
 # Add any Sphinx extension module names here, as strings. They can be
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst
index 1deacb7..4958fc0 100644
--- a/docs/design/firmware-design.rst
+++ b/docs/design/firmware-design.rst
@@ -1672,7 +1672,7 @@
    point during a cold boot.
 
 -  On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory
-   region and transfered to the SCP before being overwritten by EL3 Runtime
+   region and transferred to the SCP before being overwritten by EL3 Runtime
    Software.
 
 -  BL32 (for AArch64) can be loaded in one of the following locations:
@@ -2623,7 +2623,7 @@
 Cortex-A15 target.
 
 Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support.
-Note that using neon at runtime has constraints on non secure wolrd context.
+Note that using neon at runtime has constraints on non secure world context.
 TF-A does not yet provide VFP context management.
 
 Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set
diff --git a/docs/getting_started/image-terminology.rst b/docs/getting_started/image-terminology.rst
index d9e08f7..5993d6e 100644
--- a/docs/getting_started/image-terminology.rst
+++ b/docs/getting_started/image-terminology.rst
@@ -7,7 +7,7 @@
 General Notes
 -------------
 
-- Some of the names and abbreviated names have changed to accomodate new
+- Some of the names and abbreviated names have changed to accommodate new
   requirements. The changed names are as backward compatible as possible to
   minimize confusion. Where applicable, the previous names are indicated. Some
   code, documentation and build artefacts may still refer to the previous names;
@@ -44,7 +44,7 @@
 ~~~~~~~~~~~~~~~~~~~~~~~
 
 Typically, this is the first code to execute on the AP and cannot be modified.
-Its primary purpose is to perform the minimum intialization necessary to load
+Its primary purpose is to perform the minimum initialization necessary to load
 and authenticate an updateable AP firmware image into an executable RAM
 location, then hand-off control to that image.
 
@@ -96,7 +96,7 @@
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 Typically, this is the first code to execute on the SCP and cannot be modified.
-Its primary purpose is to perform the minimum intialization necessary to load
+Its primary purpose is to perform the minimum initialization necessary to load
 and authenticate an updateable SCP firmware image into an executable RAM
 location, then hand-off control to that image. This may be performed in
 conjunction with other processor firmware (for example, ``AP_BL1`` and
@@ -129,7 +129,7 @@
 
 Typically, this is the first normal world code to execute on the AP during a
 firmware update operation, and cannot be modified. Its primary purpose is to
-load subequent firmware update images from an external interface and communicate
+load subsequent firmware update images from an external interface and communicate
 with ``AP_BL1`` to authenticate those images.
 
 During firmware update, there are (potentially) multiple transitions between the
diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst
index d715769..9cca75e 100644
--- a/docs/getting_started/porting-guide.rst
+++ b/docs/getting_started/porting-guide.rst
@@ -549,7 +549,7 @@
 -  **PLAT_PARTITION_BLOCK_SIZE**
    The size of partition block. It could be either 512 bytes or 4096 bytes.
    The default value is 512.
-   `For example, define the build flag in platform.mk`_:
+   For example, define the build flag in ``platform.mk``:
    PLAT_PARTITION_BLOCK_SIZE := 4096
    $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE))
 
@@ -954,7 +954,7 @@
     Return   : void
 
 A platform may need to do additional initialization after reset. This function
-allows the platform to do the platform specific intializations. Platform
+allows the platform to do the platform specific initializations. Platform
 specific errata workarounds could also be implemented here. The API should
 preserve the values of callee saved registers x19 to x29.
 
@@ -2777,7 +2777,7 @@
 added to the local implementation.
 
 Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have
-been written specifically for TF-A. Fome implementation files have been obtained
+been written specifically for TF-A. Some implementation files have been obtained
 from `FreeBSD`_, others have been written specifically for TF-A as well. The
 files can be found in ``include/lib/libc`` and ``lib/libc``.
 
diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst
index c7359ad..9876531 100644
--- a/docs/getting_started/user-guide.rst
+++ b/docs/getting_started/user-guide.rst
@@ -188,8 +188,6 @@
       `Summary of build options`_ for more information on available build
       options.
 
-   -  (AArch32 only) Currently only ``PLAT=fvp`` is supported.
-
    -  (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
       corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp_min, is
       provided by TF-A to demonstrate how PSCI Library can be integrated with
@@ -1360,7 +1358,7 @@
        make [DEBUG=1] [V=1] fiptool
 
        # Unpack firmware images from Linaro FIP
-       ./tools/fiptool/fiptool unpack <path-to-linaro-release>/fip.bin
+       ./tools/fiptool/fiptool unpack <path-to-linaro-release>/[SOFTWARE]/fip.bin
 
    The unpack operation will result in a set of binary images extracted to the
    current working directory. The SCP_BL2 image corresponds to
@@ -1407,7 +1405,7 @@
 
       .. code:: shell
 
-          export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
+          export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-eabi-
 
    -  Build BL32 in AArch32.
 
@@ -1766,6 +1764,7 @@
 -  ``FVP_Base_Cortex-A76AEx8``
 -  ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
 -  ``FVP_Base_Neoverse-N1x4``
+-  ``FVP_Base_Zeusx4``
 -  ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
 -  ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
 -  ``FVP_RD_E1Edge`` (Version 11.3 build 42)
diff --git a/docs/index.rst b/docs/index.rst
index 4f0f6ef..baadd42 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -6,6 +6,7 @@
    :hidden:
 
    Home<self>
+   about/index
    getting_started/index
    process/index
    components/index
@@ -14,14 +15,9 @@
    perf/index
    security_advisories/index
    change-log
-   acknowledgements
    glossary
-   maintainers
    license
 
-.. contents:: On This Page
-    :depth: 3
-
 Trusted Firmware-A (TF-A) provides a reference implementation of secure world
 software for `Armv7-A and Armv8-A`_, including a `Secure Monitor`_ executing
 at Exception Level 3 (EL3). It implements various Arm interface standards,
@@ -47,229 +43,41 @@
 with reference implementations of Arm standards to benefit developers working
 with Armv7-A and Armv8-A TrustZone technology.
 
-Functionality
--------------
-
--  Initialization of the secure world, for example exception vectors, control
-   registers and interrupts for the platform.
-
--  Library support for CPU specific reset and power down sequences. This
-   includes support for errata workarounds and the latest Arm DynamIQ CPUs.
-
--  Drivers to enable standard initialization of Arm System IP, for example
-   Generic Interrupt Controller (GIC), Cache Coherent Interconnect (CCI),
-   Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone
-   Controller (TZC).
-
--  A generic `SCMI`_ driver to interface with conforming power controllers, for
-   example the Arm System Control Processor (SCP).
-
--  SMC (Secure Monitor Call) handling, conforming to the `SMC Calling
-   Convention`_ using an EL3 runtime services framework.
-
--  `PSCI`_ library support for CPU, cluster and system power management
-   use-cases.
-   This library is pre-integrated with the AArch64 EL3 Runtime Software, and
-   is also suitable for integration with other AArch32 EL3 Runtime Software,
-   for example an AArch32 Secure OS.
-
--  A minimal AArch32 Secure Payload (SP\_MIN) to demonstrate `PSCI`_ library
-   integration with AArch32 EL3 Runtime Software.
-
--  Secure Monitor library code such as world switching, EL1 context management
-   and interrupt routing.
-   When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the
-   AArch64 EL3 Runtime Software must be integrated with a Secure Payload
-   Dispatcher (SPD) component to customize the interaction with the SP.
-
--  A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP
-   interaction with PSCI.
-
--  SPDs for the `OP-TEE Secure OS`_, `NVIDIA Trusted Little Kernel`_
-   and `Trusty Secure OS`_.
-
--  A Trusted Board Boot implementation, conforming to all mandatory TBBR
-   requirements. This includes image authentication, Firmware Update (or
-   recovery mode), and packaging of the various firmware images into a
-   Firmware Image Package (FIP).
-
--  Pre-integration of TBB with the Arm CryptoCell product, to take advantage of
-   its hardware Root of Trust and crypto acceleration services.
-
--  Reliability, Availability, and Serviceability (RAS) functionality, including
-
-   -  A Secure Partition Manager (SPM) to manage Secure Partitions in
-      Secure-EL0, which can be used to implement simple management and
-      security services.
-
-   -  An |SDEI| dispatcher to route interrupt-based |SDEI| events.
-
-   -  An Exception Handling Framework (EHF) that allows dispatching of EL3
-      interrupts to their registered handlers, to facilitate firmware-first
-      error handling.
-
--  A dynamic configuration framework that enables each of the firmware images
-   to be configured at runtime if required by the platform. It also enables
-   loading of a hardware configuration (for example, a kernel device tree)
-   as part of the FIP, to be passed through the firmware stages.
-
--  Support for alternative boot flows, for example to support platforms where
-   the EL3 Runtime Software is loaded using other firmware or a separate
-   secure system processor, or where a non-TF-A ROM expects BL2 to be loaded
-   at EL3.
-
--  Support for the GCC, LLVM and Arm Compiler 6 toolchains.
-
--  Support for combining several libraries into a "romlib" image that may be
-   shared across images to reduce memory footprint. The romlib image is stored
-   in ROM but is accessed through a jump-table that may be stored
-   in read-write memory, allowing for the library code to be patched.
-
--  A prototype implementation of a Secure Partition Manager (SPM) that is based
-   on the SPCI Alpha 1 and SPRT draft specifications.
-
--  Support for ARMv8.3 pointer authentication in the normal and secure worlds.
-   The use of pointer authentication in the normal world is enabled whenever
-   architectural support is available, without the need for additional build
-   flags. Use of pointer authentication in the secure world remains an
-   experimental configuration at this time and requires the
-   ``BRANCH_PROTECTION`` option to be set to non-zero.
-
--  Position-Independent Executable (PIE) support. Initially for BL31 only, with
-   further support to be added in a future release.
-
-For a full description of functionality and implementation details, please
-see :ref:`Firmware Design` and supporting documentation. The
-:ref:`Change Log & Release Notes` provides details of changes made since the
-last release.
-
-Platforms
----------
-
-Various AArch32 and AArch64 builds of this release have been tested on r0, r1
-and r2 variants of the `Juno Arm Development Platform`_.
-
-The latest version of the AArch64 build of TF-A has been tested on the following
-Arm FVPs without shifted affinities, and that do not support threaded CPU cores
-(64-bit host machine only).
-
-.. note::
-   The FVP models used are Version 11.5 Build 33, unless otherwise stated.
-
--  ``FVP_Base_AEMv8A-AEMv8A``
--  ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
--  ``FVP_Base_RevC-2xAEMv8A``
--  ``FVP_Base_Cortex-A32x4``
--  ``FVP_Base_Cortex-A35x4``
--  ``FVP_Base_Cortex-A53x4``
--  ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
--  ``FVP_Base_Cortex-A55x4``
--  ``FVP_Base_Cortex-A57x1-A53x1``
--  ``FVP_Base_Cortex-A57x2-A53x4``
--  ``FVP_Base_Cortex-A57x4-A53x4``
--  ``FVP_Base_Cortex-A57x4``
--  ``FVP_Base_Cortex-A72x4-A53x4``
--  ``FVP_Base_Cortex-A72x4``
--  ``FVP_Base_Cortex-A73x4-A53x4``
--  ``FVP_Base_Cortex-A73x4``
--  ``FVP_Base_Cortex-A75x4``
--  ``FVP_Base_Cortex-A76x4``
--  ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model)
--  ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model)
--  ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
--  ``FVP_Base_Neoverse-N1x4`` (Tested with internal model)
--  ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
--  ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
--  ``FVP_RD_E1Edge`` (Version 11.3 build 42)
--  ``FVP_RD_N1Edge`` (Version 11.3 build 42)
--  ``Foundation_Platform``
-
-The latest version of the AArch32 build of TF-A has been tested on the following
-Arm FVPs without shifted affinities, and that do not support threaded CPU cores
-(64-bit host machine only).
-
--  ``FVP_Base_AEMv8A-AEMv8A``
--  ``FVP_Base_Cortex-A32x4``
-
-.. note::
-   The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities.
-
-The Foundation FVP can be downloaded free of charge. The Base FVPs can be
-licensed from Arm. See the `Arm FVP website`_.
-
-All the above platforms have been tested with `Linaro Release 18.04`_.
-
-This release also contains the following platform support:
-
--  Allwinner sun50i_a64 and sun50i_h6
--  Amlogic Meson S905 (GXBB)
--  Arm Juno Software Development Platform
--  Arm Neoverse N1 System Development Platform (N1SDP)
--  Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP
--  Arm Neoverse Reference Design E1 Edge (RD-E1-Edge) FVP
--  Arm SGI-575 and SGM-775
--  Arm Versatile Express FVP
--  HiKey, HiKey960 and Poplar boards
--  Intel Stratix 10 SoC FPGA
--  Marvell Armada 3700 and 8K
--  MediaTek MT6795 and MT8173 SoCs
--  NVIDIA T132, T186 and T210 SoCs
--  NXP QorIQ LS1043A, i.MX8MM, i.MX8MQ, i.MX8QX, i.MX8QM and i.MX7Solo WaRP7
--  QEMU
--  Raspberry Pi 3
--  Renesas R-Car Generation 3
--  RockChip RK3328, RK3368 and RK3399 SoCs
--  Socionext UniPhier SoC family and SynQuacer SC2A11 SoCs
--  STMicroelectronics STM32MP1
--  Texas Instruments K3 SoCs
--  Xilinx Versal and Zynq UltraScale + MPSoC
-
-Still to come
--------------
-
--  Support for additional platforms.
-
--  Refinements to Position Independent Executable (PIE) support.
-
--  Refinements to the SPCI-based SPM implementation as the draft SPCI and SPRT
-   specifications continue to evolve.
-
--  Documentation enhancements.
-
--  Ongoing support for new architectural features, CPUs and System IP.
-
--  Ongoing support for new Arm system architecture specifications.
-
--  Ongoing security hardening, optimization and quality improvements.
-
-For a full list of detailed issues in the current code, please see the
-:ref:`Change Log & Release Notes` and the `issue tracker`_.
-
-Getting started
+Getting Started
 ---------------
 
-See the :ref:`User Guide` for instructions on how to download, install, build
-and use TF-A with the Arm `FVP`_\ s.
+The |TF-A| documentation contains guidance for obtaining and building the
+software for existing, supported platforms, as well as supporting information
+for porting the software to a new platform.
 
-See the :ref:`Firmware Design` for information on how TF-A works.
+The **About** chapter gives a high-level overview of |TF-A| features as well as
+some information on the project and how it is organized.
 
-See the :ref:`Porting Guide` as well for information about how to use this
-software on another Armv7-A or Armv8-A platform.
+Refer to the documents in the **Getting Started** chapter for information about
+the prerequisites and requirements for building |TF-A|.
 
-See the :ref:`Contributor's Guide` for information on how to contribute to this
-project and the :ref:`Contributor Acknowledgements` file for a list of
-contributors to the project.
+The **Processes & Policies** chapter explains the project's release schedule
+and process, how security disclosures are handled, and the guidelines for
+contributing to the project (including the coding style).
 
-Contact Us
-~~~~~~~~~~
+The **Components** chapter holds documents that explain specific components
+that make up the |TF-A| software, the :ref:`Exception Handling Framework`, for
+example.
 
-We welcome any feedback on TF-A. If you think you have found a security
-vulnerability, please report this using the process defined in the TF-A
-:ref:`Security Handling` document.
+In the **System Design** chapter you will find documents that explain the
+design of portions of the software that involve more than one component, such
+as the :ref:`Trusted Board Boot` process.
 
-For all other feedback, please use the `issue tracker`_ or our `mailing list`_.
+**Platform Ports** provides a list of the supported hardware and software-model
+platforms that are supported upstream in |TF-A|. Most of these platforms also
+have additional documentation that has been provided by the maintainers of the
+platform.
 
-Arm licensees may contact Arm directly via their partner managers.
+The results of any performance evaluations are added to the
+**Performance & Testing** chapter.
+
+**Security Advisories** holds a list of documents relating to |CVE| entries that
+have previously been raised against the software.
 
 --------------
 
@@ -277,21 +85,8 @@
 
 .. _Armv7-A and Armv8-A: https://developer.arm.com/products/architecture/a-profile
 .. _Secure Monitor: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php
-.. _Power State Coordination Interface (PSCI): PSCI_
-.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
+.. _Power State Coordination Interface (PSCI): http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
 .. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a
+.. _System Control and Management Interface (SCMI): http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf
+.. _Software Delegated Exception Interface (SDEI): http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
 .. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
-.. _System Control and Management Interface (SCMI): SCMI_
-.. _SCMI: http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf
-.. _Software Delegated Exception Interface (SDEI): SDEI_
-.. _SDEI: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
-.. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php
-.. _Arm FVP website: FVP_
-.. _FVP: https://developer.arm.com/products/system-design/fixed-virtual-platforms
-.. _Linaro Release 18.04: https://community.arm.com/dev-platforms/b/documents/posts/linaro-release-notes-deprecated#LinaroRelease18.04
-.. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os
-.. _NVIDIA Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary
-.. _Trusty Secure OS: https://source.android.com/security/trusty
-.. _trustedfirmware.org: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
-.. _issue tracker: https://issues.trustedfirmware.org
-.. _mailing list: https://lists.trustedfirmware.org/mailman/listinfo/tf-a
diff --git a/docs/perf/psci-performance-juno.rst b/docs/perf/psci-performance-juno.rst
index 4cc4302..c127c1c 100644
--- a/docs/perf/psci-performance-juno.rst
+++ b/docs/perf/psci-performance-juno.rst
@@ -168,7 +168,7 @@
 | 5     | 21                  | 17                 | 6                        |
 +-------+---------------------+--------------------+--------------------------+
 
-The ``CLUSH_OVERHEAD`` times for lead CPU 4 and all CPUs in the non-lead cluster
+The ``CFLUSH_OVERHEAD`` times for lead CPU 4 and all CPUs in the non-lead cluster
 are large because all other CPUs in the cluster are powered down during the
 test. The ``CPU_SUSPEND`` call powers down to the cluster level, requiring a
 flush of both L1 and L2 caches.
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index d0b4827..5495280 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -5,6 +5,7 @@
    :maxdepth: 1
    :caption: Contents
    :numbered:
+   :hidden:
 
    allwinner
    meson-gxbb
@@ -35,3 +36,83 @@
    ti-k3
    xilinx-versal
    xilinx-zynqmp
+
+This section provides a list of supported upstream *platform ports* and the
+documentation associated with them. The list of suported Arm |FVP| platforms is
+outlined in the following section.
+
+.. note::
+   In addition to the platforms ports listed within the table of contents, there
+   are several additional platforms that are supported upstream but which do not
+   currently have associated documentation:
+
+   - Arm Juno Software Development Platform. Various |AArch32| and |AArch64|
+     builds of this release have been tested on r0, r1 and r2 variants of the
+     `Juno Arm Development Platform`_.
+   - Arm Neoverse N1 System Development Platform (N1SDP)
+   - Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP
+   - Arm Neoverse Reference Design E1 Edge (RD-E1-Edge) FVP
+   - Arm SGI-575 and SGM-775
+   - MediaTek MT6795 and MT8173 SoCs
+
+Fixed Virtual Platform (FVP) Support
+------------------------------------
+
+The latest version of the AArch64 build of TF-A has been tested on the
+following Arm FVPs without shifted affinities, and that do not support threaded
+CPU cores (64-bit host machine only).
+
+.. note::
+   The FVP models used are Version 11.6 Build 45, unless otherwise stated.
+
+-  ``FVP_Base_AEMv8A-AEMv8A``
+-  ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
+-  ``FVP_Base_RevC-2xAEMv8A``
+-  ``FVP_Base_Cortex-A32x4``
+-  ``FVP_Base_Cortex-A35x4``
+-  ``FVP_Base_Cortex-A53x4``
+-  ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
+-  ``FVP_Base_Cortex-A55x4``
+-  ``FVP_Base_Cortex-A57x1-A53x1``
+-  ``FVP_Base_Cortex-A57x2-A53x4``
+-  ``FVP_Base_Cortex-A57x4-A53x4``
+-  ``FVP_Base_Cortex-A57x4``
+-  ``FVP_Base_Cortex-A72x4-A53x4``
+-  ``FVP_Base_Cortex-A72x4``
+-  ``FVP_Base_Cortex-A73x4-A53x4``
+-  ``FVP_Base_Cortex-A73x4``
+-  ``FVP_Base_Cortex-A75x4``
+-  ``FVP_Base_Cortex-A76x4``
+-  ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model)
+-  ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model)
+-  ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
+-  ``FVP_Base_Zeusx4``
+-  ``FVP_Base_Neoverse-N1x4`` (Tested with internal model)
+-  ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
+-  ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
+-  ``FVP_RD_E1Edge`` (Version 11.3 build 42)
+-  ``FVP_RD_N1Edge`` (Version 11.3 build 42)
+-  ``Foundation_Platform``
+
+The latest version of the AArch32 build of TF-A has been tested on the
+following Arm FVPs without shifted affinities, and that do not support threaded
+CPU cores (64-bit host machine only).
+
+-  ``FVP_Base_AEMv8A-AEMv8A``
+-  ``FVP_Base_Cortex-A32x4``
+
+.. note::
+   The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities.
+
+The *Foundation* and *Base* FVPs can be downloaded free of charge. See the
+`Arm FVP website`_.
+
+All the above platforms have been tested with `Linaro Release 19.06`_.
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*
+
+.. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php
+.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms
+.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06
diff --git a/docs/plat/marvell/porting.rst b/docs/plat/marvell/porting.rst
index 8fc1c1f..0a71dbd 100644
--- a/docs/plat/marvell/porting.rst
+++ b/docs/plat/marvell/porting.rst
@@ -112,7 +112,7 @@
 
     .. seealso::
         For XFI/SFI comphy type there is procedure "rx_training" which eases
-        process of suiting some of the parameters. Please see :ref:`uboot_cmd`
+        process of suiting some of the parameters. Please see *uboot_cmd*
         section: rx_training.
 
     The PHY porting layer simplifies updating static values per board type,
diff --git a/docs/plat/meson-g12a.rst b/docs/plat/meson-g12a.rst
index 1021da4..7cd1bf7 100644
--- a/docs/plat/meson-g12a.rst
+++ b/docs/plat/meson-g12a.rst
@@ -1,5 +1,5 @@
 Amlogic Meson S905X2 (G12A)
-==========================
+===========================
 
 The Amlogic Meson S905X2 is a SoC with a quad core Arm Cortex-A53 running at
 ~1.8GHz. It also contains a Cortex-M3 used as SCP.
diff --git a/docs/process/coding-guidelines.rst b/docs/process/coding-guidelines.rst
index a53da77..cb8b892 100644
--- a/docs/process/coding-guidelines.rst
+++ b/docs/process/coding-guidelines.rst
@@ -23,8 +23,8 @@
 
 - ``**WARNING: Use of volatile is usually wrong``: see
   `Why the “volatile” type class should not be used`_ . Although this document
-  contains some very useful information, there are several legimate uses of the
-  volatile keyword within the TF codebase.
+  contains some very useful information, there are several legitimate uses of
+  the volatile keyword within the TF codebase.
 
 Headers and inclusion
 ---------------------
diff --git a/docs/process/index.rst b/docs/process/index.rst
index a870c8f..9c12de8 100644
--- a/docs/process/index.rst
+++ b/docs/process/index.rst
@@ -6,7 +6,6 @@
    :caption: Contents
    :numbered:
 
-   release-information
    security
    platform-compatibility-policy
    coding-guidelines
diff --git a/docs/process/release-information.rst b/docs/process/release-information.rst
deleted file mode 100644
index e264e51..0000000
--- a/docs/process/release-information.rst
+++ /dev/null
@@ -1,82 +0,0 @@
-Release Processes
-=================
-
-Project Release Cadence
------------------------
-
-The project currently aims to do a release once every 6 months which will be
-tagged on the master branch. There will be a code freeze (stop merging
-non-essential PRs) up to 4 weeks prior to the target release date. The release
-candidates will start appearing after this and only bug fixes or updates
-required for the release will be merged. The maintainers are free to use their
-judgement on what PRs are essential for the release. A release branch may be
-created after code freeze if there are significant PRs that need merging onto
-the integration branch during the merge window.
-
-The release testing will be performed on release candidates and depending on
-issues found, additional release candidates may be created to fix the issues.
-
-::
-
-                            |<----------6 months---------->|
-            |<---4 weeks--->|              |<---4 weeks--->|
-       +-----------------------------------------------------------> time
-            |               |              |               |
-         code freeze       ver w.x       code freeze     ver y.z
-
-
-Upcoming Releases
-~~~~~~~~~~~~~~~~~
-
-These are the estimated dates for the upcoming release. These may change
-depending on project requirement and partner feedback.
-
-+-----------------+---------------------------+------------------------------+
-| Release Version |  Target Date              | Expected Code Freeze         |
-+=================+===========================+==============================+
-| v2.0            | 1st week of Oct '18       | 1st week of Sep '18          |
-+-----------------+---------------------------+------------------------------+
-| v2.1            | 5th week of Mar '19       | 1st week of Mar '19          |
-+-----------------+---------------------------+------------------------------+
-
-Removal of Deprecated Interfaces
---------------------------------
-
-As mentioned in the :ref:`Platform Compatibility Policy`, this is a live
-document cataloging all the deprecated interfaces in TF-A project and the
-Release version after which it will be removed.
-
-+--------------------------------+-------------+---------+---------------------------------------------------------+
-| Interface                      | Deprecation | Removed | Comments                                                |
-|                                | Date        | after   |                                                         |
-|                                |             | Release |                                                         |
-+================================+=============+=========+=========================================================+
-| Legacy Console API             | Jan '18     | v2.1    | Deprecated in favour of ``MULTI_CONSOLE_API``           |
-+--------------------------------+-------------+---------+---------------------------------------------------------+
-| Weak default                   | Oct '18     | v2.1    | The default implementations are defined in              |
-| ``plat_crash_console_*``       |             |         | ``crash_console_helpers.S``. The platforms have to      |
-| APIs                           |             |         | define ``plat_crash_console_*``.                        |
-+--------------------------------+-------------+---------+---------------------------------------------------------+
-| ``finish_console_register``    | Oct '18     | v2.1    | The old version of the macro is deprecated. See commit  |
-| macro in                       |             |         | cc5859c_ for more details.                              |
-| ``MULTI_CONSOLE_API``          |             |         |                                                         |
-+--------------------------------+-------------+---------+---------------------------------------------------------+
-| Types ``tzc_action_t`` and     | Oct '18     | v2.1    | Using logical operations such as OR in enumerations     |
-| ``tzc_region_attributes_t``    |             |         | goes against the MISRA guidelines.                      |
-+--------------------------------+-------------+---------+---------------------------------------------------------+
-| Macro ``EL_IMPLEMENTED()``     | Oct '18     | v2.1    | Deprecated in favour of ``el_implemented()``.           |
-+--------------------------------+-------------+---------+---------------------------------------------------------+
-| ``get_afflvl_shift()``,        | Dec '18     | v2.1    | Removed.                                                |
-| ``mpidr_mask_lower_afflvls()``,|             |         |                                                         |
-| and ``eret()``.                |             |         |                                                         |
-+--------------------------------+-------------+---------+---------------------------------------------------------+
-| Extra include paths in the     | Jan '18     | v2.1    | Now it is needed to use the full path of the common     |
-| Makefile in ``INCLUDES``.      |             |         | header files. More information in commit 09d40e0e0828_. |
-+--------------------------------+-------------+---------+---------------------------------------------------------+
-
---------------
-
-*Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.*
-
-.. _cc5859c: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=cc5859ca19ff546c35eb0331000dae090b6eabcf
-.. _09d40e0e0828: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=09d40e0e08283a249e7dce0e106c07c5141f9b7e
diff --git a/docs/security_advisories/security-advisory-tfv-6.rst b/docs/security_advisories/security-advisory-tfv-6.rst
index 495eddd..9eeaeec 100644
--- a/docs/security_advisories/security-advisory-tfv-6.rst
+++ b/docs/security_advisories/security-advisory-tfv-6.rst
@@ -51,7 +51,7 @@
 For Cortex-A73 and Cortex-A75 CPUs, the PRs in this advisory invalidate the
 branch predictor when entering EL3 by temporarily dropping into AArch32
 Secure-EL1 and executing the ``BPIALL`` instruction. This workaround is
-signifiantly more complex than the "MMU disable/enable" workaround. The latter
+significantly more complex than the "MMU disable/enable" workaround. The latter
 is not effective at invalidating the branch predictor on Cortex-A73/Cortex-A75.
 
 Note that if other privileged software, for example a Rich OS kernel, implements
diff --git a/drivers/arm/pl011/aarch32/pl011_console.S b/drivers/arm/pl011/aarch32/pl011_console.S
index e1e346c..05c8250 100644
--- a/drivers/arm/pl011/aarch32/pl011_console.S
+++ b/drivers/arm/pl011/aarch32/pl011_console.S
@@ -57,7 +57,7 @@
 #if (ARM_ARCH_MAJOR == 7) && !defined(ARMV7_SUPPORTS_VIRTUALIZATION)
 	push	{r0,r3}
 	softudiv	r0,r1,r2,r3
-	mov	r1, r0
+	mov	r2, r0
 	pop	{r0,r3}
 #else
 	udiv	r2, r1, r2
diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h
index ea7181e..6fe67a9 100644
--- a/include/lib/cpus/aarch64/cortex_a53.h
+++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -76,8 +76,8 @@
 /*******************************************************************************
  * Helper function to access a53_cpuectlr_el1 register on Cortex-A53 CPUs
  ******************************************************************************/
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
 DEFINE_RENAME_SYSREG_RW_FUNCS(a53_cpuectlr_el1, CORTEX_A53_ECTLR_EL1)
-#endif
+#endif /* __ASSEMBLER__ */
 
 #endif /* CORTEX_A53_H */
diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h
index fb4f1ec..271a333 100644
--- a/include/lib/cpus/aarch64/cortex_a73.h
+++ b/include/lib/cpus/aarch64/cortex_a73.h
@@ -38,8 +38,8 @@
 /*******************************************************************************
  * Helper function to access a73_cpuectlr_el1 register on Cortex-A73 CPUs
  ******************************************************************************/
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
 DEFINE_RENAME_SYSREG_RW_FUNCS(a73_cpuectlr_el1, CORTEX_A73_CPUECTLR_EL1)
-#endif
+#endif /* __ASSEMBLER__ */
 
 #endif /* CORTEX_A73_H */
diff --git a/lib/xlat_tables_v2/xlat_tables_utils.c b/lib/xlat_tables_v2/xlat_tables_utils.c
index 232142e..30babc6 100644
--- a/lib/xlat_tables_v2/xlat_tables_utils.c
+++ b/lib/xlat_tables_v2/xlat_tables_utils.c
@@ -551,7 +551,7 @@
 		 * before writing the new descriptor.
 		 */
 		*entry = INVALID_DESC;
-#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
+#if !HW_ASSISTED_COHERENCY
 		dccvac((uintptr_t)entry);
 #endif
 		/* Invalidate any cached copy of this mapping in the TLBs. */
@@ -562,7 +562,7 @@
 
 		/* Write new descriptor */
 		*entry = xlat_desc(ctx, new_attr, addr_pa, level);
-#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
+#if !HW_ASSISTED_COHERENCY
 		dccvac((uintptr_t)entry);
 #endif
 		base_va += PAGE_SIZE;