Fix RTC base register
- We were using the base register for MT6397 instead of MT6392.
Change-Id: I7ee15f00c69f70b8c9808093af1b248ddcc0f2b1
diff --git a/plat/mediatek/mt8516/drivers/rtc/rtc.h b/plat/mediatek/mt8516/drivers/rtc/rtc.h
index 9c4ca49..9223cad 100644
--- a/plat/mediatek/mt8516/drivers/rtc/rtc.h
+++ b/plat/mediatek/mt8516/drivers/rtc/rtc.h
@@ -7,28 +7,43 @@
#ifndef RTC_H
#define RTC_H
+#define RTC_BASE_MT6392 0x8000
+#define RTC_BASE_MT6397 0xE000
+
+#if defined(RTC_MT6392) && defined(RTC_MT6397)
+#error "Only define one of RTC_MT6392 or RTC_MT6397!"
+#endif
+
+#if defined(RTC_MT6392)
+#define RTC_BASE RTC_BASE_MT6392
+#elif defined(RTC_MT6397)
+#define RTC_BASE RTC_BASE_MT6397
+#else
+#error "Please select an RTC!"
+#endif
+
/* RTC registers */
enum {
- RTC_BBPU = 0xE000,
- RTC_IRQ_STA = 0xE002,
- RTC_IRQ_EN = 0xE004,
- RTC_CII_EN = 0xE006
+ RTC_BBPU = RTC_BASE + 0x00,
+ RTC_IRQ_STA = RTC_BASE + 0x02,
+ RTC_IRQ_EN = RTC_BASE + 0x04,
+ RTC_CII_EN = RTC_BASE + 0x06
};
enum {
- RTC_OSC32CON = 0xE026,
- RTC_CON = 0xE03E,
- RTC_WRTGR = 0xE03C
+ RTC_OSC32CON = RTC_BASE + 0x26,
+ RTC_CON = RTC_BASE + 0x3E,
+ RTC_WRTGR = RTC_BASE + 0x3C
};
enum {
- RTC_PDN1 = 0xE02C,
- RTC_PDN2 = 0xE02E,
- RTC_SPAR0 = 0xE030,
- RTC_SPAR1 = 0xE032,
- RTC_PROT = 0xE036,
- RTC_DIFF = 0xE038,
- RTC_CALI = 0xE03A
+ RTC_PDN1 = RTC_BASE + 0x2C,
+ RTC_PDN2 = RTC_BASE + 0x2E,
+ RTC_SPAR0 = RTC_BASE + 0x30,
+ RTC_SPAR1 = RTC_BASE + 0x32,
+ RTC_PROT = RTC_BASE + 0x36,
+ RTC_DIFF = RTC_BASE + 0x38,
+ RTC_CALI = RTC_BASE + 0x3A
};
enum {
diff --git a/plat/mediatek/mt8516/platform.mk b/plat/mediatek/mt8516/platform.mk
index 70a0414..3a9c576 100644
--- a/plat/mediatek/mt8516/platform.mk
+++ b/plat/mediatek/mt8516/platform.mk
@@ -61,5 +61,7 @@
$(eval $(call add_define,MTK_SIP_SET_AUTHORIZED_SECURE_REG_ENABLE))
+$(eval $(call add_define,RTC_MT6392))
+
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0