tree 6a33c0a28c429705fcc976f2addae8c758dc8098
parent d1b6013d8485094d948e6b6039b8d119a907ecf8
author Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> 1565924894 +0800
committer Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> 1566183391 +0800

intel: agilex: Clear PLL lostlock bypass mode

To provide glitchless clock to downstream logic even if clock toggles

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1