diff --git a/docs/conf.py b/docs/conf.py
index b267de0..a100241 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -15,9 +15,6 @@
 
 project = 'Trusted Firmware-A'
 
-version = '2.1'
-release = version # We don't need these to be distinct
-
 # -- General configuration ---------------------------------------------------
 
 # Add any Sphinx extension module names here, as strings. They can be
diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst
index c7359ad..3dd23e5 100644
--- a/docs/getting_started/user-guide.rst
+++ b/docs/getting_started/user-guide.rst
@@ -188,8 +188,6 @@
       `Summary of build options`_ for more information on available build
       options.
 
-   -  (AArch32 only) Currently only ``PLAT=fvp`` is supported.
-
    -  (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
       corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp_min, is
       provided by TF-A to demonstrate how PSCI Library can be integrated with
@@ -1360,7 +1358,7 @@
        make [DEBUG=1] [V=1] fiptool
 
        # Unpack firmware images from Linaro FIP
-       ./tools/fiptool/fiptool unpack <path-to-linaro-release>/fip.bin
+       ./tools/fiptool/fiptool unpack <path-to-linaro-release>/[SOFTWARE]/fip.bin
 
    The unpack operation will result in a set of binary images extracted to the
    current working directory. The SCP_BL2 image corresponds to
@@ -1407,7 +1405,7 @@
 
       .. code:: shell
 
-          export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
+          export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-eabi-
 
    -  Build BL32 in AArch32.
 
diff --git a/docs/index.rst b/docs/index.rst
index 3cdb2b2..4cd1798 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -154,7 +154,7 @@
 (64-bit host machine only).
 
 .. note::
-   The FVP models used are Version 11.5 Build 33, unless otherwise stated.
+   The FVP models used are Version 11.6 Build 45, unless otherwise stated.
 
 -  ``FVP_Base_AEMv8A-AEMv8A``
 -  ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h
index ea7181e..6fe67a9 100644
--- a/include/lib/cpus/aarch64/cortex_a53.h
+++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -76,8 +76,8 @@
 /*******************************************************************************
  * Helper function to access a53_cpuectlr_el1 register on Cortex-A53 CPUs
  ******************************************************************************/
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
 DEFINE_RENAME_SYSREG_RW_FUNCS(a53_cpuectlr_el1, CORTEX_A53_ECTLR_EL1)
-#endif
+#endif /* __ASSEMBLER__ */
 
 #endif /* CORTEX_A53_H */
diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h
index fb4f1ec..271a333 100644
--- a/include/lib/cpus/aarch64/cortex_a73.h
+++ b/include/lib/cpus/aarch64/cortex_a73.h
@@ -38,8 +38,8 @@
 /*******************************************************************************
  * Helper function to access a73_cpuectlr_el1 register on Cortex-A73 CPUs
  ******************************************************************************/
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
 DEFINE_RENAME_SYSREG_RW_FUNCS(a73_cpuectlr_el1, CORTEX_A73_CPUECTLR_EL1)
-#endif
+#endif /* __ASSEMBLER__ */
 
 #endif /* CORTEX_A73_H */