diff --git a/bl1/aarch32/bl1_context_mgmt.c b/bl1/aarch32/bl1_context_mgmt.c
index 005d046..b5a6a34 100644
--- a/bl1/aarch32/bl1_context_mgmt.c
+++ b/bl1/aarch32/bl1_context_mgmt.c
@@ -102,7 +102,7 @@
  ******************************************************************************/
 void bl1_prepare_next_image(unsigned int image_id)
 {
-	unsigned int security_state;
+	unsigned int security_state, mode = MODE32_svc;
 	image_desc_t *image_desc;
 	entry_point_info_t *next_bl_ep;
 
@@ -117,20 +117,13 @@
 	security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
 
 	/* Prepare the SPSR for the next BL image. */
-	if (security_state == SECURE) {
-		next_bl_ep->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
-			SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
-	} else {
-		/* Use HYP mode if supported else use SVC. */
-		if (GET_VIRT_EXT(read_id_pfr1())) {
-			next_bl_ep->spsr = SPSR_MODE32(MODE32_hyp, SPSR_T_ARM,
-				SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
-		} else {
-			next_bl_ep->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
-				SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
-		}
+	if ((security_state != SECURE) && (GET_VIRT_EXT(read_id_pfr1()))) {
+		mode = MODE32_hyp;
 	}
 
+	next_bl_ep->spsr = SPSR_MODE32(mode, SPSR_T_ARM,
+				SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
+
 	/* Allow platform to make change */
 	bl1_plat_set_ep_info(image_id, next_bl_ep);
 
diff --git a/bl1/aarch64/bl1_context_mgmt.c b/bl1/aarch64/bl1_context_mgmt.c
index 0326319..8be8830 100644
--- a/bl1/aarch64/bl1_context_mgmt.c
+++ b/bl1/aarch64/bl1_context_mgmt.c
@@ -42,7 +42,7 @@
  ******************************************************************************/
 void bl1_prepare_next_image(unsigned int image_id)
 {
-	unsigned int security_state;
+	unsigned int security_state, mode = MODE_EL1;
 	image_desc_t *image_desc;
 	entry_point_info_t *next_bl_ep;
 
@@ -73,20 +73,13 @@
 		cm_set_context(&bl1_cpu_context[security_state], security_state);
 
 	/* Prepare the SPSR for the next BL image. */
-	if (security_state == SECURE) {
-		next_bl_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
-				   DISABLE_ALL_EXCEPTIONS);
-	} else {
-		/* Use EL2 if supported; else use EL1. */
-		if (el_implemented(2) != EL_IMPL_NONE) {
-			next_bl_ep->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
-				DISABLE_ALL_EXCEPTIONS);
-		} else {
-			next_bl_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
-			   DISABLE_ALL_EXCEPTIONS);
-		}
+	if ((security_state != SECURE) && (el_implemented(2) != EL_IMPL_NONE)) {
+		mode = MODE_EL2;
 	}
 
+	next_bl_ep->spsr = SPSR_64(mode, MODE_SP_ELX,
+		DISABLE_ALL_EXCEPTIONS);
+
 	/* Allow platform to make change */
 	bl1_plat_set_ep_info(image_id, next_bl_ep);
 
diff --git a/common/desc_image_load.c b/common/desc_image_load.c
index 405bb83..f2e8f60 100644
--- a/common/desc_image_load.c
+++ b/common/desc_image_load.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,6 +9,7 @@
 #include <arch_helpers.h>
 #include <common/bl_common.h>
 #include <common/desc_image_load.h>
+#include <common/tbbr/tbbr_img_def.h>
 
 static bl_load_info_t bl_load_info;
 static bl_params_t next_bl_params;
@@ -275,3 +276,47 @@
 		}
 	}
 }
+
+/*******************************************************************************
+ * Helper to extract BL32/BL33 entry point info from arg0 passed to BL31, for
+ * platforms that are only interested in those. Platforms that need to extract
+ * more information can parse the structures themselves.
+ ******************************************************************************/
+
+void bl31_params_parse_helper(u_register_t param,
+			      entry_point_info_t *bl32_ep_info_out,
+			      entry_point_info_t *bl33_ep_info_out)
+{
+	bl_params_node_t *node;
+	bl_params_t *v2 = (void *)(uintptr_t)param;
+
+#if !ERROR_DEPRECATED
+	if (v2->h.version == PARAM_VERSION_1) {
+		struct { /* Deprecated version 1 parameter structure. */
+			param_header_t h;
+			image_info_t *bl31_image_info;
+			entry_point_info_t *bl32_ep_info;
+			image_info_t *bl32_image_info;
+			entry_point_info_t *bl33_ep_info;
+			image_info_t *bl33_image_info;
+		} *v1 = (void *)(uintptr_t)param;
+		assert(v1->h.type == PARAM_BL31);
+		if (bl32_ep_info_out)
+			*bl32_ep_info_out = *v1->bl32_ep_info;
+		if (bl33_ep_info_out)
+			*bl33_ep_info_out = *v1->bl33_ep_info;
+		return;
+	}
+#endif /* !ERROR_DEPRECATED */
+
+	assert(v2->h.version == PARAM_VERSION_2);
+	assert(v2->h.type == PARAM_BL_PARAMS);
+	for (node = v2->head; node; node = node->next_params_info) {
+		if (node->image_id == BL32_IMAGE_ID)
+			if (bl32_ep_info_out)
+				*bl32_ep_info_out = *node->ep_info;
+		if (node->image_id == BL33_IMAGE_ID)
+			if (bl33_ep_info_out)
+				*bl33_ep_info_out = *node->ep_info;
+	}
+}
diff --git a/docs/components/romlib-design.rst b/docs/components/romlib-design.rst
index a70ed17..d8bc89c 100644
--- a/docs/components/romlib-design.rst
+++ b/docs/components/romlib-design.rst
@@ -42,7 +42,7 @@
 
 ::
 
-    reserved    reserved
+    reserved
 
 The reserved spaces can be used to add more functions in the future without
 affecting the order and location of functions already existing in the jump
@@ -71,29 +71,41 @@
 The "library at ROM" contains a necessary init function that initialises the
 global variables defined by the functions inside "library at ROM".
 
-Scripts
-~~~~~~~
+Script
+~~~~~~
 
-There are several scripts that generate the necessary files for the "library at
-ROM" to work:
+There is a ``romlib_generate.py`` Python script that generates the necessary
+files for the "library at ROM" to work. It implements multiple functions:
 
-1. ``gentbl.sh`` - Generates the jump table by parsing the index file.
+1. ``romlib_generate.py gentbl [args]`` - Generates the jump table by parsing
+   the index file.
 
-2. ``genvar.sh`` - Generates the jump table global variable (**not** the jump
-   table itself) with the absolute address in ROM. This global variable is,
-   basically, a pointer to the jump table.
+2. ``romlib_generator.py genvar [args]`` - Generates the jump table global
+   variable (**not** the jump table itself) with the absolute address in ROM.
+   This global variable is, basically, a pointer to the jump table.
 
-3. ``genwrappers.sh`` - Generates a wrapper function for each entry in the index
-   file except for the ones that contain the keyword ``patch``. The generated
-   wrapper file is called ``<lib>_<fn_name>.S``.
+3. ``romlib_generator.py genwrappers [args]`` - Generates a wrapper function for
+   each entry in the index file except for the ones that contain the keyword
+   ``patch``. The generated wrapper file is called ``<fn_name>.s``.
+
+4. ``romlib_generator.py pre [args]`` - Preprocesses the index file which means
+   it resolves all the include commands in the file recursively. It can also
+   generate a dependency file of the included index files which can be directly
+   used in makefiles.
+
+Each ``romlib_generate.py`` function has its own manual which is accessible by
+runing ``romlib_generator.py [function] --help``.
+
+``romlib_generate.py`` requires Python 3 environment.
+
 
 Patching of functions in library at ROM
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-The ``genwrappers.sh`` script does not generate wrappers for the entries in the
-index file that contain the keyword ``patch``. Thus, it allows calling the
-function from the actual library by breaking the link to the  "library at ROM"
-version of this function.
+The ``romlib_generator.py genwrappers`` does not generate wrappers for the
+entries in the index file that contain the keyword ``patch``. Thus, it allows
+calling the function from the actual library by breaking the link to the
+"library at ROM" version of this function.
 
 The calling sequence for a patched function is as follows:
 
@@ -117,12 +129,6 @@
     USE_ROMLIB=1                                                    \
     all fip
 
-Known issue
------------
-When building library at ROM, a clean build is always required. This is
-necessary when changes are made to the index files, e.g. adding new functions,
-patching existing ones etc.
-
 --------------
 
 *Copyright (c) 2019, Arm Limited. All rights reserved.*
diff --git a/drivers/auth/cryptocell/cryptocell_crypto.c b/drivers/auth/cryptocell/712/cryptocell_crypto.c
similarity index 94%
rename from drivers/auth/cryptocell/cryptocell_crypto.c
rename to drivers/auth/cryptocell/712/cryptocell_crypto.c
index a507d0a..395c550 100644
--- a/drivers/auth/cryptocell/cryptocell_crypto.c
+++ b/drivers/auth/cryptocell/712/cryptocell_crypto.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,19 +11,19 @@
 
 #include <arch_helpers.h>
 #include <common/debug.h>
-#include <drivers/arm/cryptocell/crypto_driver.h>
-#include <drivers/arm/cryptocell/rsa.h>
-#include <drivers/arm/cryptocell/sbrom_bsv_api.h>
-#include <drivers/arm/cryptocell/secureboot_base_func.h>
-#include <drivers/arm/cryptocell/secureboot_gen_defs.h>
-#include <drivers/arm/cryptocell/util.h>
+#include <drivers/arm/cryptocell/712/crypto_driver.h>
+#include <drivers/arm/cryptocell/712/rsa.h>
+#include <drivers/arm/cryptocell/712/sbrom_bsv_api.h>
+#include <drivers/arm/cryptocell/712/secureboot_base_func.h>
+#include <drivers/arm/cryptocell/712/secureboot_gen_defs.h>
+#include <drivers/arm/cryptocell/712/util.h>
 #include <drivers/auth/crypto_mod.h>
 #include <drivers/auth/mbedtls/mbedtls_common.h>
 #include <lib/utils.h>
 
 #include <mbedtls/oid.h>
 
-#define LIB_NAME		"CryptoCell SBROM"
+#define LIB_NAME		"CryptoCell 712 SBROM"
 #define RSA_SALT_LEN		32
 #define RSA_EXPONENT		65537
 
@@ -303,4 +303,3 @@
  */
 REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash);
 
-
diff --git a/drivers/auth/cryptocell/712/cryptocell_plat_helpers.c b/drivers/auth/cryptocell/712/cryptocell_plat_helpers.c
new file mode 100644
index 0000000..53d77db
--- /dev/null
+++ b/drivers/auth/cryptocell/712/cryptocell_plat_helpers.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stddef.h>
+#include <string.h>
+
+#include <platform_def.h>
+
+#include <plat/common/platform.h>
+#include <tools_share/tbbr_oid.h>
+
+#include <common/debug.h>
+#include <drivers/arm/cryptocell/712/sbrom_bsv_api.h>
+#include <drivers/arm/cryptocell/712/nvm.h>
+#include <drivers/arm/cryptocell/712/nvm_otp.h>
+
+/*
+ * Return the ROTPK hash
+ *
+ * dst:   buffer into which the ROTPK hash will be copied into
+ * len:   length of the provided buffer, which must be at least enough for a
+ *        SHA256 hash
+ * flags: a pointer to integer that will be set to indicate the ROTPK status
+ *
+ * Return: 0 = success, Otherwise = error
+ */
+int cc_get_rotpk_hash(unsigned char *dst, unsigned int len, unsigned int *flags)
+{
+	CCError_t error;
+	uint32_t lcs;
+
+	assert(dst != NULL);
+	assert(len >= HASH_RESULT_SIZE_IN_WORDS);
+	assert(flags != NULL);
+
+	error = NVM_GetLCS(PLAT_CRYPTOCELL_BASE, &lcs);
+	if (error != CC_OK)
+		return 1;
+
+	/* If the lifecycle state is `SD`, return failure */
+	if (lcs == CC_BSV_SECURITY_DISABLED_LCS)
+		return 1;
+
+	/*
+	 * If the lifecycle state is `CM` or `DM`, ROTPK shouldn't be verified.
+	 * Return success after setting ROTPK_NOT_DEPLOYED flag
+	 */
+	if ((lcs == CC_BSV_CHIP_MANUFACTURE_LCS) ||
+			(lcs == CC_BSV_DEVICE_MANUFACTURE_LCS)) {
+		*flags = ROTPK_NOT_DEPLOYED;
+		return 0;
+	}
+
+	/* Copy the DER header */
+	error = NVM_ReadHASHPubKey(PLAT_CRYPTOCELL_BASE,
+			CC_SB_HASH_BOOT_KEY_256B,
+			(uint32_t *)dst, HASH_RESULT_SIZE_IN_WORDS);
+	if (error != CC_OK)
+		return 1;
+
+	*flags = ROTPK_IS_HASH;
+	return 0;
+}
+
+/*
+ * Return the non-volatile counter value stored in the platform. The cookie
+ * specifies the OID of the counter in the certificate.
+ *
+ * Return: 0 = success, Otherwise = error
+ */
+int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
+{
+	CCError_t error = CC_FAIL;
+
+	if (strcmp(cookie, TRUSTED_FW_NVCOUNTER_OID) == 0) {
+		error = NVM_GetSwVersion(PLAT_CRYPTOCELL_BASE,
+				CC_SW_VERSION_COUNTER1, nv_ctr);
+	} else if (strcmp(cookie, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) {
+		error = NVM_GetSwVersion(PLAT_CRYPTOCELL_BASE,
+				CC_SW_VERSION_COUNTER2, nv_ctr);
+	}
+
+	return (error != CC_OK);
+}
+
+/*
+ * Store a new non-volatile counter value in the counter specified by the OID
+ * in the cookie. This function is not expected to be called if the Lifecycle
+ * state is RMA as the values in the certificate are expected to always match
+ * the nvcounter values. But if called when the LCS is RMA, the underlying
+ * helper functions will return success but without updating the counter.
+ *
+ * Return: 0 = success, Otherwise = error
+ */
+int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
+{
+	CCError_t error = CC_FAIL;
+
+	if (strcmp(cookie, TRUSTED_FW_NVCOUNTER_OID) == 0) {
+		error = NVM_SetSwVersion(PLAT_CRYPTOCELL_BASE,
+				CC_SW_VERSION_COUNTER1, nv_ctr);
+	} else if (strcmp(cookie, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) {
+		error = NVM_SetSwVersion(PLAT_CRYPTOCELL_BASE,
+				CC_SW_VERSION_COUNTER2, nv_ctr);
+	}
+
+	return (error != CC_OK);
+}
+
diff --git a/drivers/auth/cryptocell/cryptocell_crypto.mk b/drivers/auth/cryptocell/cryptocell_crypto.mk
index a631829..d42a2e7 100644
--- a/drivers/auth/cryptocell/cryptocell_crypto.mk
+++ b/drivers/auth/cryptocell/cryptocell_crypto.mk
@@ -17,10 +17,20 @@
   $(error Error: CCSBROM_LIB_PATH not set)
 endif
 
+CRYPTOCELL_VERSION ?= 712
+ifeq (${CRYPTOCELL_VERSION},712)
+  CCSBROM_LIB_FILENAME := cc_712sbromx509
+else
+  $(error Error: CRYPTOCELL_VERSION set to invalid version)
+endif
+
+CRYPTOCELL_SRC_DIR	:= drivers/auth/cryptocell/${CRYPTOCELL_VERSION}/
+
+CRYPTOCELL_SOURCES	:= ${CRYPTOCELL_SRC_DIR}/cryptocell_crypto.c \
+			   ${CRYPTOCELL_SRC_DIR}/cryptocell_plat_helpers.c
+
 TF_LDFLAGS		+= -L$(CCSBROM_LIB_PATH)
-LDLIBS			+= -lcc_712sbromx509
+LDLIBS			+= -l$(CCSBROM_LIB_FILENAME)
 
-CRYPTOCELL_SOURCES	:=	drivers/auth/cryptocell/cryptocell_crypto.c
-
-BL1_SOURCES		+=	${CRYPTOCELL_SOURCES}
-BL2_SOURCES		+=	${CRYPTOCELL_SOURCES}
+BL1_SOURCES		+= ${CRYPTOCELL_SOURCES}
+BL2_SOURCES		+= ${CRYPTOCELL_SOURCES}
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h
index 0db4145..34036d7 100644
--- a/include/arch/aarch32/arch.h
+++ b/include/arch/aarch32/arch.h
@@ -294,6 +294,8 @@
 #define SPSR_MODE_SHIFT		U(0)
 #define SPSR_MODE_MASK		U(0x7)
 
+#define SPSR_SSBS_BIT		BIT_32(23)
+
 #define DISABLE_ALL_EXCEPTIONS \
 		(SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT)
 
@@ -384,11 +386,12 @@
 #define GET_M32(mode)		(((mode) >> MODE32_SHIFT) & MODE32_MASK)
 
 #define SPSR_MODE32(mode, isa, endian, aif)		\
-	(MODE_RW_32 << MODE_RW_SHIFT |			\
+	((MODE_RW_32 << MODE_RW_SHIFT |			\
 	((mode) & MODE32_MASK) << MODE32_SHIFT |	\
 	((isa) & SPSR_T_MASK) << SPSR_T_SHIFT |		\
 	((endian) & SPSR_E_MASK) << SPSR_E_SHIFT |	\
-	((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
+	((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) &	\
+	(~(SPSR_SSBS_BIT)))
 
 /*
  * TTBR definitions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index e4147d7..fa857fb 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -419,6 +419,9 @@
 #define SPSR_M_AARCH64		U(0x0)
 #define SPSR_M_AARCH32		U(0x1)
 
+#define SPSR_SSBS_BIT_AARCH64	BIT_64(12)
+#define SPSR_SSBS_BIT_AARCH32	BIT_64(23)
+
 #define DISABLE_ALL_EXCEPTIONS \
 		(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
 
@@ -543,18 +546,20 @@
 #define GET_SP(mode)		(((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
 #define GET_M32(mode)		(((mode) >> MODE32_SHIFT) & MODE32_MASK)
 
-#define SPSR_64(el, sp, daif)				\
-	((MODE_RW_64 << MODE_RW_SHIFT) |		\
-	(((el) & MODE_EL_MASK) << MODE_EL_SHIFT) |	\
-	(((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) |	\
-	(((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT))
+#define SPSR_64(el, sp, daif)					\
+	(((MODE_RW_64 << MODE_RW_SHIFT) |			\
+	(((el) & MODE_EL_MASK) << MODE_EL_SHIFT) |		\
+	(((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) |		\
+	(((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) &	\
+	(~(SPSR_SSBS_BIT_AARCH64)))
 
 #define SPSR_MODE32(mode, isa, endian, aif)		\
-	((MODE_RW_32 << MODE_RW_SHIFT) |		\
+	(((MODE_RW_32 << MODE_RW_SHIFT) |		\
 	(((mode) & MODE32_MASK) << MODE32_SHIFT) |	\
 	(((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) |	\
 	(((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) |	\
-	(((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT))
+	(((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) &	\
+	(~(SPSR_SSBS_BIT_AARCH32)))
 
 /*
  * TTBR Definitions
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index 457dc2a..eb96df0 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -11,6 +11,14 @@
 #include <common/param_header.h>
 #include <lib/utils_def.h>
 
+#ifndef __ASSEMBLY__
+#include <stddef.h>
+#include <stdint.h>
+#include <lib/cassert.h>
+#endif /* __ASSEMBLY__ */
+
+#include <export/common/bl_common_exp.h>
+
 #define UP	U(1)
 #define DOWN	U(0)
 
@@ -21,22 +29,6 @@
 #define TOP	U(0x1)
 #define BOTTOM	U(0x0)
 
-/*
- * The following are used for image state attributes.
- * Image can only be in one of the following state.
- */
-#define IMAGE_STATE_RESET		U(0)
-#define IMAGE_STATE_COPIED		U(1)
-#define IMAGE_STATE_COPYING		U(2)
-#define IMAGE_STATE_AUTHENTICATED	U(3)
-#define IMAGE_STATE_EXECUTED		U(4)
-#define IMAGE_STATE_INTERRUPTED		U(5)
-
-#define IMAGE_ATTRIB_SKIP_LOADING	U(0x02)
-#define IMAGE_ATTRIB_PLAT_SETUP		U(0x04)
-
-#define INVALID_IMAGE_ID		U(0xFFFFFFFF)
-
 /*******************************************************************************
  * Constants to indicate type of exception to the common exception handler.
  ******************************************************************************/
@@ -101,11 +93,6 @@
 
 #ifndef __ASSEMBLY__
 
-#include <stddef.h>
-#include <stdint.h>
-
-#include <lib/cassert.h>
-
 /*
  * Declarations of linker defined symbols to help determine memory layout of
  * BL images
@@ -165,66 +152,6 @@
 	size_t total_size;
 } meminfo_t;
 
-/*****************************************************************************
- * Image info binary provides information from the image loader that
- * can be used by the firmware to manage available trusted RAM.
- * More advanced firmware image formats can provide additional
- * information that enables optimization or greater flexibility in the
- * common firmware code
- *****************************************************************************/
-typedef struct image_info {
-	param_header_t h;
-	uintptr_t image_base;   /* physical address of base of image */
-	uint32_t image_size;    /* bytes read from image file */
-	uint32_t image_max_size;
-} image_info_t;
-
-/*****************************************************************************
- * The image descriptor struct definition.
- *****************************************************************************/
-typedef struct image_desc {
-	/* Contains unique image id for the image. */
-	unsigned int image_id;
-	/*
-	 * This member contains Image state information.
-	 * Refer IMAGE_STATE_XXX defined above.
-	 */
-	unsigned int state;
-	uint32_t copied_size;	/* image size copied in blocks */
-	image_info_t image_info;
-	entry_point_info_t ep_info;
-} image_desc_t;
-
-/* BL image node in the BL image loading sequence */
-typedef struct bl_load_info_node {
-	unsigned int image_id;
-	image_info_t *image_info;
-	struct bl_load_info_node *next_load_info;
-} bl_load_info_node_t;
-
-/* BL image head node in the BL image loading sequence */
-typedef struct bl_load_info {
-	param_header_t h;
-	bl_load_info_node_t *head;
-} bl_load_info_t;
-
-/* BL image node in the BL image execution sequence */
-typedef struct bl_params_node {
-	unsigned int image_id;
-	image_info_t *image_info;
-	entry_point_info_t *ep_info;
-	struct bl_params_node *next_params_info;
-} bl_params_node_t;
-
-/*
- * BL image head node in the BL image execution sequence
- * It is also used to pass information to next BL image.
- */
-typedef struct bl_params {
-	param_header_t h;
-	bl_params_node_t *head;
-} bl_params_t;
-
 /*******************************************************************************
  * Function & variable prototypes
  ******************************************************************************/
diff --git a/include/common/desc_image_load.h b/include/common/desc_image_load.h
index e46eb27..b044f3e 100644
--- a/include/common/desc_image_load.h
+++ b/include/common/desc_image_load.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -40,4 +40,9 @@
 bl_params_t *get_next_bl_params_from_mem_params_desc(void);
 void populate_next_bl_params_config(bl_params_t *bl2_to_next_bl_params);
 
+/* Helper to extract BL32/BL33 entry point info from arg0 passed to BL31. */
+void bl31_params_parse_helper(u_register_t param,
+			      entry_point_info_t *bl32_ep_info_out,
+			      entry_point_info_t *bl33_ep_info_out);
+
 #endif /* DESC_IMAGE_LOAD_H */
diff --git a/include/common/ep_info.h b/include/common/ep_info.h
index a09d03b..6cb903e 100644
--- a/include/common/ep_info.h
+++ b/include/common/ep_info.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,104 +8,29 @@
 #define EP_INFO_H
 
 #include <common/param_header.h>
-#include <lib/utils_def.h>
-
-#define SECURE		U(0x0)
-#define NON_SECURE	U(0x1)
-#define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE))
-
-/*******************************************************************************
- * Constants that allow assembler code to access members of and the
- * 'entry_point_info' structure at their correct offsets.
- ******************************************************************************/
-#define ENTRY_POINT_INFO_PC_OFFSET	U(0x08)
-#ifdef AARCH32
-#define ENTRY_POINT_INFO_LR_SVC_OFFSET	U(0x10)
-#define ENTRY_POINT_INFO_ARGS_OFFSET	U(0x14)
-#else
-#define ENTRY_POINT_INFO_ARGS_OFFSET	U(0x18)
-#endif
-
-/* The following are used to set/get image attributes. */
-#define PARAM_EP_SECURITY_MASK		U(0x1)
-
-/* Secure or Non-secure image */
-#define GET_SECURITY_STATE(x) ((x) & PARAM_EP_SECURITY_MASK)
-#define SET_SECURITY_STATE(x, security) \
-			((x) = ((x) & ~PARAM_EP_SECURITY_MASK) | (security))
-
-/* Endianness of the image. */
-#define EP_EE_MASK		U(0x2)
-#define EP_EE_SHIFT		U(1)
-#define EP_EE_LITTLE		U(0x0)
-#define EP_EE_BIG		U(0x2)
-#define EP_GET_EE(x)		((x) & EP_EE_MASK)
-#define EP_SET_EE(x, ee)	((x) = ((x) & ~EP_EE_MASK) | (ee))
-
-/* Enable or disable access to the secure timer from secure images. */
-#define EP_ST_MASK		U(0x4)
-#define EP_ST_DISABLE		U(0x0)
-#define EP_ST_ENABLE		U(0x4)
-#define EP_GET_ST(x)		((x) & EP_ST_MASK)
-#define EP_SET_ST(x, ee)	((x) = ((x) & ~EP_ST_MASK) | (ee))
-
-/* Determine if an image is executable or not. */
-#define EP_EXE_MASK		U(0x8)
-#define NON_EXECUTABLE		U(0x0)
-#define EXECUTABLE		U(0x8)
-#define EP_GET_EXE(x)		((x) & EP_EXE_MASK)
-#define EP_SET_EXE(x, ee)	((x) = ((x) & ~EP_EXE_MASK) | (ee))
-
-/* Flag to indicate the first image that is executed. */
-#define EP_FIRST_EXE_MASK	U(0x10)
-#define EP_FIRST_EXE		U(0x10)
-#define EP_GET_FIRST_EXE(x)	((x) & EP_FIRST_EXE_MASK)
-#define EP_SET_FIRST_EXE(x, ee)	((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee))
 
 #ifndef __ASSEMBLY__
-
 #include <stdint.h>
-
 #include <lib/cassert.h>
+#endif /* __ASSEMBLY__ */
 
-typedef struct aapcs64_params {
-	u_register_t arg0;
-	u_register_t arg1;
-	u_register_t arg2;
-	u_register_t arg3;
-	u_register_t arg4;
-	u_register_t arg5;
-	u_register_t arg6;
-	u_register_t arg7;
-} aapcs64_params_t;
+#include <export/common/ep_info_exp.h>
 
-typedef struct aapcs32_params {
-	u_register_t arg0;
-	u_register_t arg1;
-	u_register_t arg2;
-	u_register_t arg3;
-} aapcs32_params_t;
+#define SECURE		EP_SECURE
+#define NON_SECURE	EP_NON_SECURE
+#define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE))
 
-/*****************************************************************************
- * This structure represents the superset of information needed while
- * switching exception levels. The only two mechanisms to do so are
- * ERET & SMC. Security state is indicated using bit zero of header
- * attribute
- * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start
- * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while
- * processing SMC to jump to BL31.
- *****************************************************************************/
-typedef struct entry_point_info {
-	param_header_t h;
-	uintptr_t pc;
-	uint32_t spsr;
-#ifdef AARCH32
-	uintptr_t lr_svc;
-	aapcs32_params_t args;
-#else
-	aapcs64_params_t args;
-#endif
-} entry_point_info_t;
+#define PARAM_EP_SECURITY_MASK	EP_SECURITY_MASK
+
+#define NON_EXECUTABLE	EP_NON_EXECUTABLE
+#define EXECUTABLE	EP_EXECUTABLE
+
+/* Secure or Non-secure image */
+#define GET_SECURITY_STATE(x) ((x) & EP_SECURITY_MASK)
+#define SET_SECURITY_STATE(x, security) \
+			((x) = ((x) & ~EP_SECURITY_MASK) | (security))
+
+#ifndef __ASSEMBLY__
 
 /*
  * Compile time assertions related to the 'entry_point_info' structure to
diff --git a/include/common/param_header.h b/include/common/param_header.h
index 0c1503f..b885286 100644
--- a/include/common/param_header.h
+++ b/include/common/param_header.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,20 +9,14 @@
 
 #include <stdbool.h>
 
-#include <lib/utils_def.h>
+#ifndef __ASSEMBLY__
+#include <stdint.h>
+#endif /*__ASSEMBLY__*/
 
-/* Param header types */
-#define PARAM_EP			U(0x01)
-#define PARAM_IMAGE_BINARY		U(0x02)
-#define PARAM_BL31			U(0x03)
-#define PARAM_BL_LOAD_INFO		U(0x04)
-#define PARAM_BL_PARAMS			U(0x05)
-#define PARAM_PSCI_LIB_ARGS		U(0x06)
-#define PARAM_SP_IMAGE_BOOT_INFO	U(0x07)
+#include <export/common/param_header_exp.h>
 
-/* Param header version */
-#define VERSION_1	U(0x01)
-#define VERSION_2	U(0x02)
+#define VERSION_1	PARAM_VERSION_1
+#define VERSION_2	PARAM_VERSION_2
 
 #define SET_PARAM_HEAD(_p, _type, _ver, _attr) do { \
 	(_p)->h.type = (uint8_t)(_type); \
@@ -38,21 +32,4 @@
 	._p.h.size = (uint16_t)sizeof(_p_type), \
 	._p.h.attr = (uint32_t)(_attr)
 
-#ifndef __ASSEMBLY__
-
-#include <stdint.h>
-
-/***************************************************************************
- * This structure provides version information and the size of the
- * structure, attributes for the structure it represents
- ***************************************************************************/
-typedef struct param_header {
-	uint8_t type;		/* type of the structure */
-	uint8_t version;    /* version of this structure */
-	uint16_t size;      /* size of this structure in bytes */
-	uint32_t attr;      /* attributes: unused bits SBZ */
-} param_header_t;
-
-#endif /*__ASSEMBLY__*/
-
 #endif /* PARAM_HEADER_H */
diff --git a/include/common/tbbr/tbbr_img_def.h b/include/common/tbbr/tbbr_img_def.h
index 672886d..1701995 100644
--- a/include/common/tbbr/tbbr_img_def.h
+++ b/include/common/tbbr/tbbr_img_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,83 +7,6 @@
 #ifndef TBBR_IMG_DEF_H
 #define TBBR_IMG_DEF_H
 
-#include <lib/utils_def.h>
-
-/* Firmware Image Package */
-#define FIP_IMAGE_ID			U(0)
-
-/* Trusted Boot Firmware BL2 */
-#define BL2_IMAGE_ID			U(1)
-
-/* SCP Firmware SCP_BL2 */
-#define SCP_BL2_IMAGE_ID		U(2)
-
-/* EL3 Runtime Firmware BL31 */
-#define BL31_IMAGE_ID			U(3)
-
-/* Secure Payload BL32 (Trusted OS) */
-#define BL32_IMAGE_ID			U(4)
-
-/* Non-Trusted Firmware BL33 */
-#define BL33_IMAGE_ID			U(5)
-
-/* Certificates */
-#define TRUSTED_BOOT_FW_CERT_ID		U(6)
-#define TRUSTED_KEY_CERT_ID		U(7)
-
-#define SCP_FW_KEY_CERT_ID		U(8)
-#define SOC_FW_KEY_CERT_ID		U(9)
-#define TRUSTED_OS_FW_KEY_CERT_ID	U(10)
-#define NON_TRUSTED_FW_KEY_CERT_ID	U(11)
-
-#define SCP_FW_CONTENT_CERT_ID		U(12)
-#define SOC_FW_CONTENT_CERT_ID		U(13)
-#define TRUSTED_OS_FW_CONTENT_CERT_ID	U(14)
-#define NON_TRUSTED_FW_CONTENT_CERT_ID	U(15)
-
-/* Non-Trusted ROM Firmware NS_BL1U */
-#define NS_BL1U_IMAGE_ID		U(16)
-
-/* Trusted FWU Certificate */
-#define FWU_CERT_ID			U(17)
-
-/* Trusted FWU SCP Firmware SCP_BL2U */
-#define SCP_BL2U_IMAGE_ID		U(18)
-
-/* Trusted FWU Boot Firmware BL2U */
-#define BL2U_IMAGE_ID			U(19)
-
-/* Non-Trusted FWU Firmware NS_BL2U */
-#define NS_BL2U_IMAGE_ID		U(20)
-
-/* Secure Payload BL32_EXTRA1 (Trusted OS Extra1) */
-#define BL32_EXTRA1_IMAGE_ID		U(21)
-
-/* Secure Payload BL32_EXTRA2 (Trusted OS Extra2) */
-#define BL32_EXTRA2_IMAGE_ID		U(22)
-
-/* HW_CONFIG (e.g. Kernel DT) */
-#define HW_CONFIG_ID			U(23)
-
-/* TB_FW_CONFIG */
-#define TB_FW_CONFIG_ID			U(24)
-
-/* SOC_FW_CONFIG */
-#define SOC_FW_CONFIG_ID		U(25)
-
-/* TOS_FW_CONFIG */
-#define TOS_FW_CONFIG_ID		U(26)
-
-/* NT_FW_CONFIG */
-#define NT_FW_CONFIG_ID			U(27)
-
-/* GPT Partition */
-#define GPT_IMAGE_ID			U(28)
-
-/* Binary with STM32 header */
-#define STM32_IMAGE_ID			U(29)
-
-/* Define size of the array */
-#define MAX_NUMBER_IDS			U(30)
+#include <export/common/tbbr/tbbr_img_def_exp.h>
 
 #endif /* TBBR_IMG_DEF_H */
diff --git a/include/drivers/arm/cryptocell/cc_crypto_boot_defs.h b/include/drivers/arm/cryptocell/712/cc_crypto_boot_defs.h
similarity index 100%
rename from include/drivers/arm/cryptocell/cc_crypto_boot_defs.h
rename to include/drivers/arm/cryptocell/712/cc_crypto_boot_defs.h
diff --git a/include/drivers/arm/cryptocell/cc_pal_sb_plat.h b/include/drivers/arm/cryptocell/712/cc_pal_sb_plat.h
similarity index 100%
rename from include/drivers/arm/cryptocell/cc_pal_sb_plat.h
rename to include/drivers/arm/cryptocell/712/cc_pal_sb_plat.h
diff --git a/include/drivers/arm/cryptocell/cc_pal_types.h b/include/drivers/arm/cryptocell/712/cc_pal_types.h
similarity index 100%
rename from include/drivers/arm/cryptocell/cc_pal_types.h
rename to include/drivers/arm/cryptocell/712/cc_pal_types.h
diff --git a/include/drivers/arm/cryptocell/cc_pal_types_plat.h b/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h
similarity index 100%
rename from include/drivers/arm/cryptocell/cc_pal_types_plat.h
rename to include/drivers/arm/cryptocell/712/cc_pal_types_plat.h
diff --git a/include/drivers/arm/cryptocell/cc_sec_defs.h b/include/drivers/arm/cryptocell/712/cc_sec_defs.h
similarity index 100%
rename from include/drivers/arm/cryptocell/cc_sec_defs.h
rename to include/drivers/arm/cryptocell/712/cc_sec_defs.h
diff --git a/include/drivers/arm/cryptocell/crypto_driver.h b/include/drivers/arm/cryptocell/712/crypto_driver.h
similarity index 100%
rename from include/drivers/arm/cryptocell/crypto_driver.h
rename to include/drivers/arm/cryptocell/712/crypto_driver.h
diff --git a/include/drivers/arm/cryptocell/nvm.h b/include/drivers/arm/cryptocell/712/nvm.h
similarity index 100%
rename from include/drivers/arm/cryptocell/nvm.h
rename to include/drivers/arm/cryptocell/712/nvm.h
diff --git a/include/drivers/arm/cryptocell/nvm_otp.h b/include/drivers/arm/cryptocell/712/nvm_otp.h
similarity index 100%
rename from include/drivers/arm/cryptocell/nvm_otp.h
rename to include/drivers/arm/cryptocell/712/nvm_otp.h
diff --git a/include/drivers/arm/cryptocell/rsa.h b/include/drivers/arm/cryptocell/712/rsa.h
similarity index 100%
rename from include/drivers/arm/cryptocell/rsa.h
rename to include/drivers/arm/cryptocell/712/rsa.h
diff --git a/include/drivers/arm/cryptocell/sbrom_bsv_api.h b/include/drivers/arm/cryptocell/712/sbrom_bsv_api.h
similarity index 100%
rename from include/drivers/arm/cryptocell/sbrom_bsv_api.h
rename to include/drivers/arm/cryptocell/712/sbrom_bsv_api.h
diff --git a/include/drivers/arm/cryptocell/secureboot_base_func.h b/include/drivers/arm/cryptocell/712/secureboot_base_func.h
similarity index 100%
rename from include/drivers/arm/cryptocell/secureboot_base_func.h
rename to include/drivers/arm/cryptocell/712/secureboot_base_func.h
diff --git a/include/drivers/arm/cryptocell/secureboot_gen_defs.h b/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h
similarity index 100%
rename from include/drivers/arm/cryptocell/secureboot_gen_defs.h
rename to include/drivers/arm/cryptocell/712/secureboot_gen_defs.h
diff --git a/include/drivers/arm/cryptocell/util.h b/include/drivers/arm/cryptocell/712/util.h
similarity index 100%
rename from include/drivers/arm/cryptocell/util.h
rename to include/drivers/arm/cryptocell/712/util.h
diff --git a/include/drivers/arm/cryptocell/cc_rotpk.h b/include/drivers/arm/cryptocell/cc_rotpk.h
new file mode 100644
index 0000000..9398496
--- /dev/null
+++ b/include/drivers/arm/cryptocell/cc_rotpk.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CC_ROTPK_H
+#define _CC_ROTPK_H
+
+int cc_get_rotpk_hash(unsigned char *dst, unsigned int len,
+		      unsigned int *flags);
+
+#endif
diff --git a/include/drivers/gpio.h b/include/drivers/gpio.h
index bef62f7..99c18a4 100644
--- a/include/drivers/gpio.h
+++ b/include/drivers/gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,15 +7,17 @@
 #ifndef GPIO_H
 #define GPIO_H
 
-#define GPIO_DIR_OUT		0
-#define GPIO_DIR_IN		1
+#include <export/drivers/gpio_exp.h>
 
-#define GPIO_LEVEL_LOW		0
-#define GPIO_LEVEL_HIGH		1
+#define GPIO_DIR_OUT		ARM_TF_GPIO_DIR_OUT
+#define GPIO_DIR_IN		ARM_TF_GPIO_DIR_IN
 
-#define GPIO_PULL_NONE		0
-#define GPIO_PULL_UP		1
-#define GPIO_PULL_DOWN		2
+#define GPIO_LEVEL_LOW		ARM_TF_GPIO_LEVEL_LOW
+#define GPIO_LEVEL_HIGH		ARM_TF_GPIO_LEVEL_HIGH
+
+#define GPIO_PULL_NONE		ARM_TF_GPIO_PULL_NONE
+#define GPIO_PULL_UP		ARM_TF_GPIO_PULL_UP
+#define GPIO_PULL_DOWN		ARM_TF_GPIO_PULL_DOWN
 
 typedef struct gpio_ops {
 	int (*get_direction)(int gpio);
diff --git a/include/export/README b/include/export/README
new file mode 100644
index 0000000..2de8d6b
--- /dev/null
+++ b/include/export/README
@@ -0,0 +1,33 @@
+All headers under include/export/ are export headers that are intended for
+inclusion in third-party code which needs to interact with TF-A data structures
+or interfaces. They must follow these special rules:
+
+- Header guards should start with ARM_TRUSTED_FIRMWARE_ to reduce clash risk.
+
+- All definitions should be sufficiently namespaced (e.g. with BL_ or TF_) to
+  make name clashes with third-party code unlikely.
+
+- They must not #include any headers except other export headers, and those
+  includes must use relative paths with "../double_quotes.h" notation.
+
+- They must not rely on any type definitions other that <stdint.h> types defined
+  in the ISO C standard (i.e. uint64_t is fine, but not u_register_t). They
+  should still not #include <stdint.h>. Instead, wrapper headers including
+  export headers need to ensure that they #include <stdint.h> earlier in their
+  include order.
+
+- They must not rely on any macro definitions other than those which are
+  pre-defined by all common compilers (e.g. __ASSEMBLER__ or __aarch64__).
+
+- They must only contain macro, type and structure definitions, no prototypes.
+
+- They should avoid using integer types with architecture-dependent widths
+  (e.g. long, uintptr_t, pointer types) where possible. (Some existing export
+  headers are violating this for now.)
+
+- Their names should always end in "_exp.h".
+
+- Normal TF-A code should never include export headers directly. Instead, it
+  should include a wrapper header that ensures the export header is included in
+  the right manner. (The wrapper header for include/export/x/y/z_exp.h should
+  normally be placed at include/x/y/z.h.)
diff --git a/include/export/common/bl_common_exp.h b/include/export/common/bl_common_exp.h
new file mode 100644
index 0000000..8f09017
--- /dev/null
+++ b/include/export/common/bl_common_exp.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_BL_COMMON_EXP_H
+#define ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_BL_COMMON_EXP_H
+
+/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
+
+#include "ep_info_exp.h"
+#include "tbbr/tbbr_img_def_exp.h"
+
+/*
+ * The following are used for image state attributes.
+ * Image can only be in one of the following state.
+ */
+#define IMAGE_STATE_RESET		U(0)
+#define IMAGE_STATE_COPIED		U(1)
+#define IMAGE_STATE_COPYING		U(2)
+#define IMAGE_STATE_AUTHENTICATED	U(3)
+#define IMAGE_STATE_EXECUTED		U(4)
+#define IMAGE_STATE_INTERRUPTED		U(5)
+
+#define IMAGE_ATTRIB_SKIP_LOADING	U(0x02)
+#define IMAGE_ATTRIB_PLAT_SETUP		U(0x04)
+
+#define INVALID_IMAGE_ID		U(0xFFFFFFFF)
+
+#ifndef __ASSEMBLER__
+
+/*****************************************************************************
+ * Image info binary provides information from the image loader that
+ * can be used by the firmware to manage available trusted RAM.
+ * More advanced firmware image formats can provide additional
+ * information that enables optimization or greater flexibility in the
+ * common firmware code
+ *****************************************************************************/
+typedef struct image_info {
+	param_header_t h;
+	uintptr_t image_base;   /* physical address of base of image */
+	uint32_t image_size;    /* bytes read from image file */
+	uint32_t image_max_size;
+} image_info_t;
+
+/* BL image node in the BL image execution sequence */
+typedef struct bl_params_node {
+	unsigned int image_id;
+	image_info_t *image_info;
+	entry_point_info_t *ep_info;
+	struct bl_params_node *next_params_info;
+} bl_params_node_t;
+
+/*
+ * BL image head node in the BL image execution sequence
+ * It is also used to pass information to next BL image.
+ */
+typedef struct bl_params {
+	param_header_t h;
+	bl_params_node_t *head;
+} bl_params_t;
+
+/*****************************************************************************
+ * The image descriptor struct definition.
+ *****************************************************************************/
+typedef struct image_desc {
+	/* Contains unique image id for the image. */
+	unsigned int image_id;
+	/*
+	 * This member contains Image state information.
+	 * Refer IMAGE_STATE_XXX defined above.
+	 */
+	unsigned int state;
+	uint32_t copied_size;	/* image size copied in blocks */
+	image_info_t image_info;
+	entry_point_info_t ep_info;
+} image_desc_t;
+
+/* BL image node in the BL image loading sequence */
+typedef struct bl_load_info_node {
+	unsigned int image_id;
+	image_info_t *image_info;
+	struct bl_load_info_node *next_load_info;
+} bl_load_info_node_t;
+
+/* BL image head node in the BL image loading sequence */
+typedef struct bl_load_info {
+	param_header_t h;
+	bl_load_info_node_t *head;
+} bl_load_info_t;
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_BL_COMMON_EXP_H */
diff --git a/include/export/common/ep_info_exp.h b/include/export/common/ep_info_exp.h
new file mode 100644
index 0000000..4c703e6
--- /dev/null
+++ b/include/export/common/ep_info_exp.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_EP_INFO_EXP_H
+#define ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_EP_INFO_EXP_H
+
+/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
+
+#include "../lib/utils_def_exp.h"
+#include "param_header_exp.h"
+
+/*******************************************************************************
+ * Constants that allow assembler code to access members of and the
+ * 'entry_point_info' structure at their correct offsets.
+ ******************************************************************************/
+#define ENTRY_POINT_INFO_PC_OFFSET	U(0x08)
+#ifdef __aarch64__
+#define ENTRY_POINT_INFO_ARGS_OFFSET	U(0x18)
+#else
+#define ENTRY_POINT_INFO_LR_SVC_OFFSET	U(0x10)
+#define ENTRY_POINT_INFO_ARGS_OFFSET	U(0x14)
+#endif
+
+/* Security state of the image. */
+#define EP_SECURITY_MASK	U(0x1)
+#define EP_SECURITY_SHIFT	U(0)
+#define EP_SECURE		U(0x0)
+#define EP_NON_SECURE		U(0x1)
+
+/* Endianness of the image. */
+#define EP_EE_MASK		U(0x2)
+#define EP_EE_SHIFT		U(1)
+#define EP_EE_LITTLE		U(0x0)
+#define EP_EE_BIG		U(0x2)
+#define EP_GET_EE(x)		((x) & EP_EE_MASK)
+#define EP_SET_EE(x, ee)	((x) = ((x) & ~EP_EE_MASK) | (ee))
+
+/* Enable or disable access to the secure timer from secure images. */
+#define EP_ST_MASK		U(0x4)
+#define EP_ST_SHIFT		U(2)
+#define EP_ST_DISABLE		U(0x0)
+#define EP_ST_ENABLE		U(0x4)
+#define EP_GET_ST(x)		((x) & EP_ST_MASK)
+#define EP_SET_ST(x, ee)	((x) = ((x) & ~EP_ST_MASK) | (ee))
+
+/* Determine if an image is executable or not. */
+#define EP_EXE_MASK		U(0x8)
+#define EP_EXE_SHIFT		U(3)
+#define EP_NON_EXECUTABLE	U(0x0)
+#define EP_EXECUTABLE		U(0x8)
+#define EP_GET_EXE(x)		((x) & EP_EXE_MASK)
+#define EP_SET_EXE(x, ee)	((x) = ((x) & ~EP_EXE_MASK) | (ee))
+
+/* Flag to indicate the first image that is executed. */
+#define EP_FIRST_EXE_MASK	U(0x10)
+#define EP_FIRST_EXE_SHIFT	U(4)
+#define EP_FIRST_EXE		U(0x10)
+#define EP_GET_FIRST_EXE(x)	((x) & EP_FIRST_EXE_MASK)
+#define EP_SET_FIRST_EXE(x, ee)	((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee))
+
+#ifndef __ASSEMBLER__
+
+typedef struct aapcs64_params {
+	uint64_t arg0;
+	uint64_t arg1;
+	uint64_t arg2;
+	uint64_t arg3;
+	uint64_t arg4;
+	uint64_t arg5;
+	uint64_t arg6;
+	uint64_t arg7;
+} aapcs64_params_t;
+
+typedef struct aapcs32_params {
+	uint32_t arg0;
+	uint32_t arg1;
+	uint32_t arg2;
+	uint32_t arg3;
+} aapcs32_params_t;
+
+/*****************************************************************************
+ * This structure represents the superset of information needed while
+ * switching exception levels. The only two mechanisms to do so are
+ * ERET & SMC. Security state is indicated using bit zero of header
+ * attribute
+ * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start
+ * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while
+ * processing SMC to jump to BL31.
+ *****************************************************************************/
+typedef struct entry_point_info {
+	param_header_t h;
+	uintptr_t pc;
+	uint32_t spsr;
+#ifdef __aarch64__
+	aapcs64_params_t args;
+#else
+	uintptr_t lr_svc;
+	aapcs32_params_t args;
+#endif
+} entry_point_info_t;
+
+#endif /*__ASSEMBLER__*/
+
+#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_EP_INFO_EXP_H */
diff --git a/include/export/common/param_header_exp.h b/include/export/common/param_header_exp.h
new file mode 100644
index 0000000..15bb6f2
--- /dev/null
+++ b/include/export/common/param_header_exp.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_PARAM_HEADER_EXP_H
+#define ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_PARAM_HEADER_EXP_H
+
+/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
+
+#include "../lib/utils_def_exp.h"
+
+/* Param header types */
+#define PARAM_EP			U(0x01)
+#define PARAM_IMAGE_BINARY		U(0x02)
+#define PARAM_BL31			U(0x03)
+#define PARAM_BL_LOAD_INFO		U(0x04)
+#define PARAM_BL_PARAMS			U(0x05)
+#define PARAM_PSCI_LIB_ARGS		U(0x06)
+#define PARAM_SP_IMAGE_BOOT_INFO	U(0x07)
+
+/* Param header version */
+#define PARAM_VERSION_1			U(0x01)
+#define PARAM_VERSION_2			U(0x02)
+
+#ifndef __ASSEMBLER__
+
+/***************************************************************************
+ * This structure provides version information and the size of the
+ * structure, attributes for the structure it represents
+ ***************************************************************************/
+typedef struct param_header {
+	uint8_t type;		/* type of the structure */
+	uint8_t version;	/* version of this structure */
+	uint16_t size;		/* size of this structure in bytes */
+	uint32_t attr;		/* attributes: unused bits SBZ */
+} param_header_t;
+
+#endif /*__ASSEMBLER__*/
+
+#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_PARAM_HEADER_EXP_H */
diff --git a/include/export/common/tbbr/tbbr_img_def_exp.h b/include/export/common/tbbr/tbbr_img_def_exp.h
new file mode 100644
index 0000000..ff0d16c
--- /dev/null
+++ b/include/export/common/tbbr/tbbr_img_def_exp.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_TBBR_TBBR_IMG_DEF_EXP_H
+#define ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_TBBR_TBBR_IMG_DEF_EXP_H
+
+/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
+
+#include "../../lib/utils_def_exp.h"
+
+/* Firmware Image Package */
+#define FIP_IMAGE_ID			U(0)
+
+/* Trusted Boot Firmware BL2 */
+#define BL2_IMAGE_ID			U(1)
+
+/* SCP Firmware SCP_BL2 */
+#define SCP_BL2_IMAGE_ID		U(2)
+
+/* EL3 Runtime Firmware BL31 */
+#define BL31_IMAGE_ID			U(3)
+
+/* Secure Payload BL32 (Trusted OS) */
+#define BL32_IMAGE_ID			U(4)
+
+/* Non-Trusted Firmware BL33 */
+#define BL33_IMAGE_ID			U(5)
+
+/* Certificates */
+#define TRUSTED_BOOT_FW_CERT_ID		U(6)
+#define TRUSTED_KEY_CERT_ID		U(7)
+
+#define SCP_FW_KEY_CERT_ID		U(8)
+#define SOC_FW_KEY_CERT_ID		U(9)
+#define TRUSTED_OS_FW_KEY_CERT_ID	U(10)
+#define NON_TRUSTED_FW_KEY_CERT_ID	U(11)
+
+#define SCP_FW_CONTENT_CERT_ID		U(12)
+#define SOC_FW_CONTENT_CERT_ID		U(13)
+#define TRUSTED_OS_FW_CONTENT_CERT_ID	U(14)
+#define NON_TRUSTED_FW_CONTENT_CERT_ID	U(15)
+
+/* Non-Trusted ROM Firmware NS_BL1U */
+#define NS_BL1U_IMAGE_ID		U(16)
+
+/* Trusted FWU Certificate */
+#define FWU_CERT_ID			U(17)
+
+/* Trusted FWU SCP Firmware SCP_BL2U */
+#define SCP_BL2U_IMAGE_ID		U(18)
+
+/* Trusted FWU Boot Firmware BL2U */
+#define BL2U_IMAGE_ID			U(19)
+
+/* Non-Trusted FWU Firmware NS_BL2U */
+#define NS_BL2U_IMAGE_ID		U(20)
+
+/* Secure Payload BL32_EXTRA1 (Trusted OS Extra1) */
+#define BL32_EXTRA1_IMAGE_ID		U(21)
+
+/* Secure Payload BL32_EXTRA2 (Trusted OS Extra2) */
+#define BL32_EXTRA2_IMAGE_ID		U(22)
+
+/* HW_CONFIG (e.g. Kernel DT) */
+#define HW_CONFIG_ID			U(23)
+
+/* TB_FW_CONFIG */
+#define TB_FW_CONFIG_ID			U(24)
+
+/* SOC_FW_CONFIG */
+#define SOC_FW_CONFIG_ID		U(25)
+
+/* TOS_FW_CONFIG */
+#define TOS_FW_CONFIG_ID		U(26)
+
+/* NT_FW_CONFIG */
+#define NT_FW_CONFIG_ID			U(27)
+
+/* GPT Partition */
+#define GPT_IMAGE_ID			U(28)
+
+/* Binary with STM32 header */
+#define STM32_IMAGE_ID			U(29)
+
+/* Define size of the array */
+#define MAX_NUMBER_IDS			U(30)
+
+#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_TBBR_TBBR_IMG_DEF_EXP_H */
diff --git a/include/export/drivers/gpio_exp.h b/include/export/drivers/gpio_exp.h
new file mode 100644
index 0000000..a37f190
--- /dev/null
+++ b/include/export/drivers/gpio_exp.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_DRIVERS_GPIO_EXP_H
+#define ARM_TRUSTED_FIRMWARE_EXPORT_DRIVERS_GPIO_EXP_H
+
+/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
+
+#define ARM_TF_GPIO_DIR_OUT		0
+#define ARM_TF_GPIO_DIR_IN		1
+
+#define ARM_TF_GPIO_LEVEL_LOW		0
+#define ARM_TF_GPIO_LEVEL_HIGH		1
+
+#define ARM_TF_GPIO_PULL_NONE		0
+#define ARM_TF_GPIO_PULL_UP		1
+#define ARM_TF_GPIO_PULL_DOWN		2
+
+#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_DRIVERS_GPIO_EXP_H */
diff --git a/include/export/lib/bl_aux_params/bl_aux_params_exp.h b/include/export/lib/bl_aux_params/bl_aux_params_exp.h
new file mode 100644
index 0000000..7391dec
--- /dev/null
+++ b/include/export/lib/bl_aux_params/bl_aux_params_exp.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_LIB_BL_AUX_PARAMS_EXP_H
+#define ARM_TRUSTED_FIRMWARE_EXPORT_LIB_BL_AUX_PARAMS_EXP_H
+
+/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
+
+#include "../../drivers/gpio_exp.h"
+
+/*
+ * This API implements a lightweight parameter passing mechanism that can be
+ * used to pass SoC Firmware configuration data from BL2 to BL31 by platforms or
+ * configurations that do not want to depend on libfdt. It is structured as a
+ * singly-linked list of parameter structures that all share the same common
+ * header but may have different (and differently-sized) structure bodies after
+ * that. The header contains a type field to indicate the parameter type (which
+ * is used to infer the structure length and how to interpret its contents) and
+ * a next pointer which contains the absolute physical address of the next
+ * parameter structure. The next pointer in the last structure block is set to
+ * NULL. The picture below shows how the parameters are kept in memory.
+ *
+ * head of list  ---> +----------------+ --+
+ *                    |      type      |   |
+ *                    +----------------+   |--> struct bl_aux_param
+ *               +----|      next      |   |
+ *               |    +----------------+ --+
+ *               |    | parameter data |
+ *               |    +----------------+
+ *               |
+ *               +--> +----------------+ --+
+ *                    |      type      |   |
+ *                    +----------------+   |--> struct bl_aux_param
+ *           NULL <---|      next      |   |
+ *                    +----------------+ --+
+ *                    | parameter data |
+ *                    +----------------+
+ *
+ * Note: The SCTLR_EL3.A bit (Alignment fault check enable) is set in TF-A, so
+ * BL2 must ensure that each parameter struct starts on a 64-bit aligned address
+ * to avoid alignment faults. Parameters may be allocated in any address range
+ * accessible at the time of BL31 handoff (e.g. SRAM, DRAM, SoC-internal scratch
+ * registers, etc.), in particular address ranges that may not be mapped in
+ * BL31's page tables, so the parameter list must be parsed before the MMU is
+ * enabled and any information that is required at a later point should be
+ * deep-copied out into BL31-internal data structures.
+ */
+
+enum bl_aux_param_type {
+	BL_AUX_PARAM_NONE = 0,
+	BL_AUX_PARAM_VENDOR_SPECIFIC_FIRST = 0x1,
+	/* 0x1 - 0x7fffffff can be used by vendor-specific handlers. */
+	BL_AUX_PARAM_VENDOR_SPECIFIC_LAST = 0x7fffffff,
+	BL_AUX_PARAM_GENERIC_FIRST = 0x80000001,
+	BL_AUX_PARAM_COREBOOT_TABLE = BL_AUX_PARAM_GENERIC_FIRST,
+	/* 0x80000001 - 0xffffffff are reserved for the generic handler. */
+	BL_AUX_PARAM_GENERIC_LAST = 0xffffffff,
+	/* Top 32 bits of the type field are reserved for future use. */
+};
+
+/* common header for all BL aux parameters */
+struct bl_aux_param_header {
+	uint64_t type;
+	uint64_t next;
+};
+
+/* commonly useful parameter structures that can be shared by multiple types */
+struct bl_aux_param_uint64 {
+	struct bl_aux_param_header h;
+	uint64_t value;
+};
+
+struct bl_aux_gpio_info {
+	uint8_t polarity;
+	uint8_t direction;
+	uint8_t pull_mode;
+	uint8_t reserved;
+	uint32_t index;
+};
+
+struct bl_aux_param_gpio {
+	struct bl_aux_param_header h;
+	struct bl_aux_gpio_info gpio;
+};
+
+#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_LIB_BL_AUX_PARAMS_EXP_H */
diff --git a/include/export/lib/utils_def_exp.h b/include/export/lib/utils_def_exp.h
new file mode 100644
index 0000000..86c409c
--- /dev/null
+++ b/include/export/lib/utils_def_exp.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef	ARM_TRUSTED_FIRMWARE_EXPORT_LIB_UTILS_DEF_EXP_H
+#define	ARM_TRUSTED_FIRMWARE_EXPORT_LIB_UTILS_DEF_EXP_H
+
+/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
+
+/*
+ * For those constants to be shared between C and other sources, apply a 'U',
+ * 'UL', 'ULL', 'L' or 'LL' suffix to the argument only in C, to avoid
+ * undefined or unintended behaviour.
+ *
+ * The GNU assembler and linker do not support these suffixes (it causes the
+ * build process to fail) therefore the suffix is omitted when used in linker
+ * scripts and assembler files.
+*/
+#if defined(__ASSEMBLER__)
+# define   U(_x)	(_x)
+# define  UL(_x)	(_x)
+# define ULL(_x)	(_x)
+# define   L(_x)	(_x)
+# define  LL(_x)	(_x)
+#else
+# define   U(_x)	(_x##U)
+# define  UL(_x)	(_x##UL)
+# define ULL(_x)	(_x##ULL)
+# define   L(_x)	(_x##L)
+# define  LL(_x)	(_x##LL)
+#endif
+
+#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_LIB_UTILS_DEF_EXP_H */
diff --git a/include/export/plat/rockchip/common/plat_params_exp.h b/include/export/plat/rockchip/common/plat_params_exp.h
new file mode 100644
index 0000000..ccc9cd9
--- /dev/null
+++ b/include/export/plat/rockchip/common/plat_params_exp.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_PLAT_ROCKCHIP_COMMON_PLAT_PARAMS_EXP_H
+#define ARM_TRUSTED_FIRMWARE_EXPORT_PLAT_ROCKCHIP_COMMON_PLAT_PARAMS_EXP_H
+
+/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
+
+#include "../../../lib/bl_aux_params/bl_aux_params_exp.h"
+
+/* param type */
+enum bl_aux_rk_param_type {
+	BL_AUX_PARAM_RK_RESET_GPIO = BL_AUX_PARAM_VENDOR_SPECIFIC_FIRST,
+	BL_AUX_PARAM_RK_POWEROFF_GPIO,
+	BL_AUX_PARAM_RK_SUSPEND_GPIO,
+	BL_AUX_PARAM_RK_SUSPEND_APIO,
+};
+
+struct bl_aux_rk_apio_info {
+	uint8_t apio1 : 1;
+	uint8_t apio2 : 1;
+	uint8_t apio3 : 1;
+	uint8_t apio4 : 1;
+	uint8_t apio5 : 1;
+};
+
+struct bl_aux_param_rk_apio {
+	struct bl_aux_param_header h;
+	struct bl_aux_rk_apio_info apio;
+};
+
+#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_PLAT_ROCKCHIP_COMMON_PLAT_PARAMS_EXP_H */
diff --git a/include/lib/bl_aux_params/bl_aux_params.h b/include/lib/bl_aux_params/bl_aux_params.h
new file mode 100644
index 0000000..f6ce802
--- /dev/null
+++ b/include/lib/bl_aux_params/bl_aux_params.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef LIB_BL_AUX_PARAMS_H
+#define LIB_BL_AUX_PARAMS_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <export/lib/bl_aux_params/bl_aux_params_exp.h>
+
+/*
+ * Handler function that handles an individual aux parameter. Return true if
+ * the parameter was handled, and flase if bl_aux_params_parse() should make its
+ * own attempt at handling it (for generic parameters).
+ */
+typedef bool (*bl_aux_param_handler_t)(struct bl_aux_param_header *param);
+
+/*
+ * Interprets head as the start of an aux parameter list, and passes the
+ * parameters individually to handler(). Handles generic parameters directly if
+ * handler() hasn't already done so. If only generic parameters are expected,
+ * handler() can be NULL.
+ */
+void bl_aux_params_parse(u_register_t head,
+			 bl_aux_param_handler_t handler);
+
+#endif /* LIB_BL_AUX_PARAMS_H */
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 2b48967..41f71e8 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,6 +7,8 @@
 #ifndef UTILS_DEF_H
 #define UTILS_DEF_H
 
+#include <export/lib/utils_def_exp.h>
+
 /* Compute the number of elements in the given array */
 #define ARRAY_SIZE(a)				\
 	(sizeof(a) / sizeof((a)[0]))
@@ -106,29 +108,6 @@
 #define check_u32_overflow(_u32, _inc) \
 	((_u32) > (UINT32_MAX - (_inc)))
 
-/*
- * For those constants to be shared between C and other sources, apply a 'U',
- * 'UL', 'ULL', 'L' or 'LL' suffix to the argument only in C, to avoid
- * undefined or unintended behaviour.
- *
- * The GNU assembler and linker do not support these suffixes (it causes the
- * build process to fail) therefore the suffix is omitted when used in linker
- * scripts and assembler files.
-*/
-#if defined(__LINKER__) || defined(__ASSEMBLY__)
-# define   U(_x)	(_x)
-# define  UL(_x)	(_x)
-# define ULL(_x)	(_x)
-# define   L(_x)	(_x)
-# define  LL(_x)	(_x)
-#else
-# define   U(_x)	(_x##U)
-# define  UL(_x)	(_x##UL)
-# define ULL(_x)	(_x##ULL)
-# define   L(_x)	(_x##L)
-# define  LL(_x)	(_x##LL)
-#endif
-
 /* Register size of the current architecture. */
 #ifdef AARCH32
 #define REGSZ		U(4)
diff --git a/include/plat/marvell/a3700/common/marvell_def.h b/include/plat/marvell/a3700/common/marvell_def.h
index 229b8b0..eb13ba8 100644
--- a/include/plat/marvell/a3700/common/marvell_def.h
+++ b/include/plat/marvell/a3700/common/marvell_def.h
@@ -12,7 +12,7 @@
 
 #include <arch.h>
 #include <common/tbbr/tbbr_img_def.h>
-#include <lib/xlat_tables/xlat_tables.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
 #include <plat/common/common_def.h>
 
 /****************************************************************************
diff --git a/include/plat/marvell/a3700/common/plat_marvell.h b/include/plat/marvell/a3700/common/plat_marvell.h
index 8b8b53f..ea7cdcd 100644
--- a/include/plat/marvell/a3700/common/plat_marvell.h
+++ b/include/plat/marvell/a3700/common/plat_marvell.h
@@ -13,7 +13,7 @@
 #include <common/bl_common.h>
 #include <lib/cassert.h>
 #include <lib/el3_runtime/cpu_data.h>
-#include <lib/xlat_tables/xlat_tables.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
 
 /*
  * Extern declarations common to Marvell standard platforms
diff --git a/include/plat/marvell/a8k/common/marvell_def.h b/include/plat/marvell/a8k/common/marvell_def.h
index 5ba90f7..4eda01f 100644
--- a/include/plat/marvell/a8k/common/marvell_def.h
+++ b/include/plat/marvell/a8k/common/marvell_def.h
@@ -12,7 +12,7 @@
 
 #include <arch.h>
 #include <common/tbbr/tbbr_img_def.h>
-#include <lib/xlat_tables/xlat_tables.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
 #include <plat/common/common_def.h>
 
 /******************************************************************************
diff --git a/include/plat/marvell/a8k/common/plat_marvell.h b/include/plat/marvell/a8k/common/plat_marvell.h
index 65d4de8..5d805a7 100644
--- a/include/plat/marvell/a8k/common/plat_marvell.h
+++ b/include/plat/marvell/a8k/common/plat_marvell.h
@@ -13,7 +13,7 @@
 #include <lib/cassert.h>
 #include <lib/el3_runtime/cpu_data.h>
 #include <lib/utils.h>
-#include <lib/xlat_tables/xlat_tables.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
 
 /*
  * Extern declarations common to Marvell standard platforms
diff --git a/lib/bl_aux_params/bl_aux_params.c b/lib/bl_aux_params/bl_aux_params.c
new file mode 100644
index 0000000..7a8115c
--- /dev/null
+++ b/lib/bl_aux_params/bl_aux_params.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/coreboot.h>
+#include <lib/bl_aux_params/bl_aux_params.h>
+
+void bl_aux_params_parse(u_register_t head,
+			 bl_aux_param_handler_t handler)
+{
+	struct bl_aux_param_header *p;
+
+	for (p = (void *)head; p; p = (void *)(uintptr_t)p->next) {
+		if (handler && handler(p))
+			continue;
+
+		switch (p->type) {
+#if COREBOOT
+		case BL_AUX_PARAM_COREBOOT_TABLE:
+			coreboot_table_setup((void *)(uintptr_t)
+				((struct bl_aux_param_uint64 *)p)->value);
+			break;
+#endif
+		default:
+			ERROR("Ignoring unknown BL aux parameter: 0x%llx",
+			      p->type);
+			break;
+		}
+	}
+}
diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile
index bc05d0f..60c1458 100644
--- a/lib/romlib/Makefile
+++ b/lib/romlib/Makefile
@@ -5,9 +5,11 @@
 #
 
 AS          = $(CROSS_COMPILE)as
+AR          = $(CROSS_COMPILE)ar
 LD          = $(CROSS_COMPILE)ld
 OC          = $(CROSS_COMPILE)objcopy
 CPP         = $(CROSS_COMPILE)cpp
+ROMLIB_GEN  = ./romlib_generator.py
 BUILD_DIR   = ../../$(BUILD_PLAT)/romlib
 LIB_DIR     = ../../$(BUILD_PLAT)/lib
 WRAPPER_DIR = ../../$(BUILD_PLAT)/libwrapper
@@ -17,6 +19,11 @@
 OBJS        = $(BUILD_DIR)/jmptbl.o $(BUILD_DIR)/init.o
 MAPFILE     = ../../$(BUILD_PLAT)/romlib/romlib.map
 
+ifneq ($(PLAT_DIR),)
+  WRAPPER_SOURCES   = $(shell $(ROMLIB_GEN) genwrappers -b $(WRAPPER_DIR) --list ../../$(PLAT_DIR)/jmptbl.i)
+  WRAPPER_OBJS      = $(WRAPPER_SOURCES:.s=.o)
+endif
+
 V ?= 0
 ifeq ($(V),0)
   Q := @
@@ -61,19 +68,31 @@
 
 $(WRAPPER_DIR)/jmpvar.s: $(BUILD_DIR)/romlib.elf
 	@echo "  VAR     $@"
-	$(Q)./genvar.sh -o $@ $(BUILD_DIR)/romlib.elf
+	$(Q)$(ROMLIB_GEN) genvar --output $@ $<
 
-$(LIB_DIR)/libwrappers.a: $(BUILD_DIR)/jmptbl.i $(WRAPPER_DIR)/jmpvar.o
+$(LIB_DIR)/libwrappers.a: $(WRAPPER_DIR)/jmpvar.o $(WRAPPER_OBJS)
 	@echo "  AR      $@"
-	$(Q)./genwrappers.sh -b $(WRAPPER_DIR) -o $@ --bti=$(ENABLE_BTI) --asflags=$(ASFLAGS) $(BUILD_DIR)/jmptbl.i
+	$(Q)$(AR) -rc $@ $(WRAPPER_DIR)/jmpvar.o $(WRAPPER_OBJS)
 
-$(BUILD_DIR)/jmptbl.i: $(BUILD_DIR)/jmptbl.s
+$(BUILD_DIR)/jmptbl.i: ../../$(PLAT_DIR)/jmptbl.i
+	@echo "  PRE     $@"
+	$(Q)$(ROMLIB_GEN) pre --output $@ --deps $(BUILD_DIR)/jmptbl.d $<
 
-$(BUILD_DIR)/jmptbl.s: ../../$(PLAT_DIR)/jmptbl.i
+$(BUILD_DIR)/wrappers.stamp: $(BUILD_DIR)/jmptbl.i
+	@echo "  WRP     $<"
+	$(Q)$(ROMLIB_GEN) genwrappers --bti=$(ENABLE_BTI) -b $(WRAPPER_DIR) $<
+	@touch $@
+
+$(WRAPPER_SOURCES): $(BUILD_DIR)/wrappers.stamp
+
+$(WRAPPER_OBJS): $(WRAPPER_SOURCES) $(BUILD_DIR)/wrappers.stamp
+
+$(BUILD_DIR)/jmptbl.s: $(BUILD_DIR)/jmptbl.i
 	@echo "  TBL     $@"
-	$(Q)./gentbl.sh -o $@ -b $(BUILD_DIR) --bti=$(ENABLE_BTI) ../../$(PLAT_DIR)/jmptbl.i
+	$(Q)$(ROMLIB_GEN) gentbl --output $@ --bti=$(ENABLE_BTI) $<
 
 clean:
 	@rm -f $(BUILD_DIR)/*
 
 -include $(BUILD_DIR)/romlib.d
+-include $(BUILD_DIR)/jmptbl.d
diff --git a/lib/romlib/gentbl.sh b/lib/romlib/gentbl.sh
deleted file mode 100755
index bfb1ec3cf..0000000
--- a/lib/romlib/gentbl.sh
+++ /dev/null
@@ -1,66 +0,0 @@
-#!/bin/sh
-# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-
-set -e
-
-output=jmptbl.s
-build=.
-
-for i
-do
-	case $i in
-	-o)
-		output=$2
-		shift 2
-		;;
-	-b)
-		build=$2
-		shift 2
-		;;
-	--bti=*)
-		enable_bti=$(echo $1 | sed 's/--bti=\(.*\)/\1/')
-		shift 1
-		;;
-	--)
-		shift
-		break
-		;;
-	-*)
-		echo usage: gentbl.sh [-o output] [-b dir] file ... >&2
-		exit 1
-		;;
-	esac
-done
-
-tmp=`mktemp`
-trap "rm -f $$.tmp" EXIT INT QUIT
-rm -f $output
-
-# Pre-process include files
-awk '!/^$/ && !/[:blank:]*#.*/{
-if (NF == 2 && $1 == "include") {
-	while ((getline line < $2) > 0)
-		if (line !~ /^$/ && line !~ /[:blank:]*#.*/)
-			print line
-		close($2)
-} else
-	print
-}' "$@" |
-awk -v OFS="\t" '
-BEGIN{print "#index\tlib\tfunction\t[patch]"}
-{print NR-1, $0}' | tee $build/jmptbl.i |
-awk -v OFS="\n" -v BTI=$enable_bti '
-BEGIN {print "\t.text",
-             "\t.globl\tjmptbl",
-             "jmptbl:"}
-      {sub(/[:blank:]*#.*/,"")}
-!/^$/ {
-	if (BTI == 1)
-		print "\tbti\tj"
-	if ($3 == "reserved")
-		print "\t.word\t0x0"
-	else
-		print "\tb\t" $3}' > $$.tmp &&
-mv $$.tmp $output
diff --git a/lib/romlib/genvar.sh b/lib/romlib/genvar.sh
deleted file mode 100755
index a3e2cdf..0000000
--- a/lib/romlib/genvar.sh
+++ /dev/null
@@ -1,36 +0,0 @@
-#!/bin/sh
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-
-set -e
-
-output=jmpvar.s
-for i
-do
-	case $i in
-	-o)
-		output=$2
-		shift 2
-		;;
-	--)
-		shift
-		break
-		;;
-	-*)
-		echo usage: genvar.sh [-o output] file... >&2
-		;;
-	esac
-done
-
-tmp=`mktemp`
-trap "rm -f $tmp" EXIT INT QUIT
-
-nm -a "$@" |
-awk -v OFS="\n" '
-$3 == ".text" {print "\t.data",
-                     "\t.globl\tjmptbl",
-                     "\t.align\t4",
-                     "jmptbl:\t.quad\t0x" $1}' > $tmp
-
-mv $tmp $output
diff --git a/lib/romlib/genwrappers.sh b/lib/romlib/genwrappers.sh
deleted file mode 100755
index e092548..0000000
--- a/lib/romlib/genwrappers.sh
+++ /dev/null
@@ -1,71 +0,0 @@
-#!/bin/sh
-# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-
-set -e
-
-build=.
-out=output.a
-
-for i
-do
-	case $i in
-	-o)
-		out=$2
-		shift 2
-		;;
-	-b)
-		build=$2
-		shift 2
-		;;
-	--bti=*)
-		enable_bti=$(echo $1 | sed 's/--bti=\(.*\)/\1/')
-		shift 1
-		;;
-	--asflags=*)
-		asflags=$(echo $1 | sed 's/--asflags=\(.*\)/\1/')
-		shift 1
-		;;
-	--)
-		shift
-		break
-		;;
-	-*)
-		echo usage: genwrappers.sh [-o output] [-b dir] file ... >&2
-		exit 1
-		;;
-	esac
-done
-
-awk -v BTI=$enable_bti '
-{sub(/[:blank:]*#.*/,"")}
-!/^$/ && $NF != "patch" && $NF != "reserved" {
-		if (BTI == 1)
-			print $1*8, $2, $3
-		else
-			print $1*4, $2, $3}' "$@" |
-while read idx lib sym
-do
-	file=$build/${lib}_$sym
-
-	cat <<EOF > $file.s
-	.globl	$sym
-$sym:
-EOF
-if [ $enable_bti = 1 ]
-then
-	echo "\tbti\tjc" >> $file.s
-fi
-	cat <<EOF >> $file.s
-	ldr	x17, =jmptbl
-	mov	x16, #$idx
-	ldr	x17, [x17]
-	add	x16, x16, x17
-	br	x16
-EOF
-
-	${CROSS_COMPILE}as ${asflags} -o $file.o $file.s
-done
-
-${CROSS_COMPILE}ar -rc $out $build/*.o
diff --git a/lib/romlib/romlib_generator.py b/lib/romlib/romlib_generator.py
new file mode 100755
index 0000000..0682dd4
--- /dev/null
+++ b/lib/romlib/romlib_generator.py
@@ -0,0 +1,277 @@
+#!/usr/bin/env python3
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+"""
+This module contains a set of classes and a runner that can generate code for the romlib module
+based on the templates in the 'templates' directory.
+"""
+
+import argparse
+import os
+import re
+import subprocess
+import string
+import sys
+
+class IndexFileParser:
+    """
+    Parses the contents of the index file into the items and dependencies variables. It
+    also resolves included files in the index files recursively with circular inclusion detection.
+    """
+
+    def __init__(self):
+        self.items = []
+        self.dependencies = {}
+        self.include_chain = []
+
+    def add_dependency(self, parent, dependency):
+        """ Adds a dependency into the dependencies variable. """
+        if parent in self.dependencies:
+            self.dependencies[parent].append(dependency)
+        else:
+            self.dependencies[parent] = [dependency]
+
+    def get_dependencies(self, parent):
+        """ Gets all the recursive dependencies of a parent file. """
+        parent = os.path.normpath(parent)
+        if parent in self.dependencies:
+            direct_deps = self.dependencies[parent]
+            deps = direct_deps
+            for direct_dep in direct_deps:
+                deps += self.get_dependencies(direct_dep)
+            return deps
+
+        return []
+
+    def parse(self, file_name):
+        """ Opens and parses index file. """
+        file_name = os.path.normpath(file_name)
+
+        if file_name not in self.include_chain:
+            self.include_chain.append(file_name)
+            self.dependencies[file_name] = []
+        else:
+            raise Exception("Circular dependency detected: " + file_name)
+
+        with open(file_name, "r") as index_file:
+            for line in index_file.readlines():
+                line_elements = line.split()
+
+                if line.startswith("#") or not line_elements:
+                    # Comment or empty line
+                    continue
+
+                if line_elements[0] == "reserved":
+                    # Reserved slot in the jump table
+                    self.items.append({"type": "reserved"})
+                elif line_elements[0] == "include" and len(line_elements) > 1:
+                    # Include other index file
+                    included_file = os.path.normpath(line_elements[1])
+                    self.add_dependency(file_name, included_file)
+                    self.parse(included_file)
+                elif len(line_elements) > 1:
+                    # Library function
+                    library_name = line_elements[0]
+                    function_name = line_elements[1]
+                    patch = bool(len(line_elements) > 2 and line_elements[2] == "patch")
+
+                    self.items.append({"type": "function", "library_name": library_name,
+                                       "function_name": function_name, "patch": patch})
+                else:
+                    raise Exception("Invalid line: '" + line + "'")
+
+        self.include_chain.pop()
+
+class RomlibApplication:
+    """ Base class of romlib applications. """
+    TEMPLATE_DIR = os.path.dirname(os.path.realpath(__file__)) + "/templates/"
+
+    def __init__(self, prog):
+        self.args = argparse.ArgumentParser(prog=prog, description=self.__doc__)
+        self.config = None
+
+    def parse_arguments(self, argv):
+        """ Parses the arguments that should come from the command line arguments. """
+        self.config = self.args.parse_args(argv)
+
+    def build_template(self, name, mapping=None, remove_comment=False):
+        """
+        Loads a template and builds it with the defined mapping. Template paths are always relative
+        to this script.
+        """
+
+        with open(self.TEMPLATE_DIR + name, "r") as template_file:
+            if remove_comment:
+                # Removing copyright comment to make the generated code more readable when the
+                # template is inserted multiple times into the output.
+                template_lines = template_file.readlines()
+                end_of_comment_line = 0
+                for index, line in enumerate(template_lines):
+                    if line.find("*/") != -1:
+                        end_of_comment_line = index
+                        break
+                template_data = "".join(template_lines[end_of_comment_line + 1:])
+            else:
+                template_data = template_file.read()
+
+            template = string.Template(template_data)
+            return template.substitute(mapping)
+
+class IndexPreprocessor(RomlibApplication):
+    """ Removes empty and comment lines from the index file and resolves includes. """
+
+    def __init__(self, prog):
+        RomlibApplication.__init__(self, prog)
+
+        self.args.add_argument("-o", "--output", help="Output file", metavar="output",
+                               default="jmpvar.s")
+        self.args.add_argument("--deps", help="Dependency file")
+        self.args.add_argument("file", help="Input file")
+
+    def main(self):
+        """
+        After parsing the input index file it generates a clean output with all includes resolved.
+        Using --deps option it also outputs the dependencies in makefile format like gcc's with -M.
+        """
+
+        index_file_parser = IndexFileParser()
+        index_file_parser.parse(self.config.file)
+
+        with open(self.config.output, "w") as output_file:
+            for item in index_file_parser.items:
+                if item["type"] == "function":
+                    patch = "\tpatch" if item["patch"] else ""
+                    output_file.write(
+                        item["library_name"] + "\t" + item["function_name"] + patch + "\n")
+                else:
+                    output_file.write("reserved\n")
+
+        if self.config.deps:
+            with open(self.config.deps, "w") as deps_file:
+                deps = [self.config.file] + index_file_parser.get_dependencies(self.config.file)
+                deps_file.write(self.config.output + ": " + " \\\n".join(deps) + "\n")
+
+class TableGenerator(RomlibApplication):
+    """ Generates the jump table by parsing the index file. """
+
+    def __init__(self, prog):
+        RomlibApplication.__init__(self, prog)
+
+        self.args.add_argument("-o", "--output", help="Output file", metavar="output",
+                               default="jmpvar.s")
+        self.args.add_argument("--bti", help="Branch Target Identification", type=int)
+        self.args.add_argument("file", help="Input file")
+
+    def main(self):
+        """
+        Inserts the jmptbl definition and the jump entries into the output file. Also can insert
+        BTI related code before entries if --bti option set. It can output a dependency file of the
+        included index files. This can be directly included in makefiles.
+        """
+
+        index_file_parser = IndexFileParser()
+        index_file_parser.parse(self.config.file)
+
+        with open(self.config.output, "w") as output_file:
+            output_file.write(self.build_template("jmptbl_header.S"))
+            bti = "_bti" if self.config.bti == 1 else ""
+
+            for item in index_file_parser.items:
+                template_name = "jmptbl_entry_" + item["type"] + bti + ".S"
+                output_file.write(self.build_template(template_name, item, True))
+
+class WrapperGenerator(RomlibApplication):
+    """
+    Generates a wrapper function for each entry in the index file except for the ones that contain
+    the keyword patch. The generated wrapper file is called <lib>_<fn_name>.s.
+    """
+
+    def __init__(self, prog):
+        RomlibApplication.__init__(self, prog)
+
+        self.args.add_argument("-b", help="Build directory", default=".", metavar="build")
+        self.args.add_argument("--bti", help="Branch Target Identification", type=int)
+        self.args.add_argument("--list", help="Only list assembly files", action="store_true")
+        self.args.add_argument("file", help="Input file")
+
+    def main(self):
+        """
+        Iterates through the items in the parsed index file and builds the template for each entry.
+        """
+
+        index_file_parser = IndexFileParser()
+        index_file_parser.parse(self.config.file)
+
+        bti = "_bti" if self.config.bti == 1 else ""
+        function_offset = 0
+        files = []
+
+        for item_index in range(0, len(index_file_parser.items)):
+            item = index_file_parser.items[item_index]
+
+            if item["type"] == "reserved" or item["patch"]:
+                continue
+
+            asm = self.config.b + "/" + item["function_name"] + ".s"
+            if self.config.list:
+                # Only listing files
+                files.append(asm)
+            else:
+                with open(asm, "w") as asm_file:
+                    # The jump instruction is 4 bytes but BTI requires and extra instruction so
+                    # this makes it 8 bytes per entry.
+                    function_offset = item_index * (8 if self.config.bti else 4)
+
+                    item["function_offset"] = function_offset
+                    asm_file.write(self.build_template("wrapper" + bti + ".S", item))
+
+        if self.config.list:
+            print(" ".join(files))
+
+class VariableGenerator(RomlibApplication):
+    """ Generates the jump table global variable with the absolute address in ROM. """
+
+    def __init__(self, prog):
+        RomlibApplication.__init__(self, prog)
+
+        self.args.add_argument("-o", "--output", help="Output file", metavar="output",
+                               default="jmpvar.s")
+        self.args.add_argument("file", help="Input file")
+
+    def main(self):
+        """
+        Runs nm -a command on the input file and inserts the address of the .text section into the
+        template as the ROM address of the jmp_table.
+        """
+        symbols = subprocess.check_output(["nm", "-a", self.config.file])
+
+        matching_symbol = re.search("([0-9A-Fa-f]+) . \\.text", str(symbols))
+        if not matching_symbol:
+            raise Exception("No '.text' section was found in %s" % self.config.file)
+
+        mapping = {"jmptbl_address": matching_symbol.group(1)}
+
+        with open(self.config.output, "w") as output_file:
+            output_file.write(self.build_template("jmptbl_glob_var.S", mapping))
+
+if __name__ == "__main__":
+    APPS = {"genvar": VariableGenerator, "pre": IndexPreprocessor,
+            "gentbl": TableGenerator, "genwrappers": WrapperGenerator}
+
+    if len(sys.argv) < 2 or sys.argv[1] not in APPS:
+        print("usage: romlib_generator.py [%s] [args]" % "|".join(APPS.keys()), file=sys.stderr)
+        sys.exit(1)
+
+    APP = APPS[sys.argv[1]]("romlib_generator.py " + sys.argv[1])
+    APP.parse_arguments(sys.argv[2:])
+    try:
+        APP.main()
+        sys.exit(0)
+    except FileNotFoundError as file_not_found_error:
+        print(file_not_found_error, file=sys.stderr)
+    except subprocess.CalledProcessError as called_process_error:
+        print(called_process_error.output, file=sys.stderr)
+
+    sys.exit(1)
diff --git a/lib/romlib/templates/jmptbl_entry_function.S b/lib/romlib/templates/jmptbl_entry_function.S
new file mode 100644
index 0000000..a0f8456
--- /dev/null
+++ b/lib/romlib/templates/jmptbl_entry_function.S
@@ -0,0 +1,6 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+	b	${function_name}
diff --git a/lib/romlib/templates/jmptbl_entry_function_bti.S b/lib/romlib/templates/jmptbl_entry_function_bti.S
new file mode 100644
index 0000000..d96ee94
--- /dev/null
+++ b/lib/romlib/templates/jmptbl_entry_function_bti.S
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+	bti	j
+	b	${function_name}
diff --git a/lib/romlib/templates/jmptbl_entry_reserved.S b/lib/romlib/templates/jmptbl_entry_reserved.S
new file mode 100644
index 0000000..a9b5f18
--- /dev/null
+++ b/lib/romlib/templates/jmptbl_entry_reserved.S
@@ -0,0 +1,6 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+	b	.
diff --git a/lib/romlib/templates/jmptbl_entry_reserved_bti.S b/lib/romlib/templates/jmptbl_entry_reserved_bti.S
new file mode 100644
index 0000000..a9f0375
--- /dev/null
+++ b/lib/romlib/templates/jmptbl_entry_reserved_bti.S
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+	bti	j
+	b	.
diff --git a/lib/romlib/templates/jmptbl_glob_var.S b/lib/romlib/templates/jmptbl_glob_var.S
new file mode 100644
index 0000000..d306512
--- /dev/null
+++ b/lib/romlib/templates/jmptbl_glob_var.S
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+	.data
+	.globl	jmptbl
+	.align	4
+jmptbl:	.quad	0x${jmptbl_address}
diff --git a/lib/romlib/templates/jmptbl_header.S b/lib/romlib/templates/jmptbl_header.S
new file mode 100644
index 0000000..72b8ce5
--- /dev/null
+++ b/lib/romlib/templates/jmptbl_header.S
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+	.text
+	.globl	jmptbl
+jmptbl:
diff --git a/lib/romlib/templates/wrapper.S b/lib/romlib/templates/wrapper.S
new file mode 100644
index 0000000..734a68a
--- /dev/null
+++ b/lib/romlib/templates/wrapper.S
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+	.globl	${function_name}
+${function_name}:
+	ldr	x17, =jmptbl
+	mov	x16, #${function_offset}
+	ldr	x17, [x17]
+	add	x16, x16, x17
+	br	x16
diff --git a/lib/romlib/templates/wrapper_bti.S b/lib/romlib/templates/wrapper_bti.S
new file mode 100644
index 0000000..ba9b11c
--- /dev/null
+++ b/lib/romlib/templates/wrapper_bti.S
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+	.globl	${function_name}
+${function_name}:
+	bti	jc
+	ldr	x17, =jmptbl
+	mov	x16, #${function_offset}
+	ldr	x17, [x17]
+	add	x16, x16, x17
+	br	x16
diff --git a/plat/arm/board/common/board_arm_trusted_boot.c b/plat/arm/board/common/board_arm_trusted_boot.c
index e3c6805..c71e932 100644
--- a/plat/arm/board/common/board_arm_trusted_boot.c
+++ b/plat/arm/board/common/board_arm_trusted_boot.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -181,12 +181,7 @@
 }
 #else /* ARM_CRYPTOCELL_INTEG */
 
-#include <drivers/arm/cryptocell/nvm.h>
-#include <drivers/arm/cryptocell/nvm_otp.h>
-#include <drivers/arm/cryptocell/sbrom_bsv_api.h>
-
-CASSERT(HASH_RESULT_SIZE_IN_BYTES == SHA256_BYTES,
-		assert_mismatch_in_hash_result_size);
+#include <drivers/arm/cryptocell/cc_rotpk.h>
 
 /*
  * Return the ROTPK hash in the following ASN.1 structure in DER format:
@@ -205,90 +200,16 @@
 			unsigned int *flags)
 {
 	unsigned char *dst;
-	CCError_t error;
-	uint32_t lcs;
 
 	assert(key_ptr != NULL);
 	assert(key_len != NULL);
 	assert(flags != NULL);
 
-	error = NVM_GetLCS(PLAT_CRYPTOCELL_BASE, &lcs);
-	if (error != CC_OK)
-		return 1;
-
-	/* If the lifecycle state is `SD`, return failure */
-	if (lcs == CC_BSV_SECURITY_DISABLED_LCS)
-		return 1;
-
-	/*
-	 * If the lifecycle state is `CM` or `DM`, ROTPK shouldn't be verified.
-	 * Return success after setting ROTPK_NOT_DEPLOYED flag
-	 */
-	if ((lcs == CC_BSV_CHIP_MANUFACTURE_LCS) ||
-			(lcs == CC_BSV_DEVICE_MANUFACTURE_LCS)) {
-		*key_len = 0;
-		*flags = ROTPK_NOT_DEPLOYED;
-		return 0;
-	}
-
 	/* Copy the DER header */
 	memcpy(rotpk_hash_der, rotpk_hash_hdr, rotpk_hash_hdr_len);
 	dst = &rotpk_hash_der[rotpk_hash_hdr_len];
-	error = NVM_ReadHASHPubKey(PLAT_CRYPTOCELL_BASE,
-			CC_SB_HASH_BOOT_KEY_256B,
-			(uint32_t *)dst, HASH_RESULT_SIZE_IN_WORDS);
-	if (error != CC_OK)
-		return 1;
-
 	*key_ptr = rotpk_hash_der;
 	*key_len = sizeof(rotpk_hash_der);
-	*flags = ROTPK_IS_HASH;
-	return 0;
+	return cc_get_rotpk_hash(dst, SHA256_BYTES, flags);
 }
-
-/*
- * Return the non-volatile counter value stored in the platform. The cookie
- * specifies the OID of the counter in the certificate.
- *
- * Return: 0 = success, Otherwise = error
- */
-int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
-{
-	CCError_t error = CC_FAIL;
-
-	if (strcmp(cookie, TRUSTED_FW_NVCOUNTER_OID) == 0) {
-		error = NVM_GetSwVersion(PLAT_CRYPTOCELL_BASE,
-				CC_SW_VERSION_COUNTER1, nv_ctr);
-	} else if (strcmp(cookie, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) {
-		error = NVM_GetSwVersion(PLAT_CRYPTOCELL_BASE,
-				CC_SW_VERSION_COUNTER2, nv_ctr);
-	}
-
-	return (error != CC_OK);
-}
-
-/*
- * Store a new non-volatile counter value in the counter specified by the OID
- * in the cookie. This function is not expected to be called if the Lifecycle
- * state is RMA as the values in the certificate are expected to always match
- * the nvcounter values. But if called when the LCS is RMA, the underlying
- * helper functions will return success but without updating the counter.
- *
- * Return: 0 = success, Otherwise = error
- */
-int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
-{
-	CCError_t error = CC_FAIL;
-
-	if (strcmp(cookie, TRUSTED_FW_NVCOUNTER_OID) == 0) {
-		error = NVM_SetSwVersion(PLAT_CRYPTOCELL_BASE,
-				CC_SW_VERSION_COUNTER1, nv_ctr);
-	} else if (strcmp(cookie, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) {
-		error = NVM_SetSwVersion(PLAT_CRYPTOCELL_BASE,
-				CC_SW_VERSION_COUNTER2, nv_ctr);
-	}
-
-	return (error != CC_OK);
-}
-
 #endif /* ARM_CRYPTOCELL_INTEG */
diff --git a/plat/hisilicon/poplar/bl31_plat_setup.c b/plat/hisilicon/poplar/bl31_plat_setup.c
index f81078f..981ef37 100644
--- a/plat/hisilicon/poplar/bl31_plat_setup.c
+++ b/plat/hisilicon/poplar/bl31_plat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -130,6 +130,6 @@
 			       BL_COHERENT_RAM_BASE,
 			       BL_COHERENT_RAM_END);
 
-	INFO("Boot BL33 from 0x%lx for %lu Bytes\n",
+	INFO("Boot BL33 from 0x%lx for %llu Bytes\n",
 	     bl33_image_ep_info.pc, bl33_image_ep_info.args.arg2);
 }
diff --git a/plat/imx/common/include/imx_clock.h b/plat/imx/common/include/imx_clock.h
index ce245ad..d75dcff 100644
--- a/plat/imx/common/include/imx_clock.h
+++ b/plat/imx/common/include/imx_clock.h
@@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef IMX_CLOCK_H
@@ -819,6 +818,8 @@
 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_USB_PLL			(BIT(26) | BIT(24))
 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_REF_1M			(BIT(26) | BIT(25))
 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_SYS_PLL_PFD1_DIV2		((BIT(26) | BIT(25) | BIT(24))
+#define WDOG_DEFAULT_CLK_SELECT					(CCM_TARGET_ROOT_ENABLE |\
+								CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M)
 
 /* Target CSI_MCLK_CLK_ROOT */
 
diff --git a/plat/imx/common/include/imx_io_mux.h b/plat/imx/common/include/imx_io_mux.h
index 9b30421..d588cfd 100644
--- a/plat/imx/common/include/imx_io_mux.h
+++ b/plat/imx/common/include/imx_io_mux.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,7 @@
 #define IMX_IO_MUX_H
 
 #include <stdint.h>
+#include <lib/utils_def.h>
 
 /*
  * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
@@ -20,7 +21,10 @@
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_OFFSET		0x0020
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_OFFSET		0x0024
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_OFFSET		0x0028
+
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_OFFSET		0x002C
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_ALT1_SD3_CD_B	BIT(0)
+
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_OFFSET		0x0030
 
 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_OFFSET	0x0034
@@ -121,8 +125,24 @@
 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_OFFSET		0x0154
 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_OFFSET		0x0158
 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_OFFSET		0x015C
+
 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_OFFSET		0x0160
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT0_I2C4_SCL		0x0
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT1_UART5_RX_DATA	BIT(0)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT2_WDOG4_WDOG_B	BIT(1)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT3_CSI_PIXCLK		(BIT(1) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT4_USB_OTG1_ID		BIT(2)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT5_GPIO4_IO14		(BIT(2) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT6_EPDC_VCOM0		(BIT(2) | BIT(1))
+
 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_OFFSET		0x0164
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT0_I2C4_SDA		0x0
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT1_UART5_TX_DATA	BIT(0)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT2_WDOG4_WDOG_RST_B_DEB BIT(1)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT3_CSI_MCLK		(BIT(1) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT4_USB_OTG2_ID		BIT(2)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT5_GPIO4_IO15		(BIT(1) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT6_EPDC_VCOM1		(BIT(2) | BIT(1))
 
 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_OFFSET	0x0168
 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT0_ECSPI1_SCLK	0x00
@@ -165,6 +185,7 @@
 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_OFFSET		0x01C4
 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_OFFSET		0x01C8
 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_OFFSET		0x01CC
+
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_OFFSET		0x01D0
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_OFFSET		0x01D4
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_OFFSET		0x01D8
@@ -391,6 +412,7 @@
 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_OFFSET		0x0434
 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_OFFSET		0x0438
 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_OFFSET		0x043C
+
 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_OFFSET		0x0440
 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_OFFSET		0x0444
 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_OFFSET		0x0448
@@ -403,6 +425,19 @@
 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_OFFSET		0x0464
 #define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_OFFSET		0x0468
 #define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_OFFSET	0x046C
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_0_X1		0
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_1_X4		BIT(0)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_2_X2		BIT(1)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_3_X6		(BIT(1) | BIT(0))
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_1_X4		BIT(0)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_SLOW		BIT(2)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_FAST		0
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_HYS			BIT(3)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PE			BIT(4)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PD_100K		(0 << 5)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_5K			(1 << 5)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_47K		(2 << 5)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_100K		(3 << 5)
 
 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_OFFSET	0x0470
 #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_OFFSET	0x0474
@@ -588,7 +623,15 @@
 #define IOMUXC_UART4_RTS_B_SELECT_INPUT_OFFSET		0x0708
 #define IOMUXC_UART4_RX_DATA_SELECT_INPUT_OFFSET	0x070C
 #define IOMUXC_UART5_RTS_B_SELECT_INPUT_OFFSET		0x0710
+
 #define IOMUXC_UART5_RX_DATA_SELECT_INPUT_OFFSET	0x0714
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_I2C4_SCL_ALT1	0x00
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_I2C4_SDA_ALT1	BIT(0)
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_SAI1_RX_DATA_ALT2	BIT(1)
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_SAI1_TX_BCLK_ALT2	(BIT(1) | BIT(0))
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_GPIO1_IO06_ALT3	BIT(2)
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_GPIO1_IO07_ALT3	(BIT(2) | BIT(1))
+
 #define IOMUXC_UART6_RTS_B_SELECT_INPUT_OFFSET		0x0718
 #define IOMUXC_UART6_RX_DATA_SELECT_INPUT_OFFSET	0x071C
 #define IOMUXC_UART7_RTS_B_SELECT_INPUT_OFFSET		0x0720
diff --git a/plat/imx/imx7/common/imx7.mk b/plat/imx/imx7/common/imx7.mk
new file mode 100644
index 0000000..849ddcd
--- /dev/null
+++ b/plat/imx/imx7/common/imx7.mk
@@ -0,0 +1,110 @@
+#
+# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Architecture
+$(eval $(call add_define,ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING))
+
+TF_CFLAGS	+=	-mfpu=neon
+ASFLAGS		+=	-mfpu=neon
+
+# Platform
+PLAT_INCLUDES		:=	-Idrivers/imx/uart			\
+				-Iplat/imx/common/include		\
+				-Iplat/imx/imx7/include			\
+				-Idrivers/imx/timer			\
+				-Idrivers/imx/usdhc			\
+
+# Translation tables library
+include lib/xlat_tables_v2/xlat_tables.mk
+
+BL2_SOURCES		+=	common/desc_image_load.c			\
+				drivers/delay_timer/delay_timer.c		\
+				drivers/mmc/mmc.c				\
+				drivers/io/io_block.c				\
+				drivers/io/io_fip.c				\
+				drivers/io/io_memmap.c				\
+				drivers/io/io_storage.c				\
+				drivers/imx/timer/imx_gpt.c			\
+				drivers/imx/uart/imx_uart.c			\
+				drivers/imx/uart/imx_crash_uart.S		\
+				lib/aarch32/arm32_aeabi_divmod.c		\
+				lib/aarch32/arm32_aeabi_divmod_a32.S		\
+				lib/cpus/aarch32/cortex_a7.S			\
+				lib/optee/optee_utils.c				\
+				plat/imx/common/imx_aips.c			\
+				plat/imx/common/imx_caam.c			\
+				plat/imx/common/imx_clock.c			\
+				plat/imx/common/imx_csu.c			\
+				plat/imx/common/imx_io_mux.c			\
+				plat/imx/common/imx_snvs.c			\
+				plat/imx/common/imx_wdog.c			\
+				plat/imx/common/imx7_clock.c			\
+				plat/imx/imx7/common/imx7_bl2_mem_params_desc.c	\
+				plat/imx/imx7/common/imx7_bl2_el3_common.c	\
+				plat/imx/imx7/common/imx7_helpers.S		\
+				plat/imx/imx7/common/imx7_image_load.c		\
+				plat/imx/imx7/common/imx7_io_storage.c		\
+				plat/imx/common/aarch32/imx_uart_console.S	\
+				${XLAT_TABLES_LIB_SRCS}
+
+ifneq (${TRUSTED_BOARD_BOOT},0)
+
+include drivers/auth/mbedtls/mbedtls_crypto.mk
+include drivers/auth/mbedtls/mbedtls_x509.mk
+
+AUTH_SOURCES	:=	drivers/auth/auth_mod.c			\
+			drivers/auth/crypto_mod.c		\
+			drivers/auth/img_parser_mod.c		\
+			drivers/auth/tbbr/tbbr_cot.c
+
+BL2_SOURCES		+=	${AUTH_SOURCES}					\
+				plat/common/tbbr/plat_tbbr.c			\
+				plat/imx/imx7/common/imx7_trusted_boot.c	\
+				plat/imx/imx7/common/imx7_rotpk.S
+
+ROT_KEY             = $(BUILD_PLAT)/rot_key.pem
+ROTPK_HASH          = $(BUILD_PLAT)/rotpk_sha256.bin
+
+$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
+$(eval $(call MAKE_LIB_DIRS))
+
+$(BUILD_PLAT)/bl2/imx7_rotpk.o: $(ROTPK_HASH)
+
+certificates: $(ROT_KEY)
+
+$(ROT_KEY): | $(BUILD_PLAT)
+	@echo "  OPENSSL $@"
+	@if [ ! -f $(ROT_KEY) ]; then \
+		openssl genrsa 2048 > $@ 2>/dev/null; \
+	fi
+
+$(ROTPK_HASH): $(ROT_KEY)
+	@echo "  OPENSSL $@"
+	$(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+	openssl dgst -sha256 -binary > $@ 2>/dev/null
+endif
+
+# Add the build options to pack BLx images and kernel device tree
+# in the FIP if the platform requires.
+ifneq ($(BL2),)
+$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert))
+endif
+ifneq ($(BL32_EXTRA1),)
+$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
+endif
+ifneq ($(BL32_EXTRA2),)
+$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
+endif
+ifneq ($(HW_CONFIG),)
+$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config))
+endif
+
+# Verify build config
+# -------------------
+
+ifeq (${ARCH},aarch64)
+  $(error Error: AArch64 not supported on i.mx7)
+endif
diff --git a/plat/imx/imx7/common/imx7_bl2_el3_common.c b/plat/imx/imx7/common/imx7_bl2_el3_common.c
new file mode 100644
index 0000000..a1e2aaf
--- /dev/null
+++ b/plat/imx/imx7/common/imx7_bl2_el3_common.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <platform_def.h>
+
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <common/desc_image_load.h>
+#include <drivers/mmc.h>
+#include <lib/xlat_tables/xlat_mmu_helpers.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <lib/mmio.h>
+#include <lib/optee_utils.h>
+#include <lib/utils.h>
+
+#include <imx_aips.h>
+#include <imx_caam.h>
+#include <imx_clock.h>
+#include <imx_csu.h>
+#include <imx_gpt.h>
+#include <imx_uart.h>
+#include <imx_snvs.h>
+#include <imx_wdog.h>
+#include <imx7_def.h>
+
+#ifndef AARCH32_SP_OPTEE
+#error "Must build with OPTEE support included"
+#endif
+
+uintptr_t plat_get_ns_image_entrypoint(void)
+{
+	return IMX7_UBOOT_BASE;
+}
+
+static uint32_t imx7_get_spsr_for_bl32_entry(void)
+{
+	return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
+			   DISABLE_ALL_EXCEPTIONS);
+}
+
+static uint32_t imx7_get_spsr_for_bl33_entry(void)
+{
+	return SPSR_MODE32(MODE32_svc,
+			   plat_get_ns_image_entrypoint() & 0x1,
+			   SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
+}
+
+int bl2_plat_handle_post_image_load(unsigned int image_id)
+{
+	int err = 0;
+	bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
+	bl_mem_params_node_t *hw_cfg_mem_params = NULL;
+
+	bl_mem_params_node_t *pager_mem_params = NULL;
+	bl_mem_params_node_t *paged_mem_params = NULL;
+
+	assert(bl_mem_params);
+
+	switch (image_id) {
+	case BL32_IMAGE_ID:
+		pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
+		assert(pager_mem_params);
+
+		paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
+		assert(paged_mem_params);
+
+		err = parse_optee_header(&bl_mem_params->ep_info,
+					 &pager_mem_params->image_info,
+					 &paged_mem_params->image_info);
+		if (err != 0)
+			WARN("OPTEE header parse error.\n");
+
+		/*
+		 * When ATF loads the DTB the address of the DTB is passed in
+		 * arg2, if an hw config image is present use the base address
+		 * as DTB address an pass it as arg2
+		 */
+		hw_cfg_mem_params = get_bl_mem_params_node(HW_CONFIG_ID);
+
+		bl_mem_params->ep_info.args.arg0 =
+					bl_mem_params->ep_info.args.arg1;
+		bl_mem_params->ep_info.args.arg1 = 0;
+		if (hw_cfg_mem_params)
+			bl_mem_params->ep_info.args.arg2 =
+					hw_cfg_mem_params->image_info.image_base;
+		else
+			bl_mem_params->ep_info.args.arg2 = 0;
+		bl_mem_params->ep_info.args.arg3 = 0;
+		bl_mem_params->ep_info.spsr = imx7_get_spsr_for_bl32_entry();
+		break;
+
+	case BL33_IMAGE_ID:
+		/* AArch32 only core: OP-TEE expects NSec EP in register LR */
+		pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
+		assert(pager_mem_params);
+		pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
+
+		/* BL33 expects to receive the primary CPU MPID (through r0) */
+		bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
+		bl_mem_params->ep_info.spsr = imx7_get_spsr_for_bl33_entry();
+		break;
+
+	default:
+		/* Do nothing in default case */
+		break;
+	}
+
+	return err;
+}
+
+void bl2_el3_plat_arch_setup(void)
+{
+	/* Setup the MMU here */
+}
+
+static void imx7_setup_system_counter(void)
+{
+	unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS;
+
+	/* Set the frequency table index to our target frequency */
+	write_cntfrq(freq);
+
+	/* Enable system counter @ frequency table index 0, halt on debug */
+	mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF,
+		      CNTCR_FCREQ(0) | CNTCR_HDBG | CNTCR_EN);
+}
+
+static void imx7_setup_wdog_clocks(void)
+{
+	uint32_t wdog_en_bits = (uint32_t)WDOG_DEFAULT_CLK_SELECT;
+
+	imx_clock_set_wdog_clk_root_bits(wdog_en_bits);
+	imx_clock_enable_wdog(0);
+	imx_clock_enable_wdog(1);
+	imx_clock_enable_wdog(2);
+	imx_clock_enable_wdog(3);
+}
+
+
+/*
+ * bl2_el3_early_platform_setup()
+ * MMU off
+ */
+void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
+				  u_register_t arg3, u_register_t arg4)
+{
+	static console_imx_uart_t console;
+	int console_scope = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME;
+
+	/* Initialize common components */
+	imx_aips_init();
+	imx_csu_init();
+	imx_snvs_init();
+	imx_gpt_ops_init(GPT1_BASE_ADDR);
+	imx_clock_init();
+	imx7_setup_system_counter();
+	imx7_setup_wdog_clocks();
+
+	/* Platform specific setup */
+	imx7_platform_setup(arg1, arg2, arg3, arg4);
+
+	/* Init UART, clock should be enabled in imx7_platform_setup() */
+	console_imx_uart_register(PLAT_IMX7_BOOT_UART_BASE,
+				  PLAT_IMX7_BOOT_UART_CLK_IN_HZ,
+				  PLAT_IMX7_CONSOLE_BAUDRATE,
+				  &console);
+	console_set_scope(&console.console, console_scope);
+
+	/* Open handles to persistent storage */
+	plat_imx7_io_setup();
+
+	/* Setup higher-level functionality CAAM, RTC etc */
+	imx_caam_init();
+	imx_wdog_init();
+
+	/* Print out the expected memory map */
+	VERBOSE("\tOPTEE       0x%08x-0x%08x\n", IMX7_OPTEE_BASE, IMX7_OPTEE_LIMIT);
+	VERBOSE("\tATF/BL2     0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT);
+	VERBOSE("\tSHRAM       0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT);
+	VERBOSE("\tFIP         0x%08x-0x%08x\n", IMX7_FIP_BASE, IMX7_FIP_LIMIT);
+	VERBOSE("\tDTB-OVERLAY 0x%08x-0x%08x\n", IMX7_DTB_OVERLAY_BASE, IMX7_DTB_OVERLAY_LIMIT);
+	VERBOSE("\tDTB         0x%08x-0x%08x\n", IMX7_DTB_BASE, IMX7_DTB_LIMIT);
+	VERBOSE("\tUBOOT/BL33  0x%08x-0x%08x\n", IMX7_UBOOT_BASE, IMX7_UBOOT_LIMIT);
+}
+
+/*
+ * bl2_platform_setup()
+ * MMU on - enabled by bl2_el3_plat_arch_setup()
+ */
+void bl2_platform_setup(void)
+{
+}
diff --git a/plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c b/plat/imx/imx7/common/imx7_bl2_mem_params_desc.c
similarity index 83%
rename from plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c
rename to plat/imx/imx7/common/imx7_bl2_mem_params_desc.c
index c670d42..f9b2983 100644
--- a/plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c
+++ b/plat/imx/imx7/common/imx7_bl2_mem_params_desc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,8 +22,8 @@
 		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
 				      image_info_t, 0),
 
-		.image_info.image_base = WARP7_OPTEE_BASE,
-		.image_info.image_max_size = WARP7_OPTEE_SIZE,
+		.image_info.image_base = IMX7_OPTEE_BASE,
+		.image_info.image_max_size = IMX7_OPTEE_SIZE,
 
 		.next_handoff_image_id = BL33_IMAGE_ID,
 	},
@@ -36,8 +36,8 @@
 
 		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
 				      image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
-		.image_info.image_base = WARP7_OPTEE_BASE,
-		.image_info.image_max_size = WARP7_OPTEE_SIZE,
+		.image_info.image_base = IMX7_OPTEE_BASE,
+		.image_info.image_max_size = IMX7_OPTEE_SIZE,
 
 		.next_handoff_image_id = INVALID_IMAGE_ID,
 	},
@@ -70,8 +70,8 @@
 
 			SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
 					      VERSION_2, image_info_t, 0),
-			.image_info.image_base = WARP7_UBOOT_BASE,
-			.image_info.image_max_size = WARP7_UBOOT_SIZE,
+			.image_info.image_base = IMX7_UBOOT_BASE,
+			.image_info.image_max_size = IMX7_UBOOT_SIZE,
 		# endif /* PRELOADED_BL33_BASE */
 
 		.next_handoff_image_id = INVALID_IMAGE_ID,
diff --git a/plat/imx/imx7/warp7/aarch32/warp7_helpers.S b/plat/imx/imx7/common/imx7_helpers.S
similarity index 82%
rename from plat/imx/imx7/warp7/aarch32/warp7_helpers.S
rename to plat/imx/imx7/common/imx7_helpers.S
index 3695b32..661fd29 100644
--- a/plat/imx/imx7/warp7/aarch32/warp7_helpers.S
+++ b/plat/imx/imx7/common/imx7_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved.
+ * Copyright (c) Linaro 2018-2019 Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -35,14 +35,14 @@
 endfunc plat_get_my_entrypoint
 
 func plat_crash_console_init
-	mov_imm	r0, PLAT_WARP7_BOOT_UART_BASE
-	mov_imm	r1, PLAT_WARP7_BOOT_UART_CLK_IN_HZ
-	mov_imm	r2, PLAT_WARP7_CONSOLE_BAUDRATE
+	mov_imm	r0, PLAT_IMX7_BOOT_UART_BASE
+	mov_imm	r1, PLAT_IMX7_BOOT_UART_CLK_IN_HZ
+	mov_imm	r2, PLAT_IMX7_CONSOLE_BAUDRATE
 	b	imx_crash_uart_init
 endfunc plat_crash_console_init
 
 func plat_crash_console_putc
-	mov_imm r1, PLAT_WARP7_BOOT_UART_BASE
+	mov_imm r1, PLAT_IMX7_BOOT_UART_BASE
 	b	imx_crash_uart_putc
 endfunc plat_crash_console_putc
 
diff --git a/plat/imx/imx7/warp7/warp7_image_load.c b/plat/imx/imx7/common/imx7_image_load.c
similarity index 100%
rename from plat/imx/imx7/warp7/warp7_image_load.c
rename to plat/imx/imx7/common/imx7_image_load.c
diff --git a/plat/imx/imx7/warp7/warp7_io_storage.c b/plat/imx/imx7/common/imx7_io_storage.c
similarity index 93%
rename from plat/imx/imx7/warp7/warp7_io_storage.c
rename to plat/imx/imx7/common/imx7_io_storage.c
index fcfb503..977181d 100644
--- a/plat/imx/imx7/warp7/warp7_io_storage.c
+++ b/plat/imx/imx7/common/imx7_io_storage.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,21 +19,21 @@
 static const io_dev_connector_t *fip_dev_con;
 static uintptr_t fip_dev_handle;
 
-#ifndef WARP7_FIP_MMAP
+#ifndef IMX7_FIP_MMAP
 static const io_dev_connector_t *mmc_dev_con;
 static uintptr_t mmc_dev_handle;
 
 static const io_block_spec_t mmc_fip_spec = {
-	.offset = WARP7_FIP_MMC_BASE,
-	.length = WARP7_FIP_SIZE
+	.offset = IMX7_FIP_MMC_BASE,
+	.length = IMX7_FIP_SIZE
 };
 
 static const io_block_dev_spec_t mmc_dev_spec = {
 	/* It's used as temp buffer in block driver. */
 	.buffer		= {
-		.offset	= WARP7_FIP_BASE,
+		.offset	= IMX7_FIP_BASE,
 		/* do we need a new value? */
-		.length = WARP7_FIP_SIZE
+		.length = IMX7_FIP_SIZE
 	},
 	.ops		= {
 		.read	= mmc_read_blocks,
@@ -49,8 +49,8 @@
 static uintptr_t memmap_dev_handle;
 
 static const io_block_spec_t fip_block_spec = {
-	.offset = WARP7_FIP_BASE,
-	.length = WARP7_FIP_SIZE
+	.offset = IMX7_FIP_BASE,
+	.length = IMX7_FIP_SIZE
 };
 static int open_memmap(const uintptr_t spec);
 #endif
@@ -106,7 +106,7 @@
 };
 
 static const struct plat_io_policy policies[] = {
-#ifndef WARP7_FIP_MMAP
+#ifndef IMX7_FIP_MMAP
 	[FIP_IMAGE_ID] = {
 		&mmc_dev_handle,
 		(uintptr_t)&mmc_fip_spec,
@@ -190,7 +190,7 @@
 	return result;
 }
 
-#ifndef WARP7_FIP_MMAP
+#ifndef IMX7_FIP_MMAP
 static int open_mmc(const uintptr_t spec)
 {
 	int result;
@@ -240,11 +240,11 @@
 	return result;
 }
 
-void plat_warp7_io_setup(void)
+void plat_imx7_io_setup(void)
 {
 	int result __unused;
 
-#ifndef WARP7_FIP_MMAP
+#ifndef IMX7_FIP_MMAP
 	result = register_io_dev_block(&mmc_dev_con);
 	assert(result == 0);
 
diff --git a/plat/imx/imx7/common/imx7_rotpk.S b/plat/imx/imx7/common/imx7_rotpk.S
new file mode 100644
index 0000000..8bd53c2
--- /dev/null
+++ b/plat/imx/imx7/common/imx7_rotpk.S
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+	.global imx7_rotpk_hash
+	.global imx7_rotpk_hash_end
+imx7_rotpk_hash:
+	/* DER header */
+	.byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48
+	.byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20
+	/* SHA256 */
+	.incbin ROTPK_HASH
+imx7_rotpk_hash_end:
diff --git a/plat/imx/imx7/warp7/warp7_trusted_boot.c b/plat/imx/imx7/common/imx7_trusted_boot.c
similarity index 80%
rename from plat/imx/imx7/warp7/warp7_trusted_boot.c
rename to plat/imx/imx7/common/imx7_trusted_boot.c
index 6a00224..cd27128 100644
--- a/plat/imx/imx7/warp7/warp7_trusted_boot.c
+++ b/plat/imx/imx7/common/imx7_trusted_boot.c
@@ -6,13 +6,13 @@
 
 #include <plat/common/platform.h>
 
-extern char warp7_rotpk_hash[], warp7_rotpk_hash_end[];
+extern char imx7_rotpk_hash[], imx7_rotpk_hash_end[];
 
 int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
 			unsigned int *flags)
 {
-	*key_ptr = warp7_rotpk_hash;
-	*key_len = warp7_rotpk_hash_end - warp7_rotpk_hash;
+	*key_ptr = imx7_rotpk_hash;
+	*key_len = imx7_rotpk_hash_end - imx7_rotpk_hash;
 	*flags = ROTPK_IS_HASH;
 
 	return 0;
diff --git a/plat/imx/imx7/include/imx7_def.h b/plat/imx/imx7/include/imx7_def.h
new file mode 100644
index 0000000..77a8ca3
--- /dev/null
+++ b/plat/imx/imx7/include/imx7_def.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IMX7_DEF_H
+#define IMX7_DEF_H
+
+#include <stdint.h>
+
+
+/*******************************************************************************
+ * Function and variable prototypes
+ ******************************************************************************/
+void plat_imx7_io_setup(void);
+void imx7_platform_setup(u_register_t arg1, u_register_t arg2,
+			 u_register_t arg3, u_register_t arg4);
+
+#endif /*IMX7_DEF_H */
diff --git a/plat/imx/imx7/picopi/include/platform_def.h b/plat/imx/imx7/picopi/include/platform_def.h
new file mode 100644
index 0000000..1af1d0c
--- /dev/null
+++ b/plat/imx/imx7/picopi/include/platform_def.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <arch.h>
+#include <common/tbbr/tbbr_img_def.h>
+#include <plat/common/common_def.h>
+
+#define PLATFORM_STACK_SIZE		0x1000
+
+#define PLATFORM_MAX_CPUS_PER_CLUSTER	2
+#define PLATFORM_CLUSTER_COUNT		1
+#define PLATFORM_CLUSTER0_CORE_COUNT	PLATFORM_MAX_CPUS_PER_CLUSTER
+
+#define PLATFORM_CORE_COUNT		PLATFORM_CLUSTER0_CORE_COUNT
+
+#define PICOPI_PRIMARY_CPU		0
+
+#define PLAT_NUM_PWR_DOMAINS		(PLATFORM_CLUSTER_COUNT + \
+					PLATFORM_CORE_COUNT)
+#define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL1
+
+#define PLAT_MAX_RET_STATE		1
+#define PLAT_MAX_OFF_STATE		2
+
+/* Local power state for power domains in Run state. */
+#define PLAT_LOCAL_STATE_RUN		0
+
+/* Local power state for retention. Valid only for CPU power domains */
+#define PLAT_LOCAL_STATE_RET		1
+
+/*
+ * Local power state for OFF/power-down. Valid for CPU and cluster power
+ * domains.
+ */
+#define PLAT_LOCAL_STATE_OFF		2
+
+/*
+ * Macros used to parse state information from State-ID if it is using the
+ * recommended encoding for State-ID.
+ */
+#define PLAT_LOCAL_PSTATE_WIDTH		4
+#define PLAT_LOCAL_PSTATE_MASK		((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ * i.MX7 has a 32 byte cacheline size
+ * i.MX 7Dual Applications Processor Reference Manual, Rev. 1, 01/2018 pg 298
+ */
+#define CACHE_WRITEBACK_SHIFT		4
+#define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
+
+/*
+ * Partition memory into secure BootROM, OCRAM_S, non-secure DRAM, secure DRAM
+ */
+#define BOOT_ROM_BASE			0x00000000
+#define BOOT_ROM_SIZE			0x00020000
+
+#define OCRAM_S_BASE			0x00180000
+#define OCRAM_S_SIZE			0x00008000
+
+/* Controller maps 2GB, board contains 512 MB. 0x80000000 - 0xa0000000 */
+#define DRAM_BASE			0x80000000
+#define DRAM_SIZE			0x20000000
+#define DRAM_LIMIT			(DRAM_BASE + DRAM_SIZE)
+
+/* Place OPTEE at minus 32 MB from the end of memory. 0x9e000000 - 0xa0000000 */
+#define IMX7_OPTEE_SIZE			0x02000000
+#define IMX7_OPTEE_BASE			(DRAM_LIMIT - IMX7_OPTEE_SIZE)
+#define IMX7_OPTEE_LIMIT		(IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
+
+/* Place ATF directly beneath OPTEE. 0x9df00000 - 0x9e000000 */
+#define BL2_RAM_SIZE			0x00100000
+#define BL2_RAM_BASE			(IMX7_OPTEE_BASE - BL2_RAM_SIZE)
+#define BL2_RAM_LIMIT			(BL2_RAM_BASE + BL2_RAM_SIZE)
+
+/* Optional Mailbox. Only relevant on i.MX7D. 0x9deff000 - 0x9df00000*/
+#define SHARED_RAM_SIZE			0x00001000
+#define SHARED_RAM_BASE			(BL2_RAM_BASE - SHARED_RAM_SIZE)
+#define SHARED_RAM_LIMIT		(SHARED_RAM_BASE + SHARED_RAM_SIZE)
+
+/* Define the absolute location of u-boot 0x87800000 - 0x87900000 */
+#define IMX7_UBOOT_SIZE			0x00100000
+#define IMX7_UBOOT_BASE			(DRAM_BASE + 0x7800000)
+#define IMX7_UBOOT_LIMIT		(IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
+
+/* Define FIP image absolute location 0x80000000 - 0x80100000 */
+#define IMX7_FIP_SIZE			0x00100000
+#define IMX7_FIP_BASE			(DRAM_BASE)
+#define IMX7_FIP_LIMIT			(IMX7_FIP_BASE + IMX7_FIP_SIZE)
+
+/* Define FIP image location at 1MB offset */
+#define IMX7_FIP_MMC_BASE		(1024 * 1024)
+
+/* Define the absolute location of DTB 0x83000000 - 0x83100000 */
+#define IMX7_DTB_SIZE			0x00100000
+#define IMX7_DTB_BASE			(DRAM_BASE + 0x03000000)
+#define IMX7_DTB_LIMIT			(IMX7_DTB_BASE + IMX7_DTB_SIZE)
+
+/* Define the absolute location of DTB Overlay 0x83100000 - 0x83101000 */
+#define IMX7_DTB_OVERLAY_SIZE		0x00001000
+#define IMX7_DTB_OVERLAY_BASE		IMX7_DTB_LIMIT
+#define IMX7_DTB_OVERLAY_LIMIT		(IMX7_DTB_OVERLAY_BASE + \
+					 IMX7_DTB_OVERLAY_SIZE)
+/*
+ * BL2 specific defines.
+ *
+ * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
+ * size plus a little space for growth.
+ */
+#define BL2_BASE		BL2_RAM_BASE
+#define BL2_LIMIT		(BL2_RAM_BASE + BL2_RAM_SIZE)
+
+/*
+ * BL3-2/OPTEE
+ */
+# define BL32_BASE		IMX7_OPTEE_BASE
+# define BL32_LIMIT		(IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
+
+/*
+ * BL3-3/U-BOOT
+ */
+#define BL33_BASE		IMX7_UBOOT_BASE
+#define BL33_LIMIT		(IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
+
+/*
+ * ATF's view of memory
+ *
+ * 0xa0000000 +-----------------+
+ *            |       DDR       | BL32/OPTEE
+ * 0x9e000000 +-----------------+
+ *            |       DDR       | BL23 ATF
+ * 0x9df00000 +-----------------+
+ *            |       DDR       | Shared MBOX RAM
+ * 0x9de00000 +-----------------+
+ *            |       DDR       | Unallocated
+ * 0x87900000 +-----------------+
+ *            |       DDR       | BL33/U-BOOT
+ * 0x87800000 +-----------------+
+ *            |       DDR       | Unallocated
+ * 0x83100000 +-----------------+
+ *            |       DDR       | DTB
+ * 0x83000000 +-----------------+
+ *            |       DDR       | Unallocated
+ * 0x80100000 +-----------------+
+ *            |       DDR       | FIP
+ * 0x80000000 +-----------------+
+ *            |     SOC I/0     |
+ * 0x00a00000 +-----------------+
+ *            |      OCRAM      | Not used
+ * 0x00900000 +-----------------+
+ *            |     SOC I/0     |
+ * 0x00188000 +-----------------+
+ *            |     OCRAM_S     | Not used
+ * 0x00180000 +-----------------+
+ *            |     SOC I/0     |
+ * 0x00020000 +-----------------+
+ *            |     BootROM     | BL1
+ * 0x00000000 +-----------------+
+ */
+
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+#define MAX_MMAP_REGIONS		10
+#define MAX_XLAT_TABLES			6
+#define MAX_IO_DEVICES			2
+#define MAX_IO_HANDLES			3
+#define MAX_IO_BLOCK_DEVICES		1
+
+/* UART defines */
+#define PLAT_IMX7_BOOT_UART_BASE	MXC_UART5_BASE
+#define PLAT_IMX7_BOOT_UART_CLK_IN_HZ	24000000
+#define PLAT_IMX7_CONSOLE_BAUDRATE	115200
+
+/* MMC defines */
+#ifndef PLAT_PICOPI_SD
+#define PLAT_PICOPI_SD 3
+#endif
+
+#if PLAT_PICOPI_SD == 1
+#define PLAT_PICOPI_BOOT_MMC_BASE	USDHC1_BASE
+#endif /* PLAT_PICOPI_SD == 1 */
+
+#if PLAT_PICOPI_SD == 2
+#define PLAT_PICOPI_BOOT_MMC_BASE	USDHC2_BASE
+#endif /* PLAT_PICOPI_SD == 2 */
+
+#if PLAT_PICOPI_SD == 3
+#define PLAT_PICOPI_BOOT_MMC_BASE	USDHC3_BASE
+#endif /* PLAT_PICOPI_SD == 3 */
+
+/*
+ * System counter
+ */
+#define SYS_COUNTER_FREQ_IN_TICKS	8000000		/* 8 MHz */
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c b/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c
new file mode 100644
index 0000000..3cf5c36
--- /dev/null
+++ b/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <platform_def.h>
+
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <drivers/mmc.h>
+#include <lib/utils.h>
+
+#include <imx_caam.h>
+#include <imx_clock.h>
+#include <imx_io_mux.h>
+#include <imx_uart.h>
+#include <imx_usdhc.h>
+#include <imx7_def.h>
+
+#define UART5_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
+			  CCM_TRGT_MUX_UART5_CLK_ROOT_OSC_24M)
+
+#define USDHC_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
+			  CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\
+			  CCM_TARGET_POST_PODF(2))
+
+#define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
+			CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL)
+
+#define PICOPI_UART5_RX_MUX \
+	IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT1_UART5_RX_DATA
+
+#define PICOPI_UART5_TX_MUX \
+	IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT1_UART5_TX_DATA
+
+#define PICOPI_SD3_FEATURES \
+	(IOMUXC_SW_PAD_CTL_PAD_SD3_PU_47K            | \
+	 IOMUXC_SW_PAD_CTL_PAD_SD3_PE                | \
+	 IOMUXC_SW_PAD_CTL_PAD_SD3_HYS               | \
+	 IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_SLOW         | \
+	 IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_3_X6)
+
+static void picopi_setup_pinmux(void)
+{
+	/* Configure UART5 TX */
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_OFFSET,
+					 PICOPI_UART5_TX_MUX);
+	/* Configure UART5 RX */
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_OFFSET,
+					 PICOPI_UART5_RX_MUX);
+
+	/* Configure USDHC3 */
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_OFFSET, 0);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_OFFSET,
+					 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_ALT1_SD3_CD_B);
+
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_OFFSET,
+				     PICOPI_SD3_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_OFFSET,
+				     PICOPI_SD3_FEATURES);
+}
+
+static void picopi_usdhc_setup(void)
+{
+	imx_usdhc_params_t params;
+	struct mmc_device_info info;
+
+	zeromem(&params, sizeof(imx_usdhc_params_t));
+	params.reg_base = PLAT_PICOPI_BOOT_MMC_BASE;
+	params.clk_rate = 25000000;
+	params.bus_width = MMC_BUS_WIDTH_8;
+	info.mmc_dev_type = MMC_IS_EMMC;
+	imx_usdhc_init(&params, &info);
+}
+
+static void picopi_setup_usb_clocks(void)
+{
+	uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT;
+
+	imx_clock_set_usb_clk_root_bits(usb_en_bits);
+	imx_clock_enable_usb(CCM_CCGR_ID_USB_IPG);
+	imx_clock_enable_usb(CCM_CCGR_ID_USB_PHY_480MCLK);
+	imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY);
+	imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY);
+}
+
+void imx7_platform_setup(u_register_t arg1, u_register_t arg2,
+			 u_register_t arg3, u_register_t arg4)
+{
+	uint32_t uart5_en_bits = (uint32_t)UART5_CLK_SELECT;
+	uint32_t usdhc_clock_sel = PLAT_PICOPI_SD - 1;
+
+	/* Initialize clocks etc */
+	imx_clock_enable_uart(4, uart5_en_bits);
+	imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT);
+
+	picopi_setup_usb_clocks();
+
+	/* Setup pin-muxes */
+	picopi_setup_pinmux();
+
+	picopi_usdhc_setup();
+}
diff --git a/plat/imx/imx7/picopi/platform.mk b/plat/imx/imx7/picopi/platform.mk
new file mode 100644
index 0000000..5901001
--- /dev/null
+++ b/plat/imx/imx7/picopi/platform.mk
@@ -0,0 +1,40 @@
+#
+# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Include imx7 common
+include plat/imx/imx7/common/imx7.mk
+
+# Platform
+PLAT_INCLUDES		+=	-Iplat/imx/imx7/picopi/include		    \
+
+BL2_SOURCES		+=	drivers/imx/usdhc/imx_usdhc.c		    \
+				plat/imx/imx7/picopi/picopi_bl2_el3_setup.c \
+
+# Build config flags
+# ------------------
+
+ARM_CORTEX_A7			:= yes
+WORKAROUND_CVE_2017_5715	:= 0
+
+RESET_TO_BL31			:= 0
+
+# Non-TF Boot ROM
+BL2_AT_EL3			:= 1
+
+# Indicate single-core
+COLD_BOOT_SINGLE_CPU		:= 1
+
+# Have different sections for code and rodata
+SEPARATE_CODE_AND_RODATA	:= 1
+
+# Use Coherent memory
+USE_COHERENT_MEM		:= 1
+
+# Use multi console API
+MULTI_CONSOLE_API		:= 1
+
+PLAT_PICOPI_UART		:=5
+$(eval $(call add_define,PLAT_PICOPI_UART))
diff --git a/plat/imx/imx7/warp7/include/platform_def.h b/plat/imx/imx7/warp7/include/platform_def.h
index d58382f..4f71908 100644
--- a/plat/imx/imx7/warp7/include/platform_def.h
+++ b/plat/imx/imx7/warp7/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -74,13 +74,13 @@
 #define DRAM_LIMIT			(DRAM_BASE + DRAM_SIZE)
 
 /* Place OPTEE at minus 32 MB from the end of memory. 0x9e000000 - 0xa0000000 */
-#define WARP7_OPTEE_SIZE		0x02000000
-#define WARP7_OPTEE_BASE		(DRAM_LIMIT - WARP7_OPTEE_SIZE)
-#define WARP7_OPTEE_LIMIT		(WARP7_OPTEE_BASE + WARP7_OPTEE_SIZE)
+#define IMX7_OPTEE_SIZE			0x02000000
+#define IMX7_OPTEE_BASE			(DRAM_LIMIT - IMX7_OPTEE_SIZE)
+#define IMX7_OPTEE_LIMIT		(IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
 
 /* Place ATF directly beneath OPTEE. 0x9df00000 - 0x9e000000 */
 #define BL2_RAM_SIZE			0x00100000
-#define BL2_RAM_BASE			(WARP7_OPTEE_BASE - BL2_RAM_SIZE)
+#define BL2_RAM_BASE			(IMX7_OPTEE_BASE - BL2_RAM_SIZE)
 #define BL2_RAM_LIMIT			(BL2_RAM_BASE + BL2_RAM_SIZE)
 
 /* Optional Mailbox. Only relevant on i.MX7D. 0x9deff000 - 0x9df00000*/
@@ -89,28 +89,28 @@
 #define SHARED_RAM_LIMIT		(SHARED_RAM_BASE + SHARED_RAM_SIZE)
 
 /* Define the absolute location of u-boot 0x87800000 - 0x87900000 */
-#define WARP7_UBOOT_SIZE		0x00100000
-#define WARP7_UBOOT_BASE		(DRAM_BASE + 0x7800000)
-#define WARP7_UBOOT_LIMIT		(WARP7_UBOOT_BASE + WARP7_UBOOT_SIZE)
+#define IMX7_UBOOT_SIZE			0x00100000
+#define IMX7_UBOOT_BASE			(DRAM_BASE + 0x7800000)
+#define IMX7_UBOOT_LIMIT		(IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
 
 /* Define FIP image absolute location 0x80000000 - 0x80100000 */
-#define WARP7_FIP_SIZE			0x00100000
-#define WARP7_FIP_BASE			(DRAM_BASE)
-#define WARP7_FIP_LIMIT			(WARP7_FIP_BASE + WARP7_FIP_SIZE)
+#define IMX7_FIP_SIZE			0x00100000
+#define IMX7_FIP_BASE			(DRAM_BASE)
+#define IMX7_FIP_LIMIT			(IMX7_FIP_BASE + IMX7_FIP_SIZE)
 
 /* Define FIP image location at 1MB offset */
-#define WARP7_FIP_MMC_BASE		(1024 * 1024)
+#define IMX7_FIP_MMC_BASE		(1024 * 1024)
 
 /* Define the absolute location of DTB 0x83000000 - 0x83100000 */
-#define WARP7_DTB_SIZE			0x00100000
-#define WARP7_DTB_BASE			(DRAM_BASE + 0x03000000)
-#define WARP7_DTB_LIMIT			(WARP7_DTB_BASE + WARP7_DTB_SIZE)
+#define IMX7_DTB_SIZE			0x00100000
+#define IMX7_DTB_BASE			(DRAM_BASE + 0x03000000)
+#define IMX7_DTB_LIMIT			(IMX7_DTB_BASE + IMX7_DTB_SIZE)
 
 /* Define the absolute location of DTB Overlay 0x83100000 - 0x83101000 */
-#define WARP7_DTB_OVERLAY_SIZE		0x00001000
-#define WARP7_DTB_OVERLAY_BASE		WARP7_DTB_LIMIT
-#define WARP7_DTB_OVERLAY_LIMIT		(WARP7_DTB_OVERLAY_BASE + \
-					 WARP7_DTB_OVERLAY_SIZE)
+#define IMX7_DTB_OVERLAY_SIZE		0x00001000
+#define IMX7_DTB_OVERLAY_BASE		IMX7_DTB_LIMIT
+#define IMX7_DTB_OVERLAY_LIMIT		(IMX7_DTB_OVERLAY_BASE + \
+					 IMX7_DTB_OVERLAY_SIZE)
 
 /*
  * BL2 specific defines.
@@ -124,14 +124,14 @@
 /*
  * BL3-2/OPTEE
  */
-# define BL32_BASE		WARP7_OPTEE_BASE
-# define BL32_LIMIT		(WARP7_OPTEE_BASE + WARP7_OPTEE_SIZE)
+# define BL32_BASE		IMX7_OPTEE_BASE
+# define BL32_LIMIT		(IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
 
 /*
  * BL3-3/U-BOOT
  */
-#define BL33_BASE		WARP7_UBOOT_BASE
-#define BL33_LIMIT		(WARP7_UBOOT_BASE + WARP7_UBOOT_SIZE)
+#define BL33_BASE		IMX7_UBOOT_BASE
+#define BL33_LIMIT		(IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
 
 /*
  * ATF's view of memory
@@ -189,9 +189,9 @@
 #error "define PLAT_WARP7_UART=1 or PLAT_WARP7_UART=6"
 #endif
 
-#define PLAT_WARP7_BOOT_UART_BASE	PLAT_WARP7_UART_BASE
-#define PLAT_WARP7_BOOT_UART_CLK_IN_HZ	24000000
-#define PLAT_WARP7_CONSOLE_BAUDRATE	115200
+#define PLAT_IMX7_BOOT_UART_BASE	PLAT_WARP7_UART_BASE
+#define PLAT_IMX7_BOOT_UART_CLK_IN_HZ	24000000
+#define PLAT_IMX7_CONSOLE_BAUDRATE	115200
 
 /* MMC defines */
 #ifndef PLAT_WARP7_SD
@@ -211,13 +211,6 @@
 #endif /* PLAT_WARP7_SD == 3 */
 
 /*
- * GIC related constants
- */
-#define GICD_BASE			0x31001000
-#define GICC_BASE			0x31002000
-#define GICR_BASE			0
-
-/*
  * System counter
  */
 #define SYS_COUNTER_FREQ_IN_TICKS	8000000		/* 8 MHz */
diff --git a/plat/imx/imx7/warp7/platform.mk b/plat/imx/imx7/warp7/platform.mk
index a93f5e0..ea0f001 100644
--- a/plat/imx/imx7/warp7/platform.mk
+++ b/plat/imx/imx7/warp7/platform.mk
@@ -4,106 +4,21 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
-# Architecture
-$(eval $(call add_define,ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING))
-
-# Tune compiler for Cortex-A7
-ifeq ($(notdir $(CC)),armclang)
-    TF_CFLAGS	+=	-mfpu=neon
-    ASFLAGS	+=	-mfpu=neon
-else ifneq ($(findstring clang,$(notdir $(CC))),)
-    TF_CFLAGS	+=	-mfpu=neon
-    ASFLAGS	+=	-mfpu=neon
-else
-    TF_CFLAGS	+=	-mfpu=neon
-    ASFLAGS	+=	-mfpu=neon
-endif
+# Include imx7 common
+include plat/imx/imx7/common/imx7.mk
 
 # Platform
-PLAT_INCLUDES		:=	-Idrivers/imx/uart			\
-				-Iplat/imx/common/include/		\
-				-Iplat/imx/imx7/warp7/include		\
-				-Idrivers/imx/timer			\
-				-Idrivers/imx/usdhc			\
-				-Iplat/imx/imx7/include
+PLAT_INCLUDES		+= -Iplat/imx/imx7/warp7/include
 
-# Translation tables library
-include lib/xlat_tables_v2/xlat_tables.mk
-
-BL2_SOURCES		+=	common/desc_image_load.c			\
-				drivers/delay_timer/delay_timer.c		\
-				drivers/mmc/mmc.c				\
-				drivers/io/io_block.c				\
-				drivers/io/io_fip.c				\
-				drivers/io/io_memmap.c				\
-				drivers/io/io_storage.c				\
-				drivers/imx/timer/imx_gpt.c			\
-				drivers/imx/uart/imx_uart.c			\
-				drivers/imx/uart/imx_crash_uart.S		\
-				drivers/imx/usdhc/imx_usdhc.c			\
-				lib/aarch32/arm32_aeabi_divmod.c		\
-				lib/aarch32/arm32_aeabi_divmod_a32.S		\
-				lib/cpus/aarch32/cortex_a7.S			\
-				lib/optee/optee_utils.c				\
-				plat/imx/common/imx_aips.c			\
-				plat/imx/common/imx_caam.c			\
-				plat/imx/common/imx_clock.c			\
-				plat/imx/common/imx_csu.c			\
-				plat/imx/common/imx_io_mux.c			\
-				plat/imx/common/imx_snvs.c			\
-				plat/imx/common/imx_wdog.c			\
-				plat/imx/common/imx7_clock.c		\
-				plat/imx/imx7/warp7/aarch32/warp7_helpers.S	\
-				plat/imx/imx7/warp7/warp7_bl2_el3_setup.c	\
-				plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c \
-				plat/imx/imx7/warp7/warp7_io_storage.c		\
-				plat/imx/imx7/warp7/warp7_image_load.c		\
-				plat/imx/common/aarch32/imx_uart_console.S	\
-				${XLAT_TABLES_LIB_SRCS}
-
-ifneq (${TRUSTED_BOARD_BOOT},0)
-
-include drivers/auth/mbedtls/mbedtls_crypto.mk
-include drivers/auth/mbedtls/mbedtls_x509.mk
-
-AUTH_SOURCES	:=	drivers/auth/auth_mod.c			\
-			drivers/auth/crypto_mod.c		\
-			drivers/auth/img_parser_mod.c		\
-			drivers/auth/tbbr/tbbr_cot.c
-
-BL2_SOURCES		+=	${AUTH_SOURCES}					\
-				plat/common/tbbr/plat_tbbr.c			\
-				plat/imx/imx7/warp7/warp7_trusted_boot.c	\
-				plat/imx/imx7/warp7/warp7_rotpk.S
-
-ROT_KEY             = $(BUILD_PLAT)/rot_key.pem
-ROTPK_HASH          = $(BUILD_PLAT)/rotpk_sha256.bin
-
-$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
-$(eval $(call MAKE_LIB_DIRS))
-
-$(BUILD_PLAT)/bl2/warp7_rotpk.o: $(ROTPK_HASH)
-
-certificates: $(ROT_KEY)
-
-$(ROT_KEY): | $(BUILD_PLAT)
-	@echo "  OPENSSL $@"
-	@if [ ! -f $(ROT_KEY) ]; then \
-		openssl genrsa 2048 > $@ 2>/dev/null; \
-	fi
-
-$(ROTPK_HASH): $(ROT_KEY)
-	@echo "  OPENSSL $@"
-	$(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
-	openssl dgst -sha256 -binary > $@ 2>/dev/null
-endif
+BL2_SOURCES		+=	drivers/imx/usdhc/imx_usdhc.c			\
+				plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
 
 # Build config flags
 # ------------------
 
+ARM_CORTEX_A7			:= yes
 WORKAROUND_CVE_2017_5715	:= 0
 
-# Enable reset to BL31 by default
 RESET_TO_BL31			:= 0
 
 # Non-TF Boot ROM
@@ -118,28 +33,5 @@
 # Use Coherent memory
 USE_COHERENT_MEM		:= 1
 
-# PLAT_WARP7_UART
 PLAT_WARP7_UART			:=1
 $(eval $(call add_define,PLAT_WARP7_UART))
-
-# Add the build options to pack BLx images and kernel device tree
-# in the FIP if the platform requires.
-ifneq ($(BL2),)
-$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert))
-endif
-ifneq ($(BL32_EXTRA1),)
-$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
-endif
-ifneq ($(BL32_EXTRA2),)
-$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
-endif
-ifneq ($(HW_CONFIG),)
-$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config))
-endif
-
-# Verify build config
-# -------------------
-
-ifeq (${ARCH},aarch64)
-  $(error Error: AArch64 not supported on i.mx7)
-endif
diff --git a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
index 0eedd21..935a411 100644
--- a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
+++ b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,30 +8,17 @@
 
 #include <platform_def.h>
 
-#include <arch_helpers.h>
-#include <common/bl_common.h>
 #include <common/debug.h>
-#include <common/desc_image_load.h>
 #include <drivers/console.h>
 #include <drivers/mmc.h>
-#include <lib/xlat_tables/xlat_mmu_helpers.h>
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <lib/mmio.h>
-#include <lib/optee_utils.h>
 #include <lib/utils.h>
 
-#include <imx_aips.h>
 #include <imx_caam.h>
 #include <imx_clock.h>
-#include <imx_csu.h>
-#include <imx_gpt.h>
 #include <imx_io_mux.h>
 #include <imx_uart.h>
-#include <imx_snvs.h>
 #include <imx_usdhc.h>
-#include <imx_wdog.h>
-
-#include "warp7_private.h"
+#include <imx7_def.h>
 
 #define UART1_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
 			  CCM_TRGT_MUX_UART1_CLK_ROOT_OSC_24M)
@@ -43,102 +30,9 @@
 			  CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\
 			  CCM_TARGET_POST_PODF(2))
 
-#define WDOG_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
-			 CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M)
-
 #define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
 			CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL)
 
-uintptr_t plat_get_ns_image_entrypoint(void)
-{
-	return WARP7_UBOOT_BASE;
-}
-
-static uint32_t warp7_get_spsr_for_bl32_entry(void)
-{
-	return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
-			   DISABLE_ALL_EXCEPTIONS);
-}
-
-static uint32_t warp7_get_spsr_for_bl33_entry(void)
-{
-	return SPSR_MODE32(MODE32_svc,
-			   plat_get_ns_image_entrypoint() & 0x1,
-			   SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
-}
-
-#ifndef AARCH32_SP_OPTEE
-#error "Must build with OPTEE support included"
-#endif
-
-int bl2_plat_handle_post_image_load(unsigned int image_id)
-{
-	int err = 0;
-	bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
-	bl_mem_params_node_t *hw_cfg_mem_params = NULL;
-
-	bl_mem_params_node_t *pager_mem_params = NULL;
-	bl_mem_params_node_t *paged_mem_params = NULL;
-
-	assert(bl_mem_params);
-
-	switch (image_id) {
-	case BL32_IMAGE_ID:
-		pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
-		assert(pager_mem_params);
-
-		paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
-		assert(paged_mem_params);
-
-		err = parse_optee_header(&bl_mem_params->ep_info,
-					 &pager_mem_params->image_info,
-					 &paged_mem_params->image_info);
-		if (err != 0)
-			WARN("OPTEE header parse error.\n");
-
-		/*
-		 * When ATF loads the DTB the address of the DTB is passed in
-		 * arg2, if an hw config image is present use the base address
-		 * as DTB address an pass it as arg2
-		 */
-		hw_cfg_mem_params = get_bl_mem_params_node(HW_CONFIG_ID);
-
-		bl_mem_params->ep_info.args.arg0 =
-					bl_mem_params->ep_info.args.arg1;
-		bl_mem_params->ep_info.args.arg1 = 0;
-		if (hw_cfg_mem_params)
-			bl_mem_params->ep_info.args.arg2 =
-					hw_cfg_mem_params->image_info.image_base;
-		else
-			bl_mem_params->ep_info.args.arg2 = 0;
-		bl_mem_params->ep_info.args.arg3 = 0;
-		bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl32_entry();
-		break;
-
-	case BL33_IMAGE_ID:
-		/* AArch32 only core: OP-TEE expects NSec EP in register LR */
-		pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
-		assert(pager_mem_params);
-		pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
-
-		/* BL33 expects to receive the primary CPU MPID (through r0) */
-		bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
-		bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl33_entry();
-		break;
-
-	default:
-		/* Do nothing in default case */
-		break;
-	}
-
-	return err;
-}
-
-void bl2_el3_plat_arch_setup(void)
-{
-	/* Setup the MMU here */
-}
-
 #define WARP7_UART1_TX_MUX \
 	IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT0_UART1_TX_DATA
 
@@ -215,29 +109,6 @@
 	imx_usdhc_init(&params, &info);
 }
 
-static void warp7_setup_system_counter(void)
-{
-	unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS;
-
-	/* Set the frequency table index to our target frequency */
-	write_cntfrq(freq);
-
-	/* Enable system counter @ frequency table index 0, halt on debug */
-	mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF,
-		      CNTCR_FCREQ(0) | CNTCR_HDBG | CNTCR_EN);
-}
-
-static void warp7_setup_wdog_clocks(void)
-{
-	uint32_t wdog_en_bits = (uint32_t)WDOG_CLK_SELECT;
-
-	imx_clock_set_wdog_clk_root_bits(wdog_en_bits);
-	imx_clock_enable_wdog(0);
-	imx_clock_enable_wdog(1);
-	imx_clock_enable_wdog(2);
-	imx_clock_enable_wdog(3);
-}
-
 static void warp7_setup_usb_clocks(void)
 {
 	uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT;
@@ -248,67 +119,24 @@
 	imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY);
 	imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY);
 }
-/*
- * bl2_el3_early_platform_setup()
- * MMU off
- */
-void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
-				  u_register_t arg3, u_register_t arg4)
+
+void imx7_platform_setup(u_register_t arg1, u_register_t arg2,
+			 u_register_t arg3, u_register_t arg4)
 {
 	uint32_t uart1_en_bits = (uint32_t)UART1_CLK_SELECT;
 	uint32_t uart6_en_bits = (uint32_t)UART6_CLK_SELECT;
 	uint32_t usdhc_clock_sel = PLAT_WARP7_SD - 1;
-	static console_imx_uart_t console;
-	int console_scope = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME;
 
-	/* Initialize the AIPS */
-	imx_aips_init();
-	imx_csu_init();
-	imx_snvs_init();
-	imx_gpt_ops_init(GPT1_BASE_ADDR);
-
-	/* Initialize clocks, regulators, pin-muxes etc */
-	imx_clock_init();
+	/* Initialize clocks etc */
 	imx_clock_enable_uart(0, uart1_en_bits);
 	imx_clock_enable_uart(5, uart6_en_bits);
+
 	imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT);
-	warp7_setup_system_counter();
-	warp7_setup_wdog_clocks();
+
 	warp7_setup_usb_clocks();
 
 	/* Setup pin-muxes */
 	warp7_setup_pinmux();
 
-	/* Init UART, storage and friends */
-	console_imx_uart_register(PLAT_WARP7_BOOT_UART_BASE,
-				  PLAT_WARP7_BOOT_UART_CLK_IN_HZ,
-				  PLAT_WARP7_CONSOLE_BAUDRATE,
-				  &console);
-	console_set_scope(&console.console, console_scope);
-
 	warp7_usdhc_setup();
-
-	/* Open handles to persistent storage */
-	plat_warp7_io_setup();
-
-	/* Setup higher-level functionality CAAM, RTC etc */
-	imx_caam_init();
-	imx_wdog_init();
-
-	/* Print out the expected memory map */
-	VERBOSE("\tOPTEE       0x%08x-0x%08x\n", WARP7_OPTEE_BASE, WARP7_OPTEE_LIMIT);
-	VERBOSE("\tATF/BL2     0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT);
-	VERBOSE("\tSHRAM       0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT);
-	VERBOSE("\tFIP         0x%08x-0x%08x\n", WARP7_FIP_BASE, WARP7_FIP_LIMIT);
-	VERBOSE("\tDTB-OVERLAY 0x%08x-0x%08x\n", WARP7_DTB_OVERLAY_BASE, WARP7_DTB_OVERLAY_LIMIT);
-	VERBOSE("\tDTB         0x%08x-0x%08x\n", WARP7_DTB_BASE, WARP7_DTB_LIMIT);
-	VERBOSE("\tUBOOT/BL33  0x%08x-0x%08x\n", WARP7_UBOOT_BASE, WARP7_UBOOT_LIMIT);
-}
-
-/*
- * bl2_platform_setup()
- * MMU on - enabled by bl2_el3_plat_arch_setup()
- */
-void bl2_platform_setup(void)
-{
 }
diff --git a/plat/imx/imx7/warp7/warp7_private.h b/plat/imx/imx7/warp7/warp7_private.h
deleted file mode 100644
index cb6d900..0000000
--- a/plat/imx/imx7/warp7/warp7_private.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef WARP7_PRIVATE_H
-#define WARP7_PRIVATE_H
-
-/*******************************************************************************
- * Function and variable prototypes
- ******************************************************************************/
-void plat_warp7_io_setup(void);
-
-#endif /* WARP7_PRIVATE_H */
diff --git a/plat/imx/imx7/warp7/warp7_rotpk.S b/plat/imx/imx7/warp7/warp7_rotpk.S
deleted file mode 100644
index f74b6d2..0000000
--- a/plat/imx/imx7/warp7/warp7_rotpk.S
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-	.global warp7_rotpk_hash
-	.global warp7_rotpk_hash_end
-warp7_rotpk_hash:
-	/* DER header */
-	.byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48
-	.byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20
-	/* SHA256 */
-	.incbin ROTPK_HASH
-warp7_rotpk_hash_end:
diff --git a/plat/marvell/a3700/common/a3700_common.mk b/plat/marvell/a3700/common/a3700_common.mk
index 64cd433..1e27567 100644
--- a/plat/marvell/a3700/common/a3700_common.mk
+++ b/plat/marvell/a3700/common/a3700_common.mk
@@ -13,6 +13,7 @@
 PLAT_COMMON_BASE		:= $(PLAT_FAMILY_BASE)/common
 MARVELL_DRV_BASE		:= drivers/marvell
 MARVELL_COMMON_BASE		:= $(MARVELL_PLAT_BASE)/common
+HANDLE_EA_EL3_FIRST		:= 1
 
 include $(MARVELL_PLAT_BASE)/marvell.mk
 
@@ -107,6 +108,7 @@
 				$(PLAT_COMMON_BASE)/dram_win.c		\
 				$(PLAT_COMMON_BASE)/io_addr_dec.c	\
 				$(PLAT_COMMON_BASE)/marvell_plat_config.c     \
+				$(PLAT_COMMON_BASE)/a3700_ea.c		\
 				$(PLAT_FAMILY_BASE)/$(PLAT)/plat_bl31_setup.c \
 				$(MARVELL_COMMON_BASE)/marvell_ddr_info.c	\
 				$(MARVELL_COMMON_BASE)/marvell_gicv3.c	\
diff --git a/plat/marvell/a3700/common/a3700_ea.c b/plat/marvell/a3700/common/a3700_ea.c
new file mode 100644
index 0000000..dd46beb
--- /dev/null
+++ b/plat/marvell/a3700/common/a3700_ea.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2019 Repk repk@triplefau.lt
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <arch_helpers.h>
+
+#define ADVK_SERROR_SYNDROME 0xbf000002
+
+void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
+		void *handle, uint64_t flags)
+{
+	if (syndrome != ADVK_SERROR_SYNDROME) {
+		ERROR("Unhandled External Abort received on 0x%lx at EL3!\n",
+			read_mpidr_el1());
+		ERROR(" exception reason=%u syndrome=0x%llx\n", ea_reason,
+				syndrome);
+		panic();
+	}
+}
diff --git a/plat/marvell/common/aarch64/marvell_common.c b/plat/marvell/common/aarch64/marvell_common.c
index ea0902c..21a62d4 100644
--- a/plat/marvell/common/aarch64/marvell_common.c
+++ b/plat/marvell/common/aarch64/marvell_common.c
@@ -13,7 +13,7 @@
 #include <arch_helpers.h>
 #include <common/debug.h>
 #include <lib/mmio.h>
-#include <lib/xlat_tables/xlat_tables.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
 
 #include <plat_marvell.h>
 
diff --git a/plat/marvell/common/marvell_common.mk b/plat/marvell/common/marvell_common.mk
index 5c8e804..f41d7a4 100644
--- a/plat/marvell/common/marvell_common.mk
+++ b/plat/marvell/common/marvell_common.mk
@@ -20,12 +20,13 @@
 LLC_ENABLE			:= 1
 $(eval $(call add_define,LLC_ENABLE))
 
+include lib/xlat_tables_v2/xlat_tables.mk
+
 PLAT_INCLUDES		+=	-I$(MARVELL_PLAT_INCLUDE_BASE)/common	\
 				-I$(MARVELL_PLAT_INCLUDE_BASE)/common/aarch64
 
 
-PLAT_BL_COMMON_SOURCES  +=      lib/xlat_tables/xlat_tables_common.c			\
-				lib/xlat_tables/aarch64/xlat_tables.c			\
+PLAT_BL_COMMON_SOURCES  += ${XLAT_TABLES_LIB_SRCS} \
 				$(MARVELL_PLAT_BASE)/common/aarch64/marvell_common.c	\
 				$(MARVELL_PLAT_BASE)/common/aarch64/marvell_helpers.S	\
 				$(MARVELL_COMMON_BASE)/marvell_console.c
diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c
index dd23e63..ad81b16 100644
--- a/plat/mediatek/mt8173/bl31_plat_setup.c
+++ b/plat/mediatek/mt8173/bl31_plat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,7 @@
 
 #include <common/bl_common.h>
 #include <common/debug.h>
+#include <common/desc_image_load.h>
 #include <drivers/console.h>
 #include <drivers/generic_delay_timer.h>
 #include <lib/mmio.h>
@@ -79,6 +80,7 @@
 	entry_point_info_t *next_image_info;
 
 	next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
+	assert(next_image_info->h.type == PARAM_EP);
 
 	/* None of the images on this platform can have 0x0 as the entrypoint */
 	if (next_image_info->pc)
@@ -98,18 +100,11 @@
 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 				u_register_t arg2, u_register_t arg3)
 {
-	struct mtk_bl31_params *arg_from_bl2 = (struct mtk_bl31_params *)arg0;
-
 	console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE);
 
 	VERBOSE("bl31_setup\n");
 
-	assert(arg_from_bl2 != NULL);
-	assert(arg_from_bl2->h.type == PARAM_BL31);
-	assert(arg_from_bl2->h.version >= VERSION_1);
-
-	bl32_ep_info = *arg_from_bl2->bl32_ep_info;
-	bl33_ep_info = *arg_from_bl2->bl33_ep_info;
+	bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
 }
 
 /*******************************************************************************
diff --git a/plat/mediatek/mt8173/platform.mk b/plat/mediatek/mt8173/platform.mk
index 0726efe..24e4ec6 100644
--- a/plat/mediatek/mt8173/platform.mk
+++ b/plat/mediatek/mt8173/platform.mk
@@ -23,7 +23,8 @@
 				plat/arm/common/arm_gicv2.c			\
 				plat/common/plat_gicv2.c
 
-BL31_SOURCES		+=	drivers/arm/cci/cci.c				\
+BL31_SOURCES		+=	common/desc_image_load.c			\
+				drivers/arm/cci/cci.c				\
 				drivers/arm/gic/common/gic_common.c		\
 				drivers/arm/gic/v2/gicv2_main.c			\
 				drivers/arm/gic/v2/gicv2_helpers.c		\
diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c
index b451189..e623e96 100644
--- a/plat/mediatek/mt8183/bl31_plat_setup.c
+++ b/plat/mediatek/mt8183/bl31_plat_setup.c
@@ -7,6 +7,7 @@
 #include <assert.h>
 #include <arch_helpers.h>
 #include <common/bl_common.h>
+#include <common/desc_image_load.h>
 #include <plat/common/common_def.h>
 #include <drivers/console.h>
 #include <common/debug.h>
@@ -50,6 +51,7 @@
 	entry_point_info_t *next_image_info;
 
 	next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
+	assert(next_image_info->h.type == PARAM_EP);
 
 	/* None of the images on this platform can have 0x0 as the entrypoint */
 	if (next_image_info->pc)
@@ -69,19 +71,13 @@
 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 				u_register_t arg2, u_register_t arg3)
 {
-	struct mtk_bl31_params *arg_from_bl2 = (struct mtk_bl31_params *)arg0;
 	static console_16550_t console;
 
 	console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console);
 
 	NOTICE("MT8183 bl31_setup\n");
 
-	assert(arg_from_bl2 != NULL);
-	assert(arg_from_bl2->h.type == PARAM_BL31);
-	assert(arg_from_bl2->h.version >= VERSION_1);
-
-	bl32_ep_info = *arg_from_bl2->bl32_ep_info;
-	bl33_ep_info = *arg_from_bl2->bl33_ep_info;
+	bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
 }
 
 
diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk
index 8c8e2fe..f0a598a 100644
--- a/plat/mediatek/mt8183/platform.mk
+++ b/plat/mediatek/mt8183/platform.mk
@@ -16,7 +16,8 @@
                           plat/common/plat_psci_common.c              \
                           plat/common/aarch64/crash_console_helpers.S
 
-BL31_SOURCES    += drivers/arm/cci/cci.c                                 \
+BL31_SOURCES    += common/desc_image_load.c                              \
+                   drivers/arm/cci/cci.c                                 \
                    drivers/arm/gic/common/gic_common.c                   \
                    drivers/arm/gic/v3/arm_gicv3_common.c                 \
                    drivers/arm/gic/v3/gicv3_helpers.c                    \
diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c
index 18f8dd9..a13ee49 100644
--- a/plat/rockchip/common/bl31_plat_setup.c
+++ b/plat/rockchip/common/bl31_plat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +10,7 @@
 
 #include <common/bl_common.h>
 #include <common/debug.h>
+#include <common/desc_image_load.h>
 #include <drivers/console.h>
 #include <drivers/generic_delay_timer.h>
 #include <drivers/ti/uart/uart_16550.h>
@@ -32,6 +33,7 @@
 	entry_point_info_t *next_image_info;
 
 	next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
+	assert(next_image_info->h.type == PARAM_EP);
 
 	/* None of the images on this platform can have 0x0 as the entrypoint */
 	if (next_image_info->pc)
@@ -41,7 +43,7 @@
 }
 
 #pragma weak params_early_setup
-void params_early_setup(void *plat_param_from_bl2)
+void params_early_setup(u_register_t plat_param_from_bl2)
 {
 }
 
@@ -57,10 +59,8 @@
 				u_register_t arg2, u_register_t arg3)
 {
 	static console_16550_t console;
-	struct rockchip_bl31_params *arg_from_bl2 = (struct rockchip_bl31_params *) arg0;
-	void *plat_params_from_bl2 = (void *) arg1;
 
-	params_early_setup(plat_params_from_bl2);
+	params_early_setup(arg1);
 
 #if COREBOOT
 	if (coreboot_serial.type)
@@ -75,14 +75,7 @@
 
 	VERBOSE("bl31_setup\n");
 
-	/* Passing a NULL context is a critical programming error */
-	assert(arg_from_bl2);
-
-	assert(arg_from_bl2->h.type == PARAM_BL31);
-	assert(arg_from_bl2->h.version >= VERSION_1);
-
-	bl32_ep_info = *arg_from_bl2->bl32_ep_info;
-	bl33_ep_info = *arg_from_bl2->bl33_ep_info;
+	bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
 }
 
 /*******************************************************************************
diff --git a/plat/rockchip/common/include/plat_params.h b/plat/rockchip/common/include/plat_params.h
index 1ec02f5..95b850f 100644
--- a/plat/rockchip/common/include/plat_params.h
+++ b/plat/rockchip/common/include/plat_params.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,90 +9,6 @@
 
 #include <stdint.h>
 
-/*
- * We defined several plat parameter structs for BL2 to pass platform related
- * parameters to Rockchip BL31 platform code.  All plat parameters start with
- * a common header, which has a type field to indicate the parameter type, and
- * a next pointer points to next parameter. If the parameter is the last one in
- * the list, next pointer will points to NULL.  After the header comes the
- * variable-sized members that describe the parameter. The picture below shows
- * how the parameters are kept in memory.
- *
- * head of list  ---> +----------------+ --+
- *                    |      type      |   |
- *                    +----------------+   |--> struct bl31_plat_param
- *               +----|      next      |   |
- *               |    +----------------+ --+
- *               |    | parameter data |
- *               |    +----------------+
- *               |
- *               +--> +----------------+ --+
- *                    |      type      |   |
- *                    +----------------+   |--> struct bl31_plat_param
- *           NULL <---|      next      |   |
- *                    +----------------+ --+
- *                    | parameter data |
- *                    +----------------+
- *
- * Note: The SCTLR_EL3.A bit (Alignment fault check enable) of ARM TF is set,
- * so be sure each parameter struct starts on 64-bit aligned address. If not,
- * alignment fault will occur during accessing its data member.
- */
-
-#define BL31_GPIO_DIR_OUT		0
-#define BL31_GPIO_DIR_IN		1
-
-#define BL31_GPIO_LEVEL_LOW		0
-#define BL31_GPIO_LEVEL_HIGH		1
-
-#define BL31_GPIO_PULL_NONE		0
-#define BL31_GPIO_PULL_UP		1
-#define BL31_GPIO_PULL_DOWN		2
-
-/* param type */
-enum {
-	PARAM_NONE = 0,
-	PARAM_RESET,
-	PARAM_POWEROFF,
-	PARAM_SUSPEND_GPIO,
-	PARAM_SUSPEND_APIO,
-	PARAM_COREBOOT_TABLE,
-};
-
-struct apio_info {
-	uint8_t apio1 : 1;
-	uint8_t apio2 : 1;
-	uint8_t apio3 : 1;
-	uint8_t apio4 : 1;
-	uint8_t apio5 : 1;
-};
-
-struct gpio_info {
-	uint8_t polarity;
-	uint8_t direction;
-	uint8_t pull_mode;
-	uint32_t index;
-};
-
-/* common header for all plat parameter type */
-struct bl31_plat_param {
-	uint64_t type;
-	void *next;
-};
-
-struct bl31_gpio_param {
-	struct bl31_plat_param h;
-	struct gpio_info gpio;
-};
-
-struct bl31_apio_param {
-	struct bl31_plat_param h;
-	struct apio_info apio;
-};
-
-struct bl31_u64_param {
-	struct bl31_plat_param h;
-	uint64_t value;
-};
+#include <export/plat/rockchip/common/plat_params_exp.h>
 
 #endif /* PLAT_PARAMS_H */
diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h
index c0ebefc..66b6185 100644
--- a/plat/rockchip/common/include/plat_private.h
+++ b/plat/rockchip/common/include/plat_private.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -14,6 +14,7 @@
 #include <lib/psci/psci.h>
 #include <lib/xlat_tables/xlat_tables.h>
 #include <lib/mmio.h>
+#include <plat_params.h>
 
 #define __sramdata __attribute__((section(".sram.data")))
 #define __sramconst __attribute__((section(".sram.rodata")))
@@ -30,15 +31,6 @@
 extern uint32_t __sram_incbin_start, __sram_incbin_end;
 extern uint32_t __sram_incbin_real_end;
 
-struct rockchip_bl31_params {
-       param_header_t h;
-       image_info_t *bl31_image_info;
-       entry_point_info_t *bl32_ep_info;
-       image_info_t *bl32_image_info;
-       entry_point_info_t *bl33_ep_info;
-       image_info_t *bl33_image_info;
-};
-
 /******************************************************************************
  * The register have write-mask bits, it is mean, if you want to set the bits,
  * you needs set the write-mask bits at the same time,
@@ -94,7 +86,7 @@
 
 void plat_delay_timer_init(void);
 
-void params_early_setup(void *plat_params_from_bl2);
+void params_early_setup(u_register_t plat_params_from_bl2);
 
 void plat_rockchip_gic_driver_init(void);
 void plat_rockchip_gic_init(void);
@@ -108,10 +100,10 @@
 
 void platform_cpu_warmboot(void);
 
-struct gpio_info *plat_get_rockchip_gpio_reset(void);
-struct gpio_info *plat_get_rockchip_gpio_poweroff(void);
-struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count);
-struct apio_info *plat_get_rockchip_suspend_apio(void);
+struct bl_aux_gpio_info *plat_get_rockchip_gpio_reset(void);
+struct bl_aux_gpio_info *plat_get_rockchip_gpio_poweroff(void);
+struct bl_aux_gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count);
+struct bl_aux_rk_apio_info *plat_get_rockchip_suspend_apio(void);
 void plat_rockchip_gpio_init(void);
 void plat_rockchip_save_gpio(void);
 void plat_rockchip_restore_gpio(void);
diff --git a/plat/rockchip/common/params_setup.c b/plat/rockchip/common/params_setup.c
index 8a743bf..d0fea4f 100644
--- a/plat/rockchip/common/params_setup.c
+++ b/plat/rockchip/common/params_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,7 @@
 #include <errno.h>
 #include <string.h>
 
+#include <lib/bl_aux_params/bl_aux_params.h>
 #include <common/bl_common.h>
 #include <common/debug.h>
 #include <drivers/console.h>
@@ -20,14 +21,11 @@
 #include <plat_params.h>
 #include <plat_private.h>
 
-static struct gpio_info param_reset;
-static struct gpio_info param_poweroff;
-static struct bl31_apio_param param_apio;
-static struct gpio_info *rst_gpio;
-static struct gpio_info *poweroff_gpio;
-static struct gpio_info suspend_gpio[10];
+static struct bl_aux_gpio_info rst_gpio;
+static struct bl_aux_gpio_info poweroff_gpio;
+static struct bl_aux_gpio_info suspend_gpio[10];
 uint32_t suspend_gpio_cnt;
-static struct apio_info *suspend_apio;
+static struct bl_aux_rk_apio_info suspend_apio;
 static uint32_t rk_uart_base = PLAT_RK_UART_BASE;
 
 uint32_t rockchip_get_uart_base(void)
@@ -36,7 +34,7 @@
 }
 
 #if COREBOOT
-static int dt_process_fdt(void *blob)
+static int dt_process_fdt(u_register_t param_from_bl2)
 {
 	return -ENODEV;
 }
@@ -105,12 +103,12 @@
 	rk_uart_base = uart_base;
 }
 
-static int dt_process_fdt(void *blob)
+static int dt_process_fdt(u_register_t param_from_bl2)
 {
 	void *fdt = plat_get_fdt();
 	int ret;
 
-	ret = fdt_open_into(blob, fdt, 0x10000);
+	ret = fdt_open_into((void *)param_from_bl2, fdt, 0x10000);
 	if (ret < 0)
 		return ret;
 
@@ -120,33 +118,56 @@
 }
 #endif
 
-struct gpio_info *plat_get_rockchip_gpio_reset(void)
+struct bl_aux_gpio_info *plat_get_rockchip_gpio_reset(void)
 {
-	return rst_gpio;
+	return &rst_gpio;
 }
 
-struct gpio_info *plat_get_rockchip_gpio_poweroff(void)
+struct bl_aux_gpio_info *plat_get_rockchip_gpio_poweroff(void)
 {
-	return poweroff_gpio;
+	return &poweroff_gpio;
 }
 
-struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count)
+struct bl_aux_gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count)
 {
 	*count = suspend_gpio_cnt;
 
 	return &suspend_gpio[0];
 }
 
-struct apio_info *plat_get_rockchip_suspend_apio(void)
+struct bl_aux_rk_apio_info *plat_get_rockchip_suspend_apio(void)
 {
-	return suspend_apio;
+	return &suspend_apio;
 }
 
-void params_early_setup(void *plat_param_from_bl2)
+static bool rk_aux_param_handler(struct bl_aux_param_header *param)
 {
-	struct bl31_plat_param *bl2_param;
-	struct bl31_gpio_param *gpio_param;
+	/* Store platform parameters for later processing if needed. */
+	switch (param->type) {
+	case BL_AUX_PARAM_RK_RESET_GPIO:
+		rst_gpio = ((struct bl_aux_param_gpio *)param)->gpio;
+		return true;
+	case BL_AUX_PARAM_RK_POWEROFF_GPIO:
+		poweroff_gpio = ((struct bl_aux_param_gpio *)param)->gpio;
+		return true;
+	case BL_AUX_PARAM_RK_SUSPEND_GPIO:
+		if (suspend_gpio_cnt >= ARRAY_SIZE(suspend_gpio)) {
+			ERROR("Exceeded the supported suspend GPIO number.\n");
+			return true;
+		}
+		suspend_gpio[suspend_gpio_cnt++] =
+			((struct bl_aux_param_gpio *)param)->gpio;
+		return true;
+	case BL_AUX_PARAM_RK_SUSPEND_APIO:
+		suspend_apio = ((struct bl_aux_param_rk_apio *)param)->apio;
+		return true;
+	}
 
+	return false;
+}
+
+void params_early_setup(u_register_t plat_param_from_bl2)
+{
 	/*
 	 * Test if this is a FDT passed as a platform-specific parameter
 	 * block.
@@ -154,49 +175,5 @@
 	if (!dt_process_fdt(plat_param_from_bl2))
 		return;
 
-	/* keep plat parameters for later processing if need */
-	bl2_param = (struct bl31_plat_param *)plat_param_from_bl2;
-	while (bl2_param) {
-		switch (bl2_param->type) {
-		case PARAM_RESET:
-			gpio_param = (struct bl31_gpio_param *)bl2_param;
-			memcpy(&param_reset, &gpio_param->gpio,
-			       sizeof(struct gpio_info));
-			rst_gpio = &param_reset;
-			break;
-		case PARAM_POWEROFF:
-			gpio_param = (struct bl31_gpio_param *)bl2_param;
-			memcpy(&param_poweroff, &gpio_param->gpio,
-				sizeof(struct gpio_info));
-			poweroff_gpio = &param_poweroff;
-			break;
-		case PARAM_SUSPEND_GPIO:
-			if (suspend_gpio_cnt >= ARRAY_SIZE(suspend_gpio)) {
-				ERROR("exceed support suspend gpio number\n");
-				break;
-			}
-			gpio_param = (struct bl31_gpio_param *)bl2_param;
-			memcpy(&suspend_gpio[suspend_gpio_cnt],
-			       &gpio_param->gpio,
-			       sizeof(struct gpio_info));
-			suspend_gpio_cnt++;
-			break;
-		case PARAM_SUSPEND_APIO:
-			memcpy(&param_apio, bl2_param,
-			       sizeof(struct bl31_apio_param));
-			suspend_apio = &param_apio.apio;
-			break;
-#if COREBOOT
-		case PARAM_COREBOOT_TABLE:
-			coreboot_table_setup((void *)
-				((struct bl31_u64_param *)bl2_param)->value);
-			break;
-#endif
-		default:
-			ERROR("not expected type found %lld\n",
-			      bl2_param->type);
-			break;
-		}
-		bl2_param = bl2_param->next;
-	}
+	bl_aux_params_parse(plat_param_from_bl2, rk_aux_param_handler);
 }
diff --git a/plat/rockchip/common/sp_min_plat_setup.c b/plat/rockchip/common/sp_min_plat_setup.c
index 7cdbaba..7b1a0b5 100644
--- a/plat/rockchip/common/sp_min_plat_setup.c
+++ b/plat/rockchip/common/sp_min_plat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,6 +11,7 @@
 #include <arch_helpers.h>
 #include <common/bl_common.h>
 #include <common/debug.h>
+#include <common/desc_image_load.h>
 #include <drivers/console.h>
 #include <drivers/generic_delay_timer.h>
 #include <drivers/ti/uart/uart_16550.h>
@@ -40,7 +41,7 @@
 }
 
 #pragma weak params_early_setup
-void params_early_setup(void *plat_param_from_bl2)
+void params_early_setup(u_register_t plat_param_from_bl2)
 {
 }
 
@@ -53,10 +54,8 @@
 				  u_register_t arg2, u_register_t arg3)
 {
 	static console_16550_t console;
-	struct rockchip_bl31_params *arg_from_bl2 = (struct rockchip_bl31_params *) arg0;
-	void *plat_params_from_bl2 = (void *) arg1;
 
-	params_early_setup(plat_params_from_bl2);
+	params_early_setup(arg1);
 
 #if COREBOOT
 	if (coreboot_serial.type)
@@ -70,13 +69,7 @@
 #endif
 	VERBOSE("sp_min_setup\n");
 
-	/* Passing a NULL context is a critical programming error */
-	assert(arg_from_bl2);
-
-	assert(arg_from_bl2->h.type == PARAM_BL31);
-	assert(arg_from_bl2->h.version >= VERSION_1);
-
-	bl33_ep_info = *arg_from_bl2->bl33_ep_info;
+	bl31_params_parse_helper(arg0, NULL, &bl33_ep_info);
 }
 
 /*******************************************************************************
diff --git a/plat/rockchip/px30/drivers/pmu/pmu.c b/plat/rockchip/px30/drivers/pmu/pmu.c
index a5ed766..0a2515d 100644
--- a/plat/rockchip/px30/drivers/pmu/pmu.c
+++ b/plat/rockchip/px30/drivers/pmu/pmu.c
@@ -626,13 +626,13 @@
 
 	/* select pvtm as 32k source */
 	mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKSELS_CON(0),
-		      BITS_WITH_WMASK(1, 0x3, 14));
+		      BITS_WITH_WMASK(1, 0x3U, 14));
 }
 
 static void pvtm_32k_config_restore(void)
 {
 	mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKSELS_CON(0),
-		      ddr_data.pmu_cru_clksel_con0 | BITS_WMSK(0x3, 14));
+		      ddr_data.pmu_cru_clksel_con0 | BITS_WMSK(0x3U, 14));
 
 	mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0,
 		      WITH_16BITS_WMSK(ddr_data.pgrf_pvtm_con[0]));
@@ -869,7 +869,7 @@
 static inline void pll_pwr_ctr(uint32_t pll_base, uint32_t pll_id, uint32_t pd)
 {
 	mmio_write_32(pll_base + PLL_CON(1),
-		      BITS_WITH_WMASK(1, 1, 15));
+		      BITS_WITH_WMASK(1, 1U, 15));
 	if (pd)
 		mmio_write_32(pll_base + PLL_CON(1),
 			      BITS_WITH_WMASK(1, 1, 14));
diff --git a/plat/rockchip/rk3288/platform.mk b/plat/rockchip/rk3288/platform.mk
index 1811b3a..faf7a15 100644
--- a/plat/rockchip/rk3288/platform.mk
+++ b/plat/rockchip/rk3288/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -30,7 +30,9 @@
 				plat/common/plat_gicv2.c			\
 				${RK_PLAT}/common/rockchip_gicv2.c
 
-PLAT_BL_COMMON_SOURCES	:=	plat/common/aarch32/crash_console_helpers.S	\
+PLAT_BL_COMMON_SOURCES	:=	common/desc_image_load.c			\
+				lib/bl_aux_params/bl_aux_params.c		\
+				plat/common/aarch32/crash_console_helpers.S	\
 				plat/common/plat_psci_common.c
 
 PLAT_BL_COMMON_SOURCES	+=	lib/xlat_tables/xlat_tables_common.c		\
diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk
index fa207aa..0da4f2d 100644
--- a/plat/rockchip/rk3328/platform.mk
+++ b/plat/rockchip/rk3328/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -28,7 +28,9 @@
 				plat/common/plat_gicv2.c			\
 				${RK_PLAT}/common/rockchip_gicv2.c
 
-PLAT_BL_COMMON_SOURCES	:=	lib/xlat_tables/aarch64/xlat_tables.c		\
+PLAT_BL_COMMON_SOURCES	:=	common/desc_image_load.c			\
+				lib/bl_aux_params/bl_aux_params.c		\
+				lib/xlat_tables/aarch64/xlat_tables.c		\
 				lib/xlat_tables/xlat_tables_common.c		\
 				plat/common/aarch64/crash_console_helpers.S	\
 				plat/common/plat_psci_common.c
diff --git a/plat/rockchip/rk3368/platform.mk b/plat/rockchip/rk3368/platform.mk
index f8878f1..cb0cb89 100644
--- a/plat/rockchip/rk3368/platform.mk
+++ b/plat/rockchip/rk3368/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -26,7 +26,9 @@
 				plat/common/plat_gicv2.c			\
 				${RK_PLAT}/common/rockchip_gicv2.c
 
-PLAT_BL_COMMON_SOURCES	:=	lib/xlat_tables/xlat_tables_common.c		\
+PLAT_BL_COMMON_SOURCES	:=	common/desc_image_load.c			\
+				lib/bl_aux_params/bl_aux_params.c		\
+				lib/xlat_tables/xlat_tables_common.c		\
 				lib/xlat_tables/aarch64/xlat_tables.c		\
 				plat/common/aarch64/crash_console_helpers.S	\
 				plat/common/plat_psci_common.c
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index 42589b9..a6b5973 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -890,7 +890,7 @@
 
 static void suspend_apio(void)
 {
-	struct apio_info *suspend_apio;
+	struct bl_aux_rk_apio_info *suspend_apio;
 	int i;
 
 	suspend_apio = plat_get_rockchip_suspend_apio();
@@ -1010,7 +1010,7 @@
 
 static void resume_apio(void)
 {
-	struct apio_info *suspend_apio;
+	struct bl_aux_rk_apio_info *suspend_apio;
 	int i;
 
 	suspend_apio = plat_get_rockchip_suspend_apio();
@@ -1038,7 +1038,7 @@
 
 static void suspend_gpio(void)
 {
-	struct gpio_info *suspend_gpio;
+	struct bl_aux_gpio_info *suspend_gpio;
 	uint32_t count;
 	int i;
 
@@ -1053,7 +1053,7 @@
 
 static void resume_gpio(void)
 {
-	struct gpio_info *suspend_gpio;
+	struct bl_aux_gpio_info *suspend_gpio;
 	uint32_t count;
 	int i;
 
@@ -1491,7 +1491,7 @@
 
 void __dead2 rockchip_soc_soft_reset(void)
 {
-	struct gpio_info *rst_gpio;
+	struct bl_aux_gpio_info *rst_gpio;
 
 	rst_gpio = plat_get_rockchip_gpio_reset();
 
@@ -1508,7 +1508,7 @@
 
 void __dead2 rockchip_soc_system_off(void)
 {
-	struct gpio_info *poweroff_gpio;
+	struct bl_aux_gpio_info *poweroff_gpio;
 
 	poweroff_gpio = plat_get_rockchip_gpio_poweroff();
 
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.h b/plat/rockchip/rk3399/drivers/pmu/pmu.h
index e1ba410..74db82f 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.h
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk
index 1d81d7e..cfc48e8 100644
--- a/plat/rockchip/rk3399/platform.mk
+++ b/plat/rockchip/rk3399/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -32,7 +32,9 @@
 				plat/common/plat_gicv3.c		\
 				${RK_PLAT}/common/rockchip_gicv3.c
 
-PLAT_BL_COMMON_SOURCES	:=	lib/xlat_tables/xlat_tables_common.c	\
+PLAT_BL_COMMON_SOURCES	:=	common/desc_image_load.c			\
+				lib/bl_aux_params/bl_aux_params.c		\
+				lib/xlat_tables/xlat_tables_common.c	\
 				lib/xlat_tables/aarch64/xlat_tables.c	\
 				plat/common/aarch64/crash_console_helpers.S \
 				plat/common/plat_psci_common.c