diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S
index 19a0ac2..ed7c27a 100644
--- a/bl1/aarch64/bl1_exceptions.S
+++ b/bl1/aarch64/bl1_exceptions.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -224,6 +224,14 @@
 	bl	save_gp_registers
 
 	/* -----------------------------------------------------
+	 * If Secure Cycle Counter is not disabled in MDCR_EL3
+	 * when ARMv8.5-PMU is implemented, save PMCR_EL0 and
+	 * disable all event counters and cycle counter.
+	 * -----------------------------------------------------
+	 */
+	bl	save_pmcr_disable_pmu
+
+	/* -----------------------------------------------------
 	 * Populate the parameters for the SMC handler. We
 	 * already have x0-x4 in place. x5 will point to a
 	 * cookie (not used now). x6 will point to the context
diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S
index 40c3191..8dca10c 100644
--- a/bl31/aarch64/ea_delegate.S
+++ b/bl31/aarch64/ea_delegate.S
@@ -68,6 +68,13 @@
 	/* Save GP registers */
 	bl	save_gp_registers
 
+	/*
+	 * If Secure Cycle Counter is not disabled in MDCR_EL3
+	 * when ARMv8.5-PMU is implemented, save PMCR_EL0 and
+	 * disable all event counters and cycle counter.
+	 */
+	bl	save_pmcr_disable_pmu
+
 	/* Save ARMv8.3-PAuth registers and load firmware key */
 #if CTX_INCLUDE_PAUTH_REGS
 	bl	pauth_context_save
@@ -106,6 +113,13 @@
 	/* Save GP registers */
 	bl	save_gp_registers
 
+	/*
+	 * If Secure Cycle Counter is not disabled in MDCR_EL3
+	 * when ARMv8.5-PMU is implemented, save PMCR_EL0 and
+	 * disable all event counters and cycle counter.
+	 */
+	bl	save_pmcr_disable_pmu
+
 	/* Save ARMv8.3-PAuth registers and load firmware key */
 #if CTX_INCLUDE_PAUTH_REGS
 	bl	pauth_context_save
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 6ffd995..fd7656e2 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -67,6 +67,14 @@
 
 	/* Save GP registers and restore them afterwards */
 	bl	save_gp_registers
+
+	/*
+	 * If Secure Cycle Counter is not disabled in MDCR_EL3
+	 * when ARMv8.5-PMU is implemented, save PMCR_EL0 and
+	 * disable all event counters and cycle counter.
+	 */
+	bl	save_pmcr_disable_pmu
+
 	bl	handle_lower_el_ea_esb
 	bl	restore_gp_registers
 
@@ -123,6 +131,13 @@
 
 	bl	save_gp_registers
 
+	/*
+	 * If Secure Cycle Counter is not disabled in MDCR_EL3
+	 * when ARMv8.5-PMU is implemented, save PMCR_EL0 and
+	 * disable all event counters and cycle counter.
+	 */
+	bl	save_pmcr_disable_pmu
+
 	/* Save ARMv8.3-PAuth registers and load firmware key */
 #if CTX_INCLUDE_PAUTH_REGS
 	bl	pauth_context_save
@@ -335,6 +350,13 @@
 	/* Save general purpose registers */
 	bl	save_gp_registers
 
+	/*
+	 * If Secure Cycle Counter is not disabled in MDCR_EL3
+	 * when ARMv8.5-PMU is implemented, save PMCR_EL0 and
+	 * disable all event counters and cycle counter.
+	 */
+	bl	save_pmcr_disable_pmu
+
 	/* Save ARMv8.3-PAuth registers and load firmware key */
 #if CTX_INCLUDE_PAUTH_REGS
 	bl	pauth_context_save
diff --git a/drivers/console/multi_console.c b/drivers/console/multi_console.c
index d9eba7f..215f495 100644
--- a/drivers/console/multi_console.c
+++ b/drivers/console/multi_console.c
@@ -70,6 +70,20 @@
 	console->flags = (console->flags & ~CONSOLE_FLAG_SCOPE_MASK) | scope;
 }
 
+static int do_putc(int c, console_t *console)
+{
+	int ret;
+
+	if ((c == '\n') &&
+	    ((console->flags & CONSOLE_FLAG_TRANSLATE_CRLF) != 0)) {
+		ret = console->putc('\r', console);
+		if (ret < 0)
+			return ret;
+	}
+
+	return console->putc(c, console);
+}
+
 int console_putc(int c)
 {
 	int err = ERROR_NO_VALID_CONSOLE;
@@ -77,7 +91,7 @@
 
 	for (console = console_list; console != NULL; console = console->next)
 		if ((console->flags & console_state) && console->putc) {
-			int ret = console->putc(c, console);
+			int ret = do_putc(c, console);
 			if ((err == ERROR_NO_VALID_CONSOLE) || (ret < err))
 				err = ret;
 		}
diff --git a/drivers/renesas/rcar/emmc/emmc_interrupt.c b/drivers/renesas/rcar/emmc/emmc_interrupt.c
index 37a3cf9..2557280 100644
--- a/drivers/renesas/rcar/emmc/emmc_interrupt.c
+++ b/drivers/renesas/rcar/emmc/emmc_interrupt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights
  * reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -26,17 +26,17 @@
 	uint32_t end_bit;
 
 	prr_data = mmio_read_32((uintptr_t) RCAR_PRR);
-	cut_ver = prr_data & RCAR_CUT_MASK;
-	if ((prr_data & RCAR_PRODUCT_MASK) == RCAR_PRODUCT_H3) {
-		if (cut_ver == RCAR_CUT_VER10) {
+	cut_ver = prr_data & PRR_CUT_MASK;
+	if ((prr_data & PRR_PRODUCT_MASK) == PRR_PRODUCT_H3) {
+		if (cut_ver == PRR_PRODUCT_10) {
 			end_bit = BIT17;
-		} else if (cut_ver == RCAR_CUT_VER11) {
+		} else if (cut_ver == PRR_PRODUCT_11) {
 			end_bit = BIT17;
 		} else {
 			end_bit = BIT20;
 		}
-	} else if ((prr_data & RCAR_PRODUCT_MASK) == RCAR_PRODUCT_M3) {
-		if (cut_ver == RCAR_CUT_VER10) {
+	} else if ((prr_data & PRR_PRODUCT_MASK) == PRR_PRODUCT_M3) {
+		if (cut_ver == PRR_PRODUCT_10) {
 			end_bit = BIT17;
 		} else {
 			end_bit = BIT20;
diff --git a/drivers/renesas/rcar/emmc/emmc_mount.c b/drivers/renesas/rcar/emmc/emmc_mount.c
index dd57b0c..df8203e 100644
--- a/drivers/renesas/rcar/emmc/emmc_mount.c
+++ b/drivers/renesas/rcar/emmc/emmc_mount.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -29,14 +29,14 @@
 {
 	uint32_t reg;
 
-	reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
-	if (reg == RCAR_PRODUCT_M3_CUT10) {
+	reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
+	if (reg == PRR_PRODUCT_M3_CUT10) {
 		mmc_drv_obj.boot_partition_en =
 		    (EMMC_PARTITION_ID) ((mmc_drv_obj.ext_csd_data[179] &
 					  EMMC_BOOT_PARTITION_EN_MASK) >>
 					 EMMC_BOOT_PARTITION_EN_SHIFT);
-	} else if ((reg == RCAR_PRODUCT_H3_CUT20)
-		   || (reg == RCAR_PRODUCT_M3_CUT11)) {
+	} else if ((reg == PRR_PRODUCT_H3_CUT20)
+		   || (reg == PRR_PRODUCT_M3_CUT11)) {
 		mmc_drv_obj.boot_partition_en = mmc_drv_obj.partition_access;
 	} else {
 		if ((mmio_read_32(MFISBTSTSR) & MFISBTSTSR_BOOT_PARTITION) !=
@@ -460,8 +460,8 @@
 	uint32_t reg;
 	EMMC_ERROR_CODE result;
 
-	reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
-	if ((reg == RCAR_PRODUCT_H3_CUT20) || (reg == RCAR_PRODUCT_M3_CUT11)) {
+	reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
+	if ((reg == PRR_PRODUCT_H3_CUT20) || (reg == PRR_PRODUCT_M3_CUT11)) {
 		SETR_32(SD_OPTION, 0x000060EEU);	/* 8 bits width */
 		/* CMD8 (EXT_CSD) */
 		emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000U,
diff --git a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c b/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
index 39b9bb4..28b56c1 100644
--- a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
+++ b/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -189,8 +189,8 @@
 	mode = mmio_read_8(IIC_DVFS_REG_ICCR) | IIC_DVFS_BIT_ICCR_ENABLE;
 	mmio_write_8(IIC_DVFS_REG_ICCR, mode);
 
-	lsi_product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
-	if (lsi_product == RCAR_PRODUCT_E3)
+	lsi_product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
+	if (lsi_product == PRR_PRODUCT_E3)
 		goto start;
 
 	reg = mmio_read_32(RCAR_MODEMR) & CHECK_MD13_MD14;
diff --git a/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c b/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
index 0aa3bff..7684c62 100644
--- a/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
+++ b/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
@@ -615,8 +615,8 @@
 	uint32_t reg;
 
 	reg = mmio_read_32(RCAR_PRR);
-	reg &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
-	if (reg == (RCAR_PRODUCT_M3_CUT10)) {
+	reg &= (PRR_PRODUCT_MASK | PRR_CUT_MASK);
+	if (reg == (PRR_PRODUCT_M3_CUT10)) {
 		/* Enable clock supply to RTDMAC. */
 		mstpcr_write(CPG_SCMSTPCR0, CPG_MSTPSR0, SCMSTPCR0_RTDMAC);
 
@@ -654,14 +654,14 @@
 	uint32_t prr;
 
 	prr = mmio_read_32(RCAR_PRR);
-	prr &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+	prr &= (PRR_PRODUCT_MASK | PRR_CUT_MASK);
 
 	mmio_write_32(PFC_PMMR, ~data);
-	if (prr == (RCAR_PRODUCT_M3_CUT10)) {
+	if (prr == (PRR_PRODUCT_M3_CUT10)) {
 		mmio_write_16(SCIF3_SCFCR, SCFCR_DATA);	/* Dummy write */
 	}
 	mmio_write_32((uintptr_t)addr, data);
-	if (prr == (RCAR_PRODUCT_M3_CUT10)) {
+	if (prr == (PRR_PRODUCT_M3_CUT10)) {
 		mmio_write_16(SCIF3_SCFCR, SCFCR_DATA);	/* Dummy write */
 	}
 }
diff --git a/drivers/renesas/rcar/pfc/pfc_init.c b/drivers/renesas/rcar/pfc/pfc_init.c
index e9455af..8810667 100644
--- a/drivers/renesas/rcar/pfc/pfc_init.c
+++ b/drivers/renesas/rcar/pfc/pfc_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -37,20 +37,6 @@
 #include "D3/pfc_init_d3.h"
 #endif
 
- /* Product Register */
-#define PRR			(0xFFF00044U)
-#define PRR_PRODUCT_MASK	(0x00007F00U)
-#define PRR_CUT_MASK		(0x000000FFU)
-#define PRR_PRODUCT_H3		(0x00004F00U)	/* R-Car H3 */
-#define PRR_PRODUCT_M3		(0x00005200U)	/* R-Car M3 */
-#define PRR_PRODUCT_V3M		(0x00005400U)	/* R-Car V3M */
-#define PRR_PRODUCT_M3N		(0x00005500U)	/* R-Car M3N */
-#define PRR_PRODUCT_E3		(0x00005700U)	/* R-Car E3 */
-#define PRR_PRODUCT_D3		(0x00005800U)	/* R-Car D3 */
-#define PRR_PRODUCT_10		(0x00U)
-#define PRR_PRODUCT_11		(0x01U)
-#define PRR_PRODUCT_20		(0x10U)
-
 #define PRR_PRODUCT_ERR(reg)				\
 	do {						\
 		ERROR("LSI Product ID(PRR=0x%x) PFC initialize not supported.\n", \
@@ -71,8 +57,8 @@
 
 	reg = mmio_read_32(RCAR_PRR);
 #if RCAR_LSI == RCAR_AUTO
-	switch (reg & RCAR_PRODUCT_MASK) {
-	case RCAR_PRODUCT_H3:
+	switch (reg & PRR_PRODUCT_MASK) {
+	case PRR_PRODUCT_H3:
 		switch (reg & PRR_CUT_MASK) {
 		case PRR_PRODUCT_10:	/* H3 Ver.1.0 */
 			pfc_init_h3_v1();
@@ -85,13 +71,13 @@
 			break;
 		}
 		break;
-	case RCAR_PRODUCT_M3:
+	case PRR_PRODUCT_M3:
 		pfc_init_m3();
 		break;
-	case RCAR_PRODUCT_M3N:
+	case PRR_PRODUCT_M3N:
 		pfc_init_m3n();
 		break;
-	case RCAR_PRODUCT_V3M:
+	case PRR_PRODUCT_V3M:
 		pfc_init_v3m();
 		break;
 	default:
diff --git a/drivers/renesas/rcar/pfc/pfc_regs.h b/drivers/renesas/rcar/pfc/pfc_regs.h
index e7dd543..4187733 100644
--- a/drivers/renesas/rcar/pfc/pfc_regs.h
+++ b/drivers/renesas/rcar/pfc/pfc_regs.h
@@ -115,7 +115,6 @@
 #define GPIO_IOINTSEL6		(GPIO_BASE + 0x5400U)
 #define GPIO_INOUTSEL6		(GPIO_BASE + 0x5404U)
 #define GPIO_OUTDT6		(GPIO_BASE + 0x5408U)
-#define GPIO_INDT6		(GPIO_BASE + 0x540CU)
 #define GPIO_INTDT6		(GPIO_BASE + 0x5410U)
 #define GPIO_INTCLR6		(GPIO_BASE + 0x5414U)
 #define GPIO_INTMSK6		(GPIO_BASE + 0x5418U)
diff --git a/drivers/renesas/rcar/pwrc/pwrc.c b/drivers/renesas/rcar/pwrc/pwrc.c
index 32e04a7..2ce6b61 100644
--- a/drivers/renesas/rcar/pwrc/pwrc.c
+++ b/drivers/renesas/rcar/pwrc/pwrc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -314,16 +314,16 @@
 	rcar_lock_get();
 
 	reg = mmio_read_32(RCAR_PRR);
-	product = reg & RCAR_PRODUCT_MASK;
-	cut = reg & RCAR_CUT_MASK;
+	product = reg & PRR_PRODUCT_MASK;
+	cut = reg & PRR_CUT_MASK;
 
 	c = rcar_pwrc_get_mpidr_cluster(mpidr);
 	dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR;
 
-	if (RCAR_PRODUCT_M3 == product && cut < RCAR_CUT_VER30)
+	if (PRR_PRODUCT_M3 == product && cut < PRR_PRODUCT_30)
 		goto done;
 
-	if (RCAR_PRODUCT_H3 == product && cut <= RCAR_CUT_VER20)
+	if (PRR_PRODUCT_H3 == product && cut <= PRR_PRODUCT_20)
 		goto done;
 
 	/* all of the CPUs in the cluster is in the CoreStandby mode */
@@ -424,13 +424,13 @@
 	uint32_t reg = mmio_read_32(RCAR_PRR);
 	uint32_t cut, product;
 
-	product = reg & RCAR_PRODUCT_MASK;
-	cut = reg & RCAR_CUT_MASK;
+	product = reg & PRR_PRODUCT_MASK;
+	cut = reg & PRR_CUT_MASK;
 
-	if (product == RCAR_PRODUCT_M3 && cut < RCAR_CUT_VER30)
+	if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30)
 		goto self_refresh;
 
-	if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
+	if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
 		goto self_refresh;
 
 	mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
@@ -445,16 +445,16 @@
 	/* Set the Self-Refresh mode */
 	mmio_write_32(DBSC4_REG_DBACEN, 0);
 
-	if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
+	if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
 		rcar_micro_delay(100);
-	else if (product == RCAR_PRODUCT_H3) {
+	else if (product == PRR_PRODUCT_H3) {
 		mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
 		DBCAM_FLUSH(0);
 		DBCAM_FLUSH(1);
 		DBCAM_FLUSH(2);
 		DBCAM_FLUSH(3);
 		mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
-	} else if (product == RCAR_PRODUCT_M3) {
+	} else if (product == PRR_PRODUCT_M3) {
 		mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
 		DBCAM_FLUSH(0);
 		DBCAM_FLUSH(1);
@@ -499,10 +499,10 @@
 	mmio_write_32(DBSC4_REG_DBRFEN, 0U);
 	rcar_micro_delay(1U);
 
-	if (product == RCAR_PRODUCT_M3 && cut < RCAR_CUT_VER30)
+	if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30)
 		return;
 
-	if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
+	if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
 		return;
 
 	mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE);
@@ -648,9 +648,9 @@
 	uint32_t reg, product;
 
 	reg = mmio_read_32(RCAR_PRR);
-	product = reg & RCAR_PRODUCT_MASK;
+	product = reg & PRR_PRODUCT_MASK;
 
-	if (product != RCAR_PRODUCT_E3)
+	if (product != PRR_PRODUCT_E3)
 		rcar_pwrc_set_self_refresh();
 	else
 		rcar_pwrc_set_self_refresh_e3();
diff --git a/drivers/renesas/rcar/qos/qos_init.c b/drivers/renesas/rcar/qos/qos_init.c
index 884e031..d0f1730 100644
--- a/drivers/renesas/rcar/qos/qos_init.c
+++ b/drivers/renesas/rcar/qos/qos_init.c
@@ -12,6 +12,7 @@
 #include "qos_init.h"
 #include "qos_common.h"
 #include "qos_reg.h"
+#include "rcar_def.h"
 #if RCAR_LSI == RCAR_AUTO
 #include "H3/qos_init_h3_v10.h"
 #include "H3/qos_init_h3_v11.h"
@@ -50,22 +51,6 @@
 #include "D3/qos_init_d3.h"
 #endif
 
- /* Product Register */
-#define PRR			0xFFF00044U
-#define PRR_PRODUCT_MASK	0x00007F00U
-#define PRR_CUT_MASK		0x000000FFU
-#define PRR_PRODUCT_H3		0x00004F00U	/* R-Car H3 */
-#define PRR_PRODUCT_M3		0x00005200U	/* R-Car M3 */
-#define PRR_PRODUCT_V3M		0x00005400U	/* R-Car V3M */
-#define PRR_PRODUCT_M3N		0x00005500U	/* R-Car M3N */
-#define PRR_PRODUCT_E3		0x00005700U	/* R-Car E3 */
-#define PRR_PRODUCT_D3		0x00005800U	/* R-Car D3 */
-#define PRR_PRODUCT_10		0x00U
-#define PRR_PRODUCT_11		0x01U
-#define PRR_PRODUCT_20		0x10U
-#define PRR_PRODUCT_21		0x11U
-#define PRR_PRODUCT_30		0x20U
-
 #if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RCAR_V3M)
 
 #define DRAM_CH_CNT			0x04
diff --git a/drivers/renesas/rcar/rom/rom_api.c b/drivers/renesas/rcar/rom/rom_api.c
index c9f8f5f..fda2815 100644
--- a/drivers/renesas/rcar/rom/rom_api.c
+++ b/drivers/renesas/rcar/rom/rom_api.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -30,30 +30,30 @@
 	uint32_t cut_ver;
 	uint32_t index;
 
-	product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
-	cut_ver = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK;
+	product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
+	cut_ver = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
 
 	switch (product) {
-	case RCAR_PRODUCT_H3:
-		if (cut_ver == RCAR_CUT_VER10)
+	case PRR_PRODUCT_H3:
+		if (cut_ver == PRR_PRODUCT_10)
 			index = OLD_API_TABLE1;
-		else if (cut_ver == RCAR_CUT_VER11)
+		else if (cut_ver == PRR_PRODUCT_11)
 			index = OLD_API_TABLE1;
-		else if (cut_ver == RCAR_CUT_VER20)
+		else if (cut_ver == PRR_PRODUCT_20)
 			index = OLD_API_TABLE2;
 		else
 			/* Later than H3 Ver.2.0 */
 			index = NEW_API_TABLE;
 		break;
-	case RCAR_PRODUCT_M3:
-		if (cut_ver == RCAR_CUT_VER10)
+	case PRR_PRODUCT_M3:
+		if (cut_ver == PRR_PRODUCT_10)
 			index = OLD_API_TABLE3;
 		else
 			/* M3 Ver.1.1 or later */
 			index = NEW_API_TABLE;
 		break;
-	case RCAR_PRODUCT_V3M:
-		if (cut_ver == RCAR_CUT_VER10)
+	case PRR_PRODUCT_V3M:
+		if (cut_ver == PRR_PRODUCT_10)
 			/* V3M WS1.0 */
 			index = NEW_API_TABLE2;
 		else
diff --git a/drivers/renesas/rcar/rpc/rpc_driver.c b/drivers/renesas/rcar/rpc/rpc_driver.c
index 5c11b62..63de5b8 100644
--- a/drivers/renesas/rcar/rpc/rpc_driver.c
+++ b/drivers/renesas/rcar/rpc/rpc_driver.c
@@ -34,10 +34,10 @@
 	if (mmio_read_32(RPC_CMNCR) & RPC_CMNCR_MD_BIT)
 		mmio_clrbits_32(RPC_CMNCR, RPC_CMNCR_MD_BIT);
 
-	product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
-	cut = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK;
+	product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
+	cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
 
-	if ((product ==  RCAR_PRODUCT_M3) && (cut < RCAR_CUT_VER30))
+	if ((product ==  PRR_PRODUCT_M3) && (cut < PRR_PRODUCT_30))
 		phy_strtim = RPC_PHYCNT_STRTIM_M3V1;
 	else
 		phy_strtim = RPC_PHYCNT_STRTIM;
diff --git a/drivers/renesas/rcar/watchdog/swdt.c b/drivers/renesas/rcar/watchdog/swdt.c
index 8b2943c..111e651 100644
--- a/drivers/renesas/rcar/watchdog/swdt.c
+++ b/drivers/renesas/rcar/watchdog/swdt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -82,7 +82,7 @@
 	uint32_t reg, val, product_cut, chk_data;
 
 	reg = mmio_read_32(RCAR_PRR);
-	product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+	product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
 
 	reg = mmio_read_32(RCAR_MODEMR);
 	chk_data = reg & CHECK_MD13_MD14;
@@ -108,7 +108,7 @@
 		val |= WTCNT_COUNT_8p22k;
 		break;
 	case MD14_MD13_TYPE_3:
-		val |= product_cut == (RCAR_PRODUCT_H3 | RCAR_CUT_VER10) ?
+		val |= product_cut == (PRR_PRODUCT_H3 | PRR_PRODUCT_10) ?
 		    WTCNT_COUNT_8p13k_H3VER10 : WTCNT_COUNT_8p13k;
 		break;
 	default:
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
index 89d666c..2cce653 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
@@ -20,6 +20,7 @@
 #include "boot_init_dram.h"
 #include "dram_sub_func.h"
 #include "micro_delay.h"
+#include "rcar_def.h"
 
 #define DDR_BACKUPMODE
 #define FATAL_MSG(x) NOTICE(x)
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
index 5d1b078..aaa5f00 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
@@ -1622,7 +1622,6 @@
 #define PFC_PUD5	0xE6060454U
 #define PFC_PUD6	0xE6060458U
 #define GPIO_INDT5	0xE605500CU
-#define GPIO_INDT6	0xE605540CU
 #define GPIO_GPSR6 	0xE6060118U
 
 #if (RCAR_GEN3_ULCB == 0)
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
index a1cbfbf..abddf0c 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
@@ -55,19 +55,6 @@
 
 #define LIFEC_CHIPID(x)		(0xE6110040U + 0x04U * (x))
 
-/* Product Register */
-#define PRR			(0xFFF00044U)
-#define PRR_PRODUCT_MASK	(0x00007F00U)
-#define PRR_CUT_MASK		(0x000000FFU)
-#define PRR_PRODUCT_H3		(0x00004F00U)	/* R-Car H3   */
-#define PRR_PRODUCT_M3		(0x00005200U)	/* R-Car M3-W */
-#define PRR_PRODUCT_M3N		(0x00005500U)	/* R-Car M3-N */
-#define PRR_PRODUCT_V3H		(0x00005600U)	/* R-Car V3H  */
-#define PRR_PRODUCT_10		(0x00U)	/*   Ver.1.0  */
-#define PRR_PRODUCT_11		(0x01U)	/*   Ver.1.1  */
-#define PRR_PRODUCT_20		(0x10U)	/*   Ver.2.0  */
-#define PRR_PRODUCT_30		(0x20U)	/*   Ver.3.0  */
-
 /* DBSC registers */
 #define DBSC_DBSYSCONF1		0xE6790004U
 #define DBSC_DBPHYCONF0		0xE6790010U
diff --git a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c b/drivers/staging/renesas/rcar/ddr/dram_sub_func.c
index 6739b0d..c6ab44a 100644
--- a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c
+++ b/drivers/staging/renesas/rcar/ddr/dram_sub_func.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,15 +8,7 @@
 #include <lib/mmio.h>
 
 #include "dram_sub_func.h"
-
-#define PRR				(0xFFF00044U)
-#define PRR_PRODUCT_MASK		(0x00007F00U)
-#define PRR_CUT_MASK			(0x000000FFU)
-#define PRR_PRODUCT_H3			(0x00004F00U)	/* R-Car H3  */
-#define PRR_PRODUCT_M3			(0x00005200U)	/* R-Car M3  */
-#define PRR_PRODUCT_M3N			(0x00005500U)	/* R-Car M3N */
-#define PRR_PRODUCT_E3			(0x00005700U)	/* R-Car E3  */
-#define PRR_PRODUCT_V3H			(0x00005600U)	/* R-Car V3H */
+#include "rcar_def.h"
 
 #if RCAR_SYSTEM_SUSPEND
 /* Local defines */
@@ -32,11 +24,9 @@
 #endif
 
 #define	GPIO_OUTDT1			(0xE6051008U)
-#define GPIO_INDT1			(0xE605100CU)
 #define GPIO_OUTDT3			(0xE6053008U)
 #define GPIO_INDT3			(0xE605300CU)
 #define GPIO_OUTDT6			(0xE6055408U)
-#define GPIO_INDT6			(0xE605540CU)
 
 #if DRAM_BACKUP_GPIO_USE == 1
 #define GPIO_BKUP_REQB_SHIFT_SALVATOR	(9U)	/* GP1_9 (BKUP_REQB) */
diff --git a/fdts/corstone700.dts b/fdts/corstone700.dts
new file mode 100644
index 0000000..16cf412
--- /dev/null
+++ b/fdts/corstone700.dts
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+	model = "corstone700";
+	compatible = "arm,Corstone-700";
+	interrupt-parent = <&gic>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		bootargs = "console=ttyAMA0 root=/dev/vda2 rw loglevel=9";
+		linux,initrd-start = <0x02a00000>;
+		linux,initrd-end = <0x04000000>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0>;
+			next-level-cache = <&L2_0>;
+		};
+
+	};
+
+	memory@2000000 {
+		device_type = "memory";
+		reg = <0x02000000 0x02000000>;
+	};
+
+	gic: interrupt-controller@1c000000 {
+		compatible = "arm,gic-400";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg =	<0x1c010000 0x1000>,
+			<0x1c02f000 0x2000>,
+			<0x1c04f000 0x1000>,
+			<0x1c06f000 0x2000>;
+		interrupts = <1 9 0xf08>;
+	};
+
+	L2_0: l2-cache0 {
+		compatible = "cache";
+	};
+
+	refclk100mhz: refclk100mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "apb_pclk";
+	};
+
+	smbclk: refclk24mhzx2 {
+		/* Reference 24MHz clock x 2 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <48000000>;
+		clock-output-names = "smclk";
+	};
+
+
+	serial0: uart@1a510000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x1a510000 0x1000>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 19 4>;
+		clocks = <&refclk100mhz>, <&smbclk>;
+		clock-names = "apb_pclk", "smclk";
+	};
+
+	serial1: uart@1a520000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x1a520000 0x1000>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 20 4>;
+		clocks = <&refclk100mhz>, <&smbclk>;
+		clock-names = "apb_pclk", "smclk";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts =	<1 13 0xf08>,
+				<1 14 0xf08>,
+				<1 11 0xf08>,
+				<1 10 0xf08>;
+		};
+
+	mbox_es0mhu0: mhu@1b000000 {
+		compatible = "arm,mhuv2","arm,primecell";
+		reg = <0x1b000000 0x1000>,
+		      <0x1b010000 0x1000>;
+		clocks = <&refclk100mhz>;
+		clock-names = "apb_pclk";
+		interrupts = <0 12 4>;
+		interrupt-names = "mhu_rx";
+		#mbox-cells = <1>;
+		mbox-name = "arm-es0-mhu0";
+	};
+
+	mbox_es0mhu1: mhu@1b020000 {
+		compatible = "arm,mhuv2","arm,primecell";
+		reg = <0x1b020000 0x1000>,
+		      <0x1b030000 0x1000>;
+		clocks = <&refclk100mhz>;
+		clock-names = "apb_pclk";
+		interrupts = <0 47 4>;
+		interrupt-names = "mhu_rx";
+		#mbox-cells = <1>;
+		mbox-name = "arm-es0-mhu1";
+	};
+
+	mbox_semhu1: mhu@1b820000 {
+		compatible = "arm,mhuv2","arm,primecell";
+		reg = <0x1b820000 0x1000>,
+		      <0x1b830000 0x1000>;
+		clocks = <&refclk100mhz>;
+		clock-names = "apb_pclk";
+		interrupts = <0 45 4>;
+		interrupt-names = "mhu_rx";
+		#mbox-cells = <1>;
+		mbox-name = "arm-se-mhu1";
+	};
+
+	client {
+		compatible = "arm,client";
+		mboxes = <&mbox_es0mhu0 0>, <&mbox_es0mhu1 0>, <&mbox_semhu1 0>;
+		mbox-names = "es0mhu0", "es0mhu1", "semhu1";
+	};
+
+	extsys0: extsys@1A010310 {
+		compatible = "arm,extsys_ctrl";
+		reg = <0x1A010310 0x4>,
+		      <0x1A010314 0x4>;
+		reg-names = "rstreg", "streg";
+	};
+
+};
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index fa857fb..5f84ece 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -112,6 +112,7 @@
 /* CLIDR definitions */
 #define LOUIS_SHIFT		U(21)
 #define LOC_SHIFT		U(24)
+#define CTYPE_SHIFT(n)		U(3 * (n - 1))
 #define CLIDR_FIELD_WIDTH	U(3)
 
 /* CSSELR definitions */
@@ -132,12 +133,13 @@
 #define ID_AA64PFR0_EL2_SHIFT	U(8)
 #define ID_AA64PFR0_EL3_SHIFT	U(12)
 #define ID_AA64PFR0_AMU_SHIFT	U(44)
-#define ID_AA64PFR0_AMU_LENGTH	U(4)
 #define ID_AA64PFR0_AMU_MASK	ULL(0xf)
 #define ID_AA64PFR0_ELX_MASK	ULL(0xf)
+#define ID_AA64PFR0_GIC_SHIFT	U(24)
+#define ID_AA64PFR0_GIC_WIDTH	U(4)
+#define ID_AA64PFR0_GIC_MASK	ULL(0xf)
 #define ID_AA64PFR0_SVE_SHIFT	U(32)
 #define ID_AA64PFR0_SVE_MASK	ULL(0xf)
-#define ID_AA64PFR0_SVE_LENGTH	U(4)
 #define ID_AA64PFR0_MPAM_SHIFT	U(40)
 #define ID_AA64PFR0_MPAM_MASK	ULL(0xf)
 #define ID_AA64PFR0_DIT_SHIFT	U(48)
@@ -148,18 +150,14 @@
 #define ID_AA64PFR0_CSV2_MASK	ULL(0xf)
 #define ID_AA64PFR0_CSV2_LENGTH	U(4)
 
-/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
-#define ID_AA64DFR0_PMS_SHIFT	U(32)
-#define ID_AA64DFR0_PMS_LENGTH	U(4)
-#define ID_AA64DFR0_PMS_MASK	ULL(0xf)
-
+/* Exception level handling */
 #define EL_IMPL_NONE		ULL(0)
 #define EL_IMPL_A64ONLY		ULL(1)
 #define EL_IMPL_A64_A32		ULL(2)
 
-#define ID_AA64PFR0_GIC_SHIFT	U(24)
-#define ID_AA64PFR0_GIC_WIDTH	U(4)
-#define ID_AA64PFR0_GIC_MASK	ULL(0xf)
+/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
+#define ID_AA64DFR0_PMS_SHIFT	U(32)
+#define ID_AA64DFR0_PMS_MASK	ULL(0xf)
 
 /* ID_AA64ISAR1_EL1 definitions */
 #define ID_AA64ISAR1_EL1	S3_0_C0_C6_1
@@ -304,20 +302,25 @@
 #define SCR_RESET_VAL		SCR_RES1_BITS
 
 /* MDCR_EL3 definitions */
+#define MDCR_SCCD_BIT		(ULL(1) << 23)
+#define MDCR_SPME_BIT		(ULL(1) << 17)
+#define MDCR_SDD_BIT		(ULL(1) << 16)
 #define MDCR_SPD32(x)		((x) << 14)
 #define MDCR_SPD32_LEGACY	ULL(0x0)
 #define MDCR_SPD32_DISABLE	ULL(0x2)
 #define MDCR_SPD32_ENABLE	ULL(0x3)
-#define MDCR_SDD_BIT		(ULL(1) << 16)
 #define MDCR_NSPB(x)		((x) << 12)
 #define MDCR_NSPB_EL1		ULL(0x3)
 #define MDCR_TDOSA_BIT		(ULL(1) << 10)
 #define MDCR_TDA_BIT		(ULL(1) << 9)
 #define MDCR_TPM_BIT		(ULL(1) << 6)
-#define MDCR_SCCD_BIT		(ULL(1) << 23)
 #define MDCR_EL3_RESET_VAL	ULL(0x0)
 
 /* MDCR_EL2 definitions */
+#define MDCR_EL2_HLP		(U(1) << 26)
+#define MDCR_EL2_HCCD		(U(1) << 23)
+#define MDCR_EL2_TTRF		(U(1) << 19)
+#define MDCR_EL2_HPMD		(U(1) << 17)
 #define MDCR_EL2_TPMS		(U(1) << 14)
 #define MDCR_EL2_E2PB(x)	((x) << 12)
 #define MDCR_EL2_E2PB_EL1	U(0x3)
@@ -677,10 +680,14 @@
 #define PMCR_EL0_N_SHIFT	U(11)
 #define PMCR_EL0_N_MASK		U(0x1f)
 #define PMCR_EL0_N_BITS		(PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
+#define PMCR_EL0_LP_BIT		(U(1) << 7)
 #define PMCR_EL0_LC_BIT		(U(1) << 6)
 #define PMCR_EL0_DP_BIT		(U(1) << 5)
 #define PMCR_EL0_X_BIT		(U(1) << 4)
 #define PMCR_EL0_D_BIT		(U(1) << 3)
+#define PMCR_EL0_C_BIT		(U(1) << 2)
+#define PMCR_EL0_P_BIT		(U(1) << 1)
+#define PMCR_EL0_E_BIT		(U(1) << 0)
 
 /*******************************************************************************
  * Definitions for system register interface to SVE
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 22b32b4..a36b7da 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -116,12 +116,42 @@
 	 * ---------------------------------------------------------------------
 	 */
 	mov_imm	x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \
-		      MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) \
-		    & ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT))
+		      MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) & \
+		    ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT))
 
 	msr	mdcr_el3, x0
 
 	/* ---------------------------------------------------------------------
+	 * Initialise PMCR_EL0 setting all fields rather than relying
+	 * on hw. Some fields are architecturally UNKNOWN on reset.
+	 *
+	 * PMCR_EL0.LP: Set to one so that event counter overflow, that
+	 *  is recorded in PMOVSCLR_EL0[0-30], occurs on the increment
+	 *  that changes PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU
+	 *  is implemented. This bit is RES0 in versions of the architecture
+	 *  earlier than ARMv8.5, setting it to 1 doesn't have any effect
+	 *  on them.
+	 *
+	 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that
+	 *  is recorded in PMOVSCLR_EL0[31], occurs on the increment
+	 *  that changes PMCCNTR_EL0[63] from 1 to 0.
+	 *
+	 * PMCR_EL0.DP: Set to one so that the cycle counter,
+	 *  PMCCNTR_EL0 does not count when event counting is prohibited.
+	 *
+	 * PMCR_EL0.X: Set to zero to disable export of events.
+	 *
+	 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0
+	 *  counts on every clock cycle.
+	 * ---------------------------------------------------------------------
+	 */
+	mov_imm	x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \
+		      PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \
+		    ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT))
+
+	msr	pmcr_el0, x0
+
+	/* ---------------------------------------------------------------------
 	 * Enable External Aborts and SError Interrupts now that the exception
 	 * vectors have been setup.
 	 * ---------------------------------------------------------------------
diff --git a/include/drivers/console.h b/include/drivers/console.h
index cada771..a4859d8 100644
--- a/include/drivers/console.h
+++ b/include/drivers/console.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,7 +21,8 @@
 #define CONSOLE_FLAG_CRASH		(U(1) << 2)
 /* Bits 3 to 7 reserved for additional scopes in future expansion. */
 #define CONSOLE_FLAG_SCOPE_MASK		((U(1) << 8) - 1)
-/* Bits 8 to 31 reserved for non-scope use in future expansion. */
+/* Bits 8 to 31 for non-scope use. */
+#define CONSOLE_FLAG_TRANSLATE_CRLF	(U(1) << 8)
 
 /* Returned by getc callbacks when receive FIFO is empty. */
 #define ERROR_NO_PENDING_CHAR		(-1)
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index a76a59b..64fa8a9 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -59,7 +59,7 @@
 #define CTX_RUNTIME_SP		U(0x10)
 #define CTX_SPSR_EL3		U(0x18)
 #define CTX_ELR_EL3		U(0x20)
-#define CTX_UNUSED		U(0x28)
+#define CTX_PMCR_EL0		U(0x28)
 #define CTX_EL3STATE_END	U(0x30)
 
 /*******************************************************************************
@@ -91,22 +91,21 @@
 #define CTX_AFSR1_EL1		U(0x98)
 #define CTX_CONTEXTIDR_EL1	U(0xa0)
 #define CTX_VBAR_EL1		U(0xa8)
-#define CTX_PMCR_EL0		U(0xb0)
 
 /*
  * If the platform is AArch64-only, there is no need to save and restore these
  * AArch32 registers.
  */
 #if CTX_INCLUDE_AARCH32_REGS
-#define CTX_SPSR_ABT		U(0xc0)  /* Align to the next 16 byte boundary */
-#define CTX_SPSR_UND		U(0xc8)
-#define CTX_SPSR_IRQ		U(0xd0)
-#define CTX_SPSR_FIQ		U(0xd8)
-#define CTX_DACR32_EL2		U(0xe0)
-#define CTX_IFSR32_EL2		U(0xe8)
-#define CTX_AARCH32_END		U(0xf0) /* Align to the next 16 byte boundary */
+#define CTX_SPSR_ABT		U(0xb0)	/* Align to the next 16 byte boundary */
+#define CTX_SPSR_UND		U(0xb8)
+#define CTX_SPSR_IRQ		U(0xc0)
+#define CTX_SPSR_FIQ		U(0xc8)
+#define CTX_DACR32_EL2		U(0xd0)
+#define CTX_IFSR32_EL2		U(0xd8)
+#define CTX_AARCH32_END		U(0xe0) /* Align to the next 16 byte boundary */
 #else
-#define CTX_AARCH32_END		U(0xc0)  /* Align to the next 16 byte boundary */
+#define CTX_AARCH32_END		U(0xb0)	/* Align to the next 16 byte boundary */
 #endif /* CTX_INCLUDE_AARCH32_REGS */
 
 /*
diff --git a/lib/cpus/aarch64/aem_generic.S b/lib/cpus/aarch64/aem_generic.S
index 51b5ce9..6291e43 100644
--- a/lib/cpus/aarch64/aem_generic.S
+++ b/lib/cpus/aarch64/aem_generic.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -18,15 +18,43 @@
 	msr	sctlr_el3, x1
 	isb
 
-	mov	x0, #DCCISW
-
 	/* ---------------------------------------------
-	 * Flush L1 cache to PoU.
+	 * AEM model supports L3 caches in which case L2
+	 * will be private per core caches and flush
+	 * from L1 to L2 is not sufficient.
 	 * ---------------------------------------------
 	 */
-	b	dcsw_op_louis
-endfunc aem_generic_core_pwr_dwn
+	mrs	x1, clidr_el1
 
+	/* ---------------------------------------------
+	 * Check if L3 cache is implemented.
+	 * ---------------------------------------------
+	 */
+	tst	x1, ((1 << CLIDR_FIELD_WIDTH) - 1) << CTYPE_SHIFT(3)
+
+	/* ---------------------------------------------
+	 * There is no L3 cache, flush L1 to L2 only.
+	 * ---------------------------------------------
+	 */
+	mov	x0, #DCCISW
+	b.eq	dcsw_op_level1
+
+	mov	x18, x30
+
+	/* ---------------------------------------------
+	 * Flush L1 cache to L2.
+	 * ---------------------------------------------
+	 */
+	bl	dcsw_op_level1
+	mov	x30, x18
+
+	/* ---------------------------------------------
+	 * Flush L2 cache to L3.
+	 * ---------------------------------------------
+	 */
+	mov	x0, #DCCISW
+	b	dcsw_op_level2
+endfunc aem_generic_core_pwr_dwn
 
 func aem_generic_cluster_pwr_dwn
 	/* ---------------------------------------------
@@ -39,7 +67,7 @@
 	isb
 
 	/* ---------------------------------------------
-	 * Flush L1 and L2 caches to PoC.
+	 * Flush all caches to PoC.
 	 * ---------------------------------------------
 	 */
 	mov	x0, #DCCISW
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index b143a2e..31e7a3a 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -43,6 +43,7 @@
 	msr	CPUPMR_EL3, x0
 	ldr	x0, =0x800200071
 	msr	CPUPCR_EL3, x0
+	isb
 1:
 	ret	x17
 endfunc errata_n1_1043202_wa
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index e6ab19b..53dc02e 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -24,9 +24,45 @@
 	.global	save_gp_registers
 	.global	restore_gp_registers
 	.global	restore_gp_registers_eret
+	.global	save_pmcr_disable_pmu
 	.global	el3_exit
 
 /* -----------------------------------------------------
+ * If ARMv8.5-PMU is implemented, cycle counting is
+ * disabled by seting MDCR_EL3.SCCD to 1.
+ * -----------------------------------------------------
+ */
+func save_pmcr_disable_pmu
+	/* -----------------------------------------------------
+	 * Check if earlier initialization MDCR_EL3.SCCD to 1
+	 * failed, meaning that ARMv8-PMU is not implemented and
+	 * PMCR_EL0 should be saved in non-secure context.
+	 * -----------------------------------------------------
+	 */
+	mrs	x9, mdcr_el3
+	tst	x9, #MDCR_SCCD_BIT
+	bne	1f
+
+	/* Secure Cycle Counter is not disabled */
+	mrs	x9, pmcr_el0
+
+	/* Check caller's security state */
+	mrs	x10, scr_el3
+	tst	x10, #SCR_NS_BIT
+	beq	2f
+
+	/* Save PMCR_EL0 if called from Non-secure state */
+	str	x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
+
+	/* Disable cycle counter when event counting is prohibited */
+2:	orr	x9, x9, #PMCR_EL0_DP_BIT
+	msr	pmcr_el0, x9
+
+	isb
+1:	ret
+endfunc save_pmcr_disable_pmu
+
+/* -----------------------------------------------------
  * The following function strictly follows the AArch64
  * PCS to use x9-x17 (temporary caller-saved registers)
  * to save EL1 system register context. It assumes that
@@ -80,9 +116,6 @@
 	mrs	x9, vbar_el1
 	stp	x17, x9, [x0, #CTX_CONTEXTIDR_EL1]
 
-	mrs	x10, pmcr_el0
-	str	x10, [x0, #CTX_PMCR_EL0]
-
 	/* Save AArch32 system registers if the build has instructed so */
 #if CTX_INCLUDE_AARCH32_REGS
 	mrs	x11, spsr_abt
@@ -169,9 +202,6 @@
 	msr	contextidr_el1, x17
 	msr	vbar_el1, x9
 
-	ldr	x10, [x0, #CTX_PMCR_EL0]
-	msr	pmcr_el0, x10
-
 	/* Restore AArch32 system registers if the build has instructed so */
 #if CTX_INCLUDE_AARCH32_REGS
 	ldp	x11, x12, [x0, #CTX_SPSR_ABT]
@@ -503,6 +533,29 @@
 	msr	spsr_el3, x16
 	msr	elr_el3, x17
 
+	/* -----------------------------------------------------
+	 * Restore PMCR_EL0 when returning to Non-secure state
+	 * if Secure Cycle Counter is not disabled in MDCR_EL3
+	 * when ARMv8.5-PMU is implemented
+	 * -----------------------------------------------------
+	 */
+	tst	x18, #SCR_NS_BIT
+	beq	2f
+
+	/* -----------------------------------------------------
+	 * Back to Non-secure state.
+	 * Check if earlier initialization MDCR_EL3.SCCD to 1
+	 * failed, meaning that ARMv8-PMU is not implemented and
+	 * PMCR_EL0 should be restored from non-secure context.
+	 * -----------------------------------------------------
+	 */
+	mrs	x17, mdcr_el3
+	tst	x17, #MDCR_SCCD_BIT
+	bne	2f
+	ldr	x17, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
+	msr	pmcr_el0, x17
+2:
+
 #if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639
 	/* Restore mitigation state as it was on entry to EL3 */
 	ldr	x17, [sp, #CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_DISABLE]
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 05ba5ed..bd5b3aa 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -66,7 +66,7 @@
 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
 {
 	unsigned int security_state;
-	uint32_t scr_el3, pmcr_el0;
+	uint32_t scr_el3;
 	el3_state_t *state;
 	gp_regs_t *gp_regs;
 	unsigned long sctlr_elx, actlr_elx;
@@ -225,31 +225,10 @@
 	actlr_elx = read_actlr_el1();
 	write_ctx_reg((get_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx));
 
-	if (security_state == SECURE) {
-		/*
-		 * Initialise PMCR_EL0 for secure context only, setting all
-		 * fields rather than relying on hw. Some fields are
-		 * architecturally UNKNOWN on reset.
-		 *
-		 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that
-		 *  is recorded in PMOVSCLR_EL0[31], occurs on the increment
-		 *  that changes PMCCNTR_EL0[63] from 1 to 0.
-		 *
-		 * PMCR_EL0.DP: Set to one so that the cycle counter,
-		 *  PMCCNTR_EL0 does not count when event counting is prohibited.
-		 *
-		 * PMCR_EL0.X: Set to zero to disable export of events.
-		 *
-		 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0
-		 *  counts on every clock cycle.
-		 */
-		pmcr_el0 = ((PMCR_EL0_RESET_VAL | PMCR_EL0_LC_BIT
-				| PMCR_EL0_DP_BIT)
-				& ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT));
-		write_ctx_reg(get_sysregs_ctx(ctx), CTX_PMCR_EL0, pmcr_el0);
-	}
-
-	/* Populate EL3 state so that we've the right context before doing ERET */
+	/*
+	 * Populate EL3 state so that we've the right context
+	 * before doing ERET
+	 */
 	state = get_el3state_ctx(ctx);
 	write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
 	write_ctx_reg(state, CTX_ELR_EL3, ep->pc);
@@ -441,6 +420,29 @@
 			 * relying on hw. Some fields are architecturally
 			 * UNKNOWN on reset.
 			 *
+			 * MDCR_EL2.HLP: Set to one so that event counter
+			 *  overflow, that is recorded in PMOVSCLR_EL0[0-30],
+			 *  occurs on the increment that changes
+			 *  PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is
+			 *  implemented. This bit is RES0 in versions of the
+			 *  architecture earlier than ARMv8.5, setting it to 1
+			 *  doesn't have any effect on them.
+			 *
+			 * MDCR_EL2.TTRF: Set to zero so that access to Trace
+			 *  Filter Control register TRFCR_EL1 at EL1 is not
+			 *  trapped to EL2. This bit is RES0 in versions of
+			 *  the architecture earlier than ARMv8.4.
+			 *
+			 * MDCR_EL2.HPMD: Set to one so that event counting is
+			 *  prohibited at EL2. This bit is RES0 in versions of
+			 *  the architecture earlier than ARMv8.1, setting it
+			 *  to 1 doesn't have any effect on them.
+			 *
+			 * MDCR_EL2.TPMS: Set to zero so that accesses to
+			 *  Statistical Profiling control registers from EL1
+			 *  do not trap to EL2. This bit is RES0 when SPE is
+			 *  not implemented.
+			 *
 			 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and
 			 *  EL1 System register accesses to the Debug ROM
 			 *  registers are not trapped to EL2.
@@ -469,13 +471,15 @@
 			 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the
 			 *  architecturally-defined reset value.
 			 */
-			mdcr_el2 = ((MDCR_EL2_RESET_VAL |
-					((read_pmcr_el0() & PMCR_EL0_N_BITS)
-					>> PMCR_EL0_N_SHIFT)) &
-					~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT
-					| MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT
-					| MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT
-					| MDCR_EL2_TPMCR_BIT));
+			mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP |
+				     MDCR_EL2_HPMD) |
+				   ((read_pmcr_el0() & PMCR_EL0_N_BITS)
+				   >> PMCR_EL0_N_SHIFT)) &
+				   ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS |
+				     MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT |
+				     MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT |
+				     MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT |
+				     MDCR_EL2_TPMCR_BIT);
 
 			write_mdcr_el2(mdcr_el2);
 
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 5d24356..022c877 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -198,21 +198,17 @@
 /******************************************************************************
  * Helper function to update the requested local power state array. This array
  * does not store the requested state for the CPU power level. Hence an
- * assertion is added to prevent us from accessing the wrong index.
+ * assertion is added to prevent us from accessing the CPU power level.
  *****************************************************************************/
 static void psci_set_req_local_pwr_state(unsigned int pwrlvl,
 					 unsigned int cpu_idx,
 					 plat_local_state_t req_pwr_state)
 {
-	/*
-	 * This should never happen, we have this here to avoid
-	 * "array subscript is above array bounds" errors in GCC.
-	 */
 	assert(pwrlvl > PSCI_CPU_PWR_LVL);
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Warray-bounds"
-	psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state;
-#pragma GCC diagnostic pop
+	if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
+			(cpu_idx < PLATFORM_CORE_COUNT)) {
+		psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state;
+	}
 }
 
 /******************************************************************************
@@ -245,7 +241,11 @@
 {
 	assert(pwrlvl > PSCI_CPU_PWR_LVL);
 
-	return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx];
+	if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
+			(cpu_idx < PLATFORM_CORE_COUNT)) {
+		return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx];
+	} else
+		return NULL;
 }
 
 /*
diff --git a/plat/arm/board/corstone700/corstone700_helpers.S b/plat/arm/board/corstone700/corstone700_helpers.S
new file mode 100644
index 0000000..c713f4f
--- /dev/null
+++ b/plat/arm/board/corstone700/corstone700_helpers.S
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+
+	.globl	plat_secondary_cold_boot_setup
+	.globl	plat_get_my_entrypoint
+	.globl	plat_is_my_cpu_primary
+	.globl	plat_arm_calc_core_pos
+
+	/* --------------------------------------------------------------------
+	 * void plat_secondary_cold_boot_setup (void);
+	 *
+	 * For AArch32, cold-booting secondary CPUs is not yet
+	 * implemented and they panic.
+	 * --------------------------------------------------------------------
+	 */
+func plat_secondary_cold_boot_setup
+cb_panic:
+	b	cb_panic
+endfunc plat_secondary_cold_boot_setup
+
+	/* ---------------------------------------------------------------------
+	 * unsigned long plat_get_my_entrypoint (void);
+	 *
+	 * Main job of this routine is to distinguish between a cold and warm
+	 * boot. On Corstone700, this information can be queried from the power
+	 * controller. The Power Control SYS Status Register (PSYSR) indicates
+	 * the wake-up reason for the CPU.
+	 *
+	 * For a cold boot, return 0.
+	 * For a warm boot, Not yet supported.
+	 *
+	 * TODO: PSYSR is a common register and should be
+	 * 	accessed using locks. Since it is not possible
+	 * 	to use locks immediately after a cold reset
+	 * 	we are relying on the fact that after a cold
+	 * 	reset all cpus will read the same WK field
+	 * ---------------------------------------------------------------------
+	 */
+func plat_get_my_entrypoint
+	/* TODO support warm boot */
+	/* Cold reset */
+	mov	r0, #0
+	bx	lr
+endfunc plat_get_my_entrypoint
+
+	/* -----------------------------------------------------
+	 * unsigned int plat_is_my_cpu_primary (void);
+	 *
+	 * Find out whether the current CPU is the primary
+	 * CPU.
+	 * -----------------------------------------------------
+	 */
+func plat_is_my_cpu_primary
+	ldcopr	r0, MPIDR
+	ldr	r1, =MPIDR_AFFINITY_MASK
+	and	r0, r1
+	cmp	r0, #0
+	moveq	r0, #1
+	movne	r0, #0
+	bx	lr
+endfunc plat_is_my_cpu_primary
+
+	/* ---------------------------------------------------------------------
+	 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
+	 *
+	 * Function to calculate the core position on Corstone700.
+	 *
+	 * (ClusterId * MAX_CPUS_PER_CLUSTER * MAX_PE_PER_CPU) +
+	 * (CPUId * MAX_PE_PER_CPU) +
+	 * ThreadId
+	 *
+	 * which can be simplified as:
+	 *
+	 * ((ClusterId * MAX_CPUS_PER_CLUSTER + CPUId) * MAX_PE_PER_CPU)
+	 * + ThreadId
+	 * ---------------------------------------------------------------------
+	 */
+func plat_arm_calc_core_pos
+	mov	r3, r0
+
+	/* Extract individual affinity fields from MPIDR */
+	ubfx	r0, r3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
+	ubfx	r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
+	ubfx	r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
+
+	/* Compute linear position */
+	mov	r3, #CORSTONE700_MAX_CPUS_PER_CLUSTER
+	mla	r1, r2, r3, r1
+	mov	r3, #CORSTONE700_MAX_PE_PER_CPU
+	mla	r0, r1, r3, r0
+
+	bx	lr
+endfunc plat_arm_calc_core_pos
diff --git a/plat/arm/board/corstone700/corstone700_plat.c b/plat/arm/board/corstone700/corstone700_plat.c
new file mode 100644
index 0000000..cee6fd6
--- /dev/null
+++ b/plat/arm/board/corstone700/corstone700_plat.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/bl_common.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+/*
+ * Table of regions to map using the MMU.
+ * Replace or extend the below regions as required
+ */
+
+const mmap_region_t plat_arm_mmap[] = {
+	ARM_MAP_SHARED_RAM,
+	ARM_MAP_NS_DRAM1,
+	CORSTONE700_MAP_DEVICE,
+	{0}
+};
+
+/* Corstone700 only has one always-on power domain and there
+ * is no power control present
+ */
+void __init plat_arm_pwrc_setup(void)
+{
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+	return CORSTONE700_TIMER_BASE_FREQUENCY;
+}
diff --git a/plat/arm/board/corstone700/corstone700_pm.c b/plat/arm/board/corstone700/corstone700_pm.c
new file mode 100644
index 0000000..4884ea5
--- /dev/null
+++ b/plat/arm/board/corstone700/corstone700_pm.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/psci/psci.h>
+#include <plat/arm/common/plat_arm.h>
+
+/*******************************************************************************
+ * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
+ * platform layer will take care of registering the handlers with PSCI.
+ ******************************************************************************/
+plat_psci_ops_t plat_arm_psci_pm_ops = {
+	/* dummy struct */
+	.validate_ns_entrypoint = NULL
+};
+
+const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
+{
+	return ops;
+}
diff --git a/plat/arm/board/corstone700/corstone700_security.c b/plat/arm/board/corstone700/corstone700_security.c
new file mode 100644
index 0000000..39b2fc9
--- /dev/null
+++ b/plat/arm/board/corstone700/corstone700_security.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * We assume that all security programming is done by the primary core.
+ */
+void plat_arm_security_setup(void)
+{
+	/*
+	 * If the platform had additional peripheral specific security
+	 * configurations, those would be configured here.
+	 */
+}
diff --git a/plat/arm/board/corstone700/corstone700_topology.c b/plat/arm/board/corstone700/corstone700_topology.c
new file mode 100644
index 0000000..d9445e0
--- /dev/null
+++ b/plat/arm/board/corstone700/corstone700_topology.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+
+/* The Corstone700 power domain tree descriptor */
+static unsigned char corstone700_power_domain_tree_desc
+			[PLAT_ARM_CLUSTER_COUNT + 2];
+/*******************************************************************************
+ * This function dynamically constructs the topology according to
+ * CLUSTER_COUNT and returns it.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+	int i;
+
+	/*
+	 * The highest level is the system level. The next level is constituted
+	 * by clusters and then cores in clusters.
+	 */
+	corstone700_power_domain_tree_desc[0] = 1;
+	corstone700_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT;
+
+	for (i = 0; i < PLAT_ARM_CLUSTER_COUNT; i++)
+		corstone700_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT;
+
+	return corstone700_power_domain_tree_desc;
+}
+
+/******************************************************************************
+ * This function implements a part of the critical interface between the PSCI
+ * generic layer and the platform that allows the former to query the platform
+ * to convert an MPIDR to a unique linear index. An error code (-1) is
+ * returned in case the MPIDR is invalid.
+ *****************************************************************************/
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+	return plat_arm_calc_core_pos(mpidr);
+}
diff --git a/plat/arm/board/corstone700/include/platform_def.h b/plat/arm/board/corstone700/include/platform_def.h
new file mode 100644
index 0000000..de99b06
--- /dev/null
+++ b/plat/arm/board/corstone700/include/platform_def.h
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <lib/utils_def.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <plat/arm/board/common/v2m_def.h>
+#include <plat/arm/common/arm_spm_def.h>
+#include <plat/common/common_def.h>
+
+/* Core/Cluster/Thread counts for Corstone700 */
+#define CORSTONE700_CLUSTER_COUNT		1
+#define CORSTONE700_MAX_CPUS_PER_CLUSTER	4
+#define CORSTONE700_MAX_PE_PER_CPU		1
+#define CORSTONE700_CORE_COUNT		(CORSTONE700_CLUSTER_COUNT *	\
+					CORSTONE700_MAX_CPUS_PER_CLUSTER * \
+					CORSTONE700_MAX_PE_PER_CPU)
+#define PLATFORM_CORE_COUNT		CORSTONE700_CORE_COUNT
+#define PLAT_ARM_CLUSTER_COUNT		CORSTONE700_CLUSTER_COUNT
+
+/* UART related constants */
+#define PLAT_ARM_BOOT_UART_BASE		0x1a510000
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ	V2M_IOFPGA_UART0_CLK_IN_HZ
+#define PLAT_ARM_RUN_UART_BASE		0x1a520000
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ	V2M_IOFPGA_UART1_CLK_IN_HZ
+#define ARM_CONSOLE_BAUDRATE		115200
+#define PLAT_ARM_CRASH_UART_BASE	PLAT_ARM_RUN_UART_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ	PLAT_ARM_RUN_UART_CLK_IN_HZ
+
+/* Memory related constants */
+#define ARM_DRAM1_BASE			UL(0x80000000)
+#define ARM_DRAM1_SIZE			UL(0x80000000)
+#define ARM_DRAM1_END			(ARM_DRAM1_BASE +	\
+					 ARM_DRAM1_SIZE - 1)
+#define ARM_NS_DRAM1_BASE		ARM_DRAM1_BASE
+#define ARM_NS_DRAM1_SIZE		ARM_DRAM1_SIZE
+#define ARM_NS_DRAM1_END                (ARM_NS_DRAM1_BASE +	\
+					ARM_NS_DRAM1_SIZE - 1)
+#define ARM_TRUSTED_SRAM_BASE		UL(0x02000000)
+#define ARM_SHARED_RAM_BASE		ARM_TRUSTED_SRAM_BASE
+#define ARM_SHARED_RAM_SIZE		UL(0x00001000)  /* 4 KB */
+#define PLAT_ARM_TRUSTED_SRAM_SIZE	0x00040000	/* 256 KB */
+
+/* The remaining Trusted SRAM is used to load the BL images */
+#define ARM_BL_RAM_BASE			(ARM_SHARED_RAM_BASE +  \
+					ARM_SHARED_RAM_SIZE)
+#define ARM_BL_RAM_SIZE			(PLAT_ARM_TRUSTED_SRAM_SIZE -   \
+					ARM_SHARED_RAM_SIZE)
+
+/*
+ * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding
+ * the page reserved for fw_configs) to BL32
+ */
+#define BL32_BASE			(ARM_BL_RAM_BASE + PAGE_SIZE)
+#define BL32_LIMIT			(ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ */
+#define CACHE_WRITEBACK_GRANULE		(U(1) << ARM_CACHE_WRITEBACK_SHIFT)
+#define ARM_CACHE_WRITEBACK_SHIFT	6
+
+/*
+ * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base
+ * and limit. Leave enough space for BL2 meminfo.
+ */
+#define ARM_TB_FW_CONFIG_BASE		(ARM_BL_RAM_BASE + sizeof(meminfo_t))
+#define ARM_TB_FW_CONFIG_LIMIT		(ARM_BL_RAM_BASE + (PAGE_SIZE / 2U))
+
+/*
+ * The max number of regions like RO(code), coherent and data required by
+ * different BL stages which need to be mapped in the MMU.
+ */
+#define ARM_BL_REGIONS			2
+#define PLAT_ARM_MMAP_ENTRIES		8
+#define MAX_XLAT_TABLES			5
+#define MAX_MMAP_REGIONS		(PLAT_ARM_MMAP_ENTRIES +        \
+					ARM_BL_REGIONS)
+
+/* GIC related constants */
+#define PLAT_ARM_GICD_BASE			0x1C010000
+#define PLAT_ARM_GICC_BASE			0x1C02F000
+
+/* Timer/watchdog related constants */
+#define ARM_SYS_CNTCTL_BASE			UL(0x1a200000)
+#define ARM_SYS_CNTREAD_BASE			UL(0x1a210000)
+#define ARM_SYS_TIMCTL_BASE			UL(0x1a220000)
+#define CORSTONE700_TIMER_BASE_FREQUENCY	UL(24000000)
+#define CORSTONE700_IRQ_TZ_WDOG			32
+#define CORSTONE700_IRQ_SEC_SYS_TIMER		34
+
+#define PLAT_MAX_PWR_LVL			2
+/*
+ * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
+ * power levels have a 1:1 mapping with the MPIDR affinity levels.
+ */
+#define ARM_PWR_LVL0		MPIDR_AFFLVL0
+#define ARM_PWR_LVL1		MPIDR_AFFLVL1
+#define ARM_PWR_LVL2		MPIDR_AFFLVL2
+
+/*
+ *  Macros for local power states in ARM platforms encoded by State-ID field
+ *  within the power-state parameter.
+ */
+/* Local power state for power domains in Run state. */
+#define ARM_LOCAL_STATE_RUN	U(0)
+/* Local power state for retention. Valid only for CPU power domains */
+#define ARM_LOCAL_STATE_RET	U(1)
+/* Local power state for OFF/power-down. Valid for CPU and cluster
+ * power domains
+ */
+#define ARM_LOCAL_STATE_OFF	U(2)
+
+#define PLAT_ARM_TRUSTED_MAILBOX_BASE	ARM_TRUSTED_SRAM_BASE
+#define PLAT_ARM_NSTIMER_FRAME_ID	U(1)
+
+#define PLAT_ARM_NS_IMAGE_OFFSET	(ARM_DRAM1_BASE + UL(0x8000000))
+
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+
+/*
+ * This macro defines the deepest retention state possible. A higher state
+ * ID will represent an invalid or a power down state.
+ */
+#define PLAT_MAX_RET_STATE		1
+
+/*
+ * This macro defines the deepest power down states possible. Any state ID
+ * higher than this is invalid.
+ */
+#define PLAT_MAX_OFF_STATE		2
+
+#define PLATFORM_STACK_SIZE		UL(0x440)
+
+#define ARM_MAP_SHARED_RAM		MAP_REGION_FLAT(		\
+						ARM_SHARED_RAM_BASE,	\
+						ARM_SHARED_RAM_SIZE,	\
+						MT_DEVICE | MT_RW | MT_SECURE)
+
+#define ARM_MAP_NS_DRAM1		MAP_REGION_FLAT(		\
+						ARM_NS_DRAM1_BASE,	\
+						ARM_NS_DRAM1_SIZE,	\
+						MT_MEMORY | MT_RW | MT_NS)
+
+#define ARM_MAP_BL_RO			MAP_REGION_FLAT(		\
+						BL_CODE_BASE,		\
+						BL_CODE_END		\
+							- BL_CODE_BASE,	\
+						MT_CODE | MT_SECURE),	\
+					MAP_REGION_FLAT(		\
+						BL_RO_DATA_BASE,	\
+						BL_RO_DATA_END		\
+						- BL_RO_DATA_BASE,	\
+						MT_RO_DATA | MT_SECURE)
+#if USE_COHERENT_MEM
+#define ARM_MAP_BL_COHERENT_RAM		MAP_REGION_FLAT(		\
+						BL_COHERENT_RAM_BASE,	\
+						BL_COHERENT_RAM_END	\
+						- BL_COHERENT_RAM_BASE,	\
+						MT_DEVICE | MT_RW | MT_SECURE)
+#endif
+
+#define CORSTONE700_DEVICE_BASE		(0x1A000000)
+#define CORSTONE700_DEVICE_SIZE		(0x26000000)
+#define CORSTONE700_MAP_DEVICE	MAP_REGION_FLAT(			\
+					CORSTONE700_DEVICE_BASE,	\
+					CORSTONE700_DEVICE_SIZE,	\
+					MT_DEVICE | MT_RW | MT_SECURE)
+
+#define ARM_IRQ_SEC_PHY_TIMER		29
+
+#define ARM_IRQ_SEC_SGI_0		8
+#define ARM_IRQ_SEC_SGI_1		9
+#define ARM_IRQ_SEC_SGI_2		10
+#define ARM_IRQ_SEC_SGI_3		11
+#define ARM_IRQ_SEC_SGI_4		12
+#define ARM_IRQ_SEC_SGI_5		13
+#define ARM_IRQ_SEC_SGI_6		14
+#define ARM_IRQ_SEC_SGI_7		15
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define ARM_G1S_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,	\
+		(grp), GIC_INTR_CFG_LEVEL), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,	\
+		(grp), GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,	\
+		(grp), GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,	\
+		(grp), GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,	\
+		(grp), GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,	\
+		(grp), GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,	\
+		(grp), GIC_INTR_CFG_EDGE)
+
+#define ARM_G0_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+		GIC_INTR_CFG_EDGE)
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_ARM_G1S_IRQ_PROPS(grp)	\
+	ARM_G1S_IRQ_PROPS(grp),	\
+	INTR_PROP_DESC(CORSTONE700_IRQ_TZ_WDOG,	\
+		GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL),	\
+	INTR_PROP_DESC(CORSTONE700_IRQ_SEC_SYS_TIMER,	\
+		GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL)	\
+
+#define PLAT_ARM_G0_IRQ_PROPS(grp)	ARM_G0_IRQ_PROPS(grp)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/corstone700/platform.mk b/plat/arm/board/corstone700/platform.mk
new file mode 100644
index 0000000..bff3589
--- /dev/null
+++ b/plat/arm/board/corstone700/platform.mk
@@ -0,0 +1,49 @@
+#
+# Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+CORSTONE700_CPU_LIBS	+=	lib/cpus/aarch32/cortex_a32.S
+
+BL32_SOURCES		+=	plat/arm/common/aarch32/arm_helpers.S	\
+				plat/arm/common/arm_console.c	\
+				plat/arm/common/arm_common.c	\
+				lib/xlat_tables/aarch32/xlat_tables.c	\
+				lib/xlat_tables/xlat_tables_common.c	\
+				${CORSTONE700_CPU_LIBS}
+
+PLAT_INCLUDES		:=	-Iplat/arm/board/corstone700/include
+
+NEED_BL32		:=	yes
+
+CORSTONE700_GIC_SOURCES      :=	drivers/arm/gic/common/gic_common.c     \
+				drivers/arm/gic/v2/gicv2_main.c         \
+				drivers/arm/gic/v2/gicv2_helpers.c      \
+				plat/common/plat_gicv2.c                \
+				plat/arm/common/arm_gicv2.c
+
+# BL1/BL2 Image not a part of the capsule Image for Corstone700
+override NEED_BL1	:=	no
+override NEED_BL2	:=	no
+override NEED_BL2U	:=	no
+
+#TFA for Corstone700 starts from BL32
+override RESET_TO_SP_MIN	:=	1
+
+#Device tree
+CORSTONE700_HW_CONFIG_DTS	:=	fdts/corstone700.dts
+CORSTONE700_HW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}.dtb
+FDT_SOURCES			+=	${CORSTONE700_HW_CONFIG_DTS}
+$(eval CORSTONE700_HW_CONFIG	:=	${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(CORSTONE700_HW_CONFIG_DTS)))
+
+# Add the HW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${CORSTONE700_HW_CONFIG},--hw-config))
+
+# Check for Linux kernel as a BL33 image by default
+$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
+  ifndef ARM_PRELOADED_DTB_BASE
+    $(error "ARM_PRELOADED_DTB_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used.")
+  endif
+  $(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
+include plat/arm/board/common/board_common.mk
diff --git a/plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c b/plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c
new file mode 100644
index 0000000..2fc0e0d
--- /dev/null
+++ b/plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
+			u_register_t arg2, u_register_t arg3)
+{
+	arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+}
diff --git a/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk b/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk
new file mode 100644
index 0000000..57e1ec3
--- /dev/null
+++ b/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk
@@ -0,0 +1,18 @@
+#
+# Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# SP_MIN source files specific to FVP platform
+BL32_SOURCES	+=	drivers/cfi/v2m/v2m_flash.c				\
+			lib/utils/mem_region.c					\
+			plat/arm/board/corstone700/corstone700_helpers.S	\
+			plat/arm/board/corstone700/corstone700_topology.c	\
+			plat/arm/board/corstone700/corstone700_security.c	\
+			plat/arm/board/corstone700/corstone700_plat.c		\
+			plat/arm/board/corstone700/corstone700_pm.c		\
+			plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c	\
+			${CORSTONE700_GIC_SOURCES}
+
+include plat/arm/common/sp_min/arm_sp_min.mk
diff --git a/plat/arm/board/fvp/fvp_bl1_setup.c b/plat/arm/board/fvp/fvp_bl1_setup.c
index b90ddcd..8f6170d 100644
--- a/plat/arm/board/fvp/fvp_bl1_setup.c
+++ b/plat/arm/board/fvp/fvp_bl1_setup.c
@@ -48,6 +48,9 @@
 {
 	arm_bl1_platform_setup();
 
+	/* Initialize System level generic or SP804 timer */
+	fvp_timer_init();
+
 	/* On FVP RevC, initialize SMMUv3 */
 	if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U)
 		smmuv3_security_init(PLAT_FVP_SMMUV3_BASE);
diff --git a/plat/arm/board/fvp/fvp_bl2_setup.c b/plat/arm/board/fvp/fvp_bl2_setup.c
index d280949..89636d1 100644
--- a/plat/arm/board/fvp/fvp_bl2_setup.c
+++ b/plat/arm/board/fvp/fvp_bl2_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -25,15 +25,6 @@
 {
 	arm_bl2_platform_setup();
 
-#if FVP_USE_SP804_TIMER
-	/* Enable the clock override for SP804 timer 0, which means that no
-	 * clock dividers are applied and the raw (35 MHz) clock will be used */
-	mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV);
-
-	/* Initialize delay timer driver using SP804 dual timer 0 */
-	sp804_timer_init(V2M_SP804_TIMER0_BASE,
-			SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
-#else
-	generic_delay_timer_init();
-#endif /* FVP_USE_SP804_TIMER */
+	/* Initialize System level generic or SP804 timer */
+	fvp_timer_init();
 }
diff --git a/plat/arm/board/fvp/fvp_bl2u_setup.c b/plat/arm/board/fvp/fvp_bl2u_setup.c
index a8db055..fd73767 100644
--- a/plat/arm/board/fvp/fvp_bl2u_setup.c
+++ b/plat/arm/board/fvp/fvp_bl2u_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -14,6 +14,9 @@
 {
 	arm_bl2u_early_platform_setup(mem_layout, plat_info);
 
+	/* Initialize System level generic or SP804 timer */
+	fvp_timer_init();
+
 	/* Initialize the platform config for future decision making */
 	fvp_config_setup();
 }
diff --git a/plat/arm/board/fvp/fvp_bl31_setup.c b/plat/arm/board/fvp/fvp_bl31_setup.c
index 3f92d37..8627c5e 100644
--- a/plat/arm/board/fvp/fvp_bl31_setup.c
+++ b/plat/arm/board/fvp/fvp_bl31_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -34,6 +34,9 @@
 	 */
 	fvp_interconnect_enable();
 
+	/* Initialize System level generic or SP804 timer */
+	fvp_timer_init();
+
 	/* On FVP RevC, initialize SMMUv3 */
 	if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U)
 		smmuv3_init(PLAT_FVP_SMMUV3_BASE);
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 36cd500..a948796 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -10,6 +10,8 @@
 #include <drivers/arm/cci.h>
 #include <drivers/arm/ccn.h>
 #include <drivers/arm/gicv2.h>
+#include <drivers/arm/sp804_delay_timer.h>
+#include <drivers/generic_delay_timer.h>
 #include <lib/mmio.h>
 #include <lib/xlat_tables/xlat_tables_compat.h>
 #include <plat/arm/common/arm_config.h>
@@ -407,3 +409,23 @@
 	return arm_get_mbedtls_heap(heap_addr, heap_size);
 }
 #endif
+
+void fvp_timer_init(void)
+{
+#if FVP_USE_SP804_TIMER
+	/* Enable the clock override for SP804 timer 0, which means that no
+	 * clock dividers are applied and the raw (35MHz) clock will be used.
+	 */
+	mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV);
+
+	/* Initialize delay timer driver using SP804 dual timer 0 */
+	sp804_timer_init(V2M_SP804_TIMER0_BASE,
+			SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
+#else
+	generic_delay_timer_init();
+
+	/* Enable System level generic timer */
+	mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
+			CNTCR_FCREQ(0U) | CNTCR_EN);
+#endif /* FVP_USE_SP804_TIMER */
+}
diff --git a/plat/arm/board/fvp/fvp_private.h b/plat/arm/board/fvp/fvp_private.h
index 5067d3a..3590370 100644
--- a/plat/arm/board/fvp/fvp_private.h
+++ b/plat/arm/board/fvp/fvp_private.h
@@ -18,6 +18,7 @@
 void fvp_interconnect_init(void);
 void fvp_interconnect_enable(void);
 void fvp_interconnect_disable(void);
+void fvp_timer_init(void);
 void tsp_early_platform_setup(void);
 
 #endif /* FVP_PRIVATE_H */
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 0eb62c4..617da2d 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -127,6 +127,7 @@
 
 BL1_SOURCES		+=	drivers/arm/smmu/smmu_v3.c			\
 				drivers/arm/sp805/sp805.c			\
+				drivers/delay_timer/delay_timer.c		\
 				drivers/io/io_semihosting.c			\
 				lib/semihosting/semihosting.c			\
 				lib/semihosting/${ARCH}/semihosting_call.S	\
@@ -138,6 +139,12 @@
 				${FVP_CPU_LIBS}					\
 				${FVP_INTERCONNECT_SOURCES}
 
+ifeq (${FVP_USE_SP804_TIMER},1)
+BL1_SOURCES		+=	drivers/arm/sp804/sp804_delay_timer.c
+else
+BL1_SOURCES		+=	drivers/delay_timer/generic_delay_timer.c
+endif
+
 
 BL2_SOURCES		+=	drivers/arm/sp805/sp805.c			\
 				drivers/io/io_semihosting.c			\
@@ -167,8 +174,13 @@
 BL2U_SOURCES		+=	plat/arm/board/fvp/fvp_bl2u_setup.c		\
 				${FVP_SECURITY_SOURCES}
 
+ifeq (${FVP_USE_SP804_TIMER},1)
+BL2U_SOURCES		+=	drivers/arm/sp804/sp804_delay_timer.c
+endif
+
 BL31_SOURCES		+=	drivers/arm/fvp/fvp_pwrc.c			\
 				drivers/arm/smmu/smmu_v3.c			\
+				drivers/delay_timer/delay_timer.c		\
 				drivers/cfi/v2m/v2m_flash.c			\
 				lib/utils/mem_region.c				\
 				plat/arm/board/fvp/fvp_bl31_setup.c		\
@@ -181,6 +193,12 @@
 				${FVP_INTERCONNECT_SOURCES}			\
 				${FVP_SECURITY_SOURCES}
 
+ifeq (${FVP_USE_SP804_TIMER},1)
+BL31_SOURCES		+=	drivers/arm/sp804/sp804_delay_timer.c
+else
+BL31_SOURCES		+=	drivers/delay_timer/generic_delay_timer.c
+endif
+
 # Add the FDT_SOURCES and options for Dynamic Config (only for Unix env)
 ifdef UNIX_MK
 FVP_HW_CONFIG_DTS	:=	fdts/${FVP_DT_PREFIX}.dts
diff --git a/plat/arm/board/juno/fdts/juno_tb_fw_config.dts b/plat/arm/board/juno/fdts/juno_tb_fw_config.dts
new file mode 100644
index 0000000..a8ab6c5
--- /dev/null
+++ b/plat/arm/board/juno/fdts/juno_tb_fw_config.dts
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+	/* Platform Config */
+	compatible = "arm,tb_fw";
+	/* Disable authentication for development */
+	disable_auth = <0x0>;
+	/*
+	 * The following two entries are placeholders for Mbed TLS
+	 * heap information. The default values don't matter since
+	 * they will be overwritten by BL1.
+	 * In case of having shared Mbed TLS heap between BL1 and BL2,
+	 * BL1 will populate these two properties with the respective
+	 * info about the shared heap. This info will be available for
+	 * BL2 in order to locate and re-use the heap.
+	 */
+	mbedtls_heap_addr = <0x0 0x0>;
+	mbedtls_heap_size = <0x0>;
+};
diff --git a/plat/arm/board/juno/juno_common.c b/plat/arm/board/juno/juno_common.c
index 98c5d3c..9570d2d 100644
--- a/plat/arm/board/juno/juno_common.c
+++ b/plat/arm/board/juno/juno_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -47,6 +47,9 @@
 	ARM_MAP_OPTEE_CORE_MEM,
 	ARM_OPTEE_PAGEABLE_LOAD_MEM,
 #endif
+#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
+	ARM_MAP_BL1_RW,
+#endif
 	{0}
 };
 #endif
diff --git a/plat/arm/board/juno/juno_security.c b/plat/arm/board/juno/juno_security.c
index 6566b15..32823e0 100644
--- a/plat/arm/board/juno/juno_security.c
+++ b/plat/arm/board/juno/juno_security.c
@@ -3,6 +3,7 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+#include <assert.h>
 
 #include <common/debug.h>
 #include <drivers/arm/nic_400.h>
@@ -149,6 +150,9 @@
 #if TRUSTED_BOARD_BOOT
 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
 {
-	return get_mbedtls_heap_helper(heap_addr, heap_size);
+	assert(heap_addr != NULL);
+	assert(heap_size != NULL);
+
+	return arm_get_mbedtls_heap(heap_addr, heap_size);
 }
 #endif
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index ea7f851..bd6bae5 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -150,8 +150,14 @@
     endif
 endif
 
+# Add the FDT_SOURCES and options for Dynamic Config
+FDT_SOURCES		+=	plat/arm/board/juno/fdts/${PLAT}_tb_fw_config.dts
+TB_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
+
+# Add the TB_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
+
 include plat/arm/board/common/board_common.mk
 include plat/arm/common/arm_common.mk
 include plat/arm/soc/common/soc_css.mk
 include plat/arm/css/common/css_common.mk
-
diff --git a/plat/common/aarch64/crash_console_helpers.S b/plat/common/aarch64/crash_console_helpers.S
index 2a48baf..e2950f5 100644
--- a/plat/common/aarch64/crash_console_helpers.S
+++ b/plat/common/aarch64/crash_console_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -125,9 +125,18 @@
 	b.eq	putc_continue
 	ldr	x2, [x15, #CONSOLE_T_PUTC]
 	cbz	x2, putc_continue
+	cmp	w14, #'\n'
+	b.ne	putc
+	tst	w1, #CONSOLE_FLAG_TRANSLATE_CRLF
+	b.eq	putc
 	mov	x1, x15
+	mov	w0, #'\r'
 	blr	x2
+	ldr	x2, [x15, #CONSOLE_T_PUTC]
+putc:
+	mov	x1, x15
 	mov	w0, w14
+	blr	x2
 putc_continue:
 	ldr	x15, [x15]			/* X15 = next struct */
 	b	putc_loop
diff --git a/plat/intel/soc/agilex/soc/agilex_memory_controller.c b/plat/intel/soc/agilex/soc/agilex_memory_controller.c
index f09238c..5f3cae7 100644
--- a/plat/intel/soc/agilex/soc/agilex_memory_controller.c
+++ b/plat/intel/soc/agilex/soc/agilex_memory_controller.c
@@ -160,8 +160,6 @@
 		return status;
 	}
 
-/*	mmio_clrbits_32(AGX_RSTMGR_BRGMODRST, AGX_RSTMGR_BRGMODRST_DDRSCH);*/
-
 	status = mem_calibration();
 	if (status) {
 		ERROR("DDR: Memory Calibration Failed\n");
@@ -169,7 +167,6 @@
 	}
 
 	configure_hmc_adaptor_regs();
-/*	configure_ddr_sched_ctrl_regs();*/
 
 	return 0;
 }
@@ -359,17 +356,18 @@
 	mmio_write_32(AGX_MPFE_HMC_ADP(ADP_DRAMADDRWIDTH), data);
 
 	/* Enable nonsecure access to DDR */
-	mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT,
-			AGX_DDR_SIZE - 1);
-	mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT,
-			0x1f);
+	data = get_physical_dram_size();
 
-	mmio_write_32(AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT,
-			AGX_DDR_SIZE - 1);
+	if (data < AGX_DDR_SIZE)
+		data = AGX_DDR_SIZE;
+
+	mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT, data - 1);
+	mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT, 0x1f);
+
+	mmio_write_32(AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT, data - 1);
 
 	mmio_write_32(AGX_SOC_NOC_FW_DDR_SCR_ENABLESET, BIT(0) | BIT(8));
 
-
 	/* ECC enablement */
 	data = mmio_read_32(AGX_MPFE_IOHMC_REG_CTRLCFG1);
 	if (data & (1 << AGX_IOHMC_CTRLCFG1_ENABLE_ECC_OFST)) {
diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
index b47be6d..13ca6aa 100644
--- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
+++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -218,49 +218,6 @@
 	ret
 endfunc platform_mem_init
 
-	/* ---------------------------------------------
-	 * int plat_crash_console_init(void)
-	 * Function to initialize the crash console
-	 * without a C Runtime to print crash report.
-	 * Clobber list : x0 - x4
-	 * ---------------------------------------------
-	 */
-func plat_crash_console_init
-	mov	x0, #0
-	adr	x1, tegra_console_base
-	ldr	x1, [x1]
-	cbz	x1, 1f
-	mov	w0, #1
-1:	ret
-endfunc plat_crash_console_init
-
-	/* ---------------------------------------------
-	 * int plat_crash_console_putc(void)
-	 * Function to print a character on the crash
-	 * console without a C Runtime.
-	 * Clobber list : x1, x2
-	 * ---------------------------------------------
-	 */
-func plat_crash_console_putc
-	adr	x1, tegra_console_base
-	ldr	x1, [x1]
-	b	console_core_putc
-endfunc plat_crash_console_putc
-
-	/* ---------------------------------------------
-	 * int plat_crash_console_flush()
-	 * Function to force a write of all buffered
-	 * data that hasn't been output.
-	 * Out : return -1 on error else return 0.
-	 * Clobber list : x0, x1
-	 * ---------------------------------------------
-	 */
-func plat_crash_console_flush
-	adr	x0, tegra_console_base
-	ldr	x0, [x0]
-	b	console_core_flush
-endfunc plat_crash_console_flush
-
 	/* ---------------------------------------------------
 	 * Function to handle a platform reset and store
 	 * input parameters passed by BL2.
diff --git a/plat/nvidia/tegra/common/drivers/spe/shared_console.S b/plat/nvidia/tegra/common/drivers/spe/shared_console.S
index c1fbc84..a3e110e 100644
--- a/plat/nvidia/tegra/common/drivers/spe/shared_console.S
+++ b/plat/nvidia/tegra/common/drivers/spe/shared_console.S
@@ -1,9 +1,10 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 #include <asm_macros.S>
+#include <console_macros.S>
 
 #define CONSOLE_NUM_BYTES_SHIFT		24
 #define CONSOLE_FLUSH_DATA_TO_PORT	(1 << 26)
@@ -20,37 +21,43 @@
 	 * finally displays everything on the UART port.
 	 */
 
-	.globl	console_core_init
-	.globl	console_core_putc
-	.globl	console_core_getc
-	.globl	console_core_flush
+	.globl	console_spe_core_init
+	.globl	console_spe_core_putc
+	.globl	console_spe_core_getc
+	.globl	console_spe_core_flush
+	.globl	console_spe_putc
+	.globl	console_spe_getc
+	.globl	console_spe_flush
+	.globl	console_spe_register
 
-	/* -----------------------------------------------
-	 * int console_core_init(uintptr_t base_addr,
-	 * unsigned int uart_clk, unsigned int baud_rate)
-	 * Function to initialize the console without a
-	 * C Runtime to print debug information. This
-	 * function will be accessed by console_init and
-	 * crash reporting.
-	 * In: x0 - console base address
-	 *     w1 - Uart clock in Hz
+	/* -------------------------------------------------
+	 * int console_spe_register(uintptr_t baseaddr,
+	 *     uint32_t clock, uint32_t baud,
+	 *     console_spe_t *console);
+	 * Function to initialize and register a new spe
+	 * console. Storage passed in for the console struct
+	 * *must* be persistent (i.e. not from the stack).
+	 * In: x0 - UART register base address
+	 *     w1 - UART clock in Hz
 	 *     w2 - Baud rate
-	 * Out: return 1 on success else 0 on error
-	 * Clobber list : x1, x2
-	 * -----------------------------------------------
+	 *     x3 - pointer to empty console_spe_t struct
+	 * Out: return 1 on success, 0 on error
+	 * Clobber list : x0, x1, x2, x6, x7, x14
+	 * -------------------------------------------------
 	 */
-func console_core_init
-	/* Check the input base address */
-	cbz	x0, core_init_fail
-	mov	w0, #1
-	ret
-core_init_fail:
+func console_spe_register
+	cbz	x3, register_fail
+	str	x0, [x3, #CONSOLE_T_DRVDATA]
+	mov	x0, x3
+	finish_console_register spe putc=1, getc=1, flush=1
+
+register_fail:
 	mov	w0, wzr
 	ret
-endfunc console_core_init
+endfunc console_spe_register
 
 	/* --------------------------------------------------------
-	 * int console_core_putc(int c, uintptr_t base_addr)
+	 * int console_spe_core_putc(int c, uintptr_t base_addr)
 	 * Function to output a character over the console. It
 	 * returns the character printed on success or -1 on error.
 	 * In : w0 - character to be printed
@@ -59,7 +66,7 @@
 	 * Clobber list : x2
 	 * --------------------------------------------------------
 	 */
-func console_core_putc
+func console_spe_core_putc
 	/* Check the input parameter */
 	cbz	x1, putc_error
 
@@ -95,32 +102,48 @@
 putc_error:
 	mov	w0, #-1
 	ret
-endfunc console_core_putc
+endfunc console_spe_core_putc
+
+	/* --------------------------------------------------------
+	 * int console_spe_putc(int c, console_spe_t *console)
+	 * Function to output a character over the console. It
+	 * returns the character printed on success or -1 on error.
+	 * In : w0 - character to be printed
+	 *      x1 - pointer to console_t structure
+	 * Out : return -1 on error else return character.
+	 * Clobber list : x2
+	 * --------------------------------------------------------
+	 */
+func console_spe_putc
+	ldr	x1, [x1, #CONSOLE_T_DRVDATA]
+	b	console_spe_core_putc
+endfunc console_spe_putc
 
 	/* ---------------------------------------------
-	 * int console_core_getc(uintptr_t base_addr)
+	 * int console_spe_getc(console_spe_t *console)
 	 * Function to get a character from the console.
 	 * It returns the character grabbed on success
-	 * or -1 on error.
-	 * In : x0 - console base address
+	 * or -1 if no character is available.
+	 * In : x0 - pointer to console_t structure
+	 * Out: w0 - character if available, else -1
 	 * Clobber list : x0, x1
 	 * ---------------------------------------------
 	 */
-func console_core_getc
+func console_spe_getc
 	mov	w0, #-1
 	ret
-endfunc console_core_getc
+endfunc console_spe_getc
 
-	/* ---------------------------------------------
-	 * int console_core_flush(uintptr_t base_addr)
+	/* -------------------------------------------------
+	 * int console_spe_core_flush(uintptr_t base_addr)
 	 * Function to force a write of all buffered
 	 * data that hasn't been output.
 	 * In : x0 - console base address
 	 * Out : return -1 on error else return 0.
 	 * Clobber list : x0, x1
-	 * ---------------------------------------------
+	 * -------------------------------------------------
 	 */
-func console_core_flush
+func console_spe_core_flush
 	cbz	x0, flush_error
 
 	/* flush console */
@@ -131,4 +154,18 @@
 flush_error:
 	mov	w0, #-1
 	ret
-endfunc console_core_flush
+endfunc console_spe_core_flush
+
+	/* ---------------------------------------------
+	 * int console_spe_flush(console_spe_t *console)
+	 * Function to force a write of all buffered
+	 * data that hasn't been output.
+	 * In : x0 - pointer to console_t structure
+	 * Out : return -1 on error else return 0.
+	 * Clobber list : x0, x1
+	 * ---------------------------------------------
+	 */
+func console_spe_flush
+	ldr	x0, [x0, #CONSOLE_T_DRVDATA]
+	b	console_spe_core_flush
+endfunc console_spe_flush
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index a9d037f..f89e77a 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -49,7 +49,6 @@
 IMPORT_SYM(uint64_t, __TEXT_END__,	TEXT_END);
 
 extern uint64_t tegra_bl31_phys_base;
-extern uint64_t tegra_console_base;
 
 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
@@ -130,9 +129,10 @@
 	struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
 	plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
 	image_info_t bl32_img_info = { {0} };
-	uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
+	uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end, console_base;
 	uint32_t console_clock;
 	int32_t ret;
+	static console_16550_t console;
 
 	/*
 	 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
@@ -194,14 +194,18 @@
 	 * Get the base address of the UART controller to be used for the
 	 * console
 	 */
-	tegra_console_base = plat_get_console_from_id(plat_params->uart_id);
+	console_base = plat_get_console_from_id(plat_params->uart_id);
 
-	if (tegra_console_base != 0U) {
+	if (console_base != 0U) {
 		/*
 		 * Configure the UART port to be used as the console
 		 */
-		(void)console_init(tegra_console_base, console_clock,
-			     TEGRA_CONSOLE_BAUDRATE);
+		(void)console_16550_register(console_base,
+					     console_clock,
+					     TEGRA_CONSOLE_BAUDRATE,
+					     &console);
+		console_set_scope(&console.console, CONSOLE_FLAG_BOOT |
+			CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
 	}
 
 	/*
diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk
index 2a2f278..34b5638 100644
--- a/plat/nvidia/tegra/common/tegra_common.mk
+++ b/plat/nvidia/tegra/common/tegra_common.mk
@@ -20,9 +20,9 @@
 				plat/common/plat_gicv2.c			\
 				${COMMON_DIR}/tegra_gicv2.c
 
-BL31_SOURCES		+=	drivers/console/aarch64/console.S		\
-				drivers/delay_timer/delay_timer.c		\
+BL31_SOURCES		+=	drivers/delay_timer/delay_timer.c		\
 				drivers/io/io_storage.c				\
+				plat/common/aarch64/crash_console_helpers.S	\
 				${TEGRA_GICv2_SOURCES}				\
 				${COMMON_DIR}/aarch64/tegra_helpers.S		\
 				${COMMON_DIR}/drivers/pmc/pmc.c			\
diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c
index e06a116..8ba02d6 100644
--- a/plat/nvidia/tegra/common/tegra_pm.c
+++ b/plat/nvidia/tegra/common/tegra_pm.c
@@ -26,7 +26,6 @@
 
 extern uint64_t tegra_bl31_phys_base;
 extern uint64_t tegra_sec_entry_point;
-extern uint64_t tegra_console_base;
 
 /*
  * tegra_fake_system_suspend acts as a boolean var controlling whether
@@ -219,7 +218,8 @@
 	/* Disable console if we are entering deep sleep. */
 	if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
 			PSTATE_ID_SOC_POWERDN) {
-		(void)console_uninit();
+		(void)console_flush();
+		console_switch_state(0);
 	}
 
 	/* disable GICC */
@@ -269,7 +269,6 @@
 void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
 {
 	const plat_params_from_bl2_t *plat_params;
-	uint32_t console_clock;
 
 	/*
 	 * Initialize the GIC cpu and distributor interfaces
@@ -282,20 +281,8 @@
 	if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
 			PSTATE_ID_SOC_POWERDN) {
 
-		/*
-		 * Reference clock used by the FPGAs is a lot slower.
-		 */
-		if (tegra_platform_is_fpga()) {
-			console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
-		} else {
-			console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
-		}
-
-		/* Initialize the runtime console */
-		if (tegra_console_base != 0ULL) {
-			(void)console_init(tegra_console_base, console_clock,
-				     TEGRA_CONSOLE_BAUDRATE);
-		}
+		/* Restart console output. */
+		console_switch_state(CONSOLE_FLAG_RUNTIME);
 
 		/*
 		 * Restore Memory Controller settings as it loses state
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index cdd9e08..34a096c 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,6 +11,7 @@
 
 #include <arch.h>
 #include <arch_helpers.h>
+#include <drivers/ti/uart/uart_16550.h>
 #include <lib/psci/psci.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
 
diff --git a/plat/renesas/rcar/bl2_cpg_init.c b/plat/renesas/rcar/bl2_cpg_init.c
index ed9b772..c3ca9ea 100644
--- a/plat/renesas/rcar/bl2_cpg_init.c
+++ b/plat/renesas/rcar/bl2_cpg_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -109,12 +109,12 @@
 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
 static void bl2_realtime_cpg_init_h3(void)
 {
-	uint32_t cut = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK;
+	uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
 	uint32_t cr0, cr8;
 
-	cr0 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ?
+	cr0 = (cut == PRR_PRODUCT_10 || cut == PRR_PRODUCT_11) ?
 	    0x00200000U : 0x00210000U;
-	cr8 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ?
+	cr8 = (cut == PRR_PRODUCT_10 || cut == PRR_PRODUCT_11) ?
 	    0x01F1FFF4U : 0x01F1FFF7U;
 
 	cpg_write(RMSTPCR0, cr0);
@@ -329,7 +329,7 @@
 {
 	uint32_t boot_cpu = mmio_read_32(RCAR_MODEMR) & MODEMR_BOOT_CPU_MASK;
 #if RCAR_LSI == RCAR_AUTO
-	uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
+	uint32_t product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
 #endif
 	bl2_secure_cpg_init();
 
@@ -338,22 +338,22 @@
 #if RCAR_LSI == RCAR_AUTO
 
 		switch (product) {
-		case RCAR_PRODUCT_H3:
+		case PRR_PRODUCT_H3:
 			bl2_realtime_cpg_init_h3();
 			break;
-		case RCAR_PRODUCT_M3:
+		case PRR_PRODUCT_M3:
 			bl2_realtime_cpg_init_m3();
 			break;
-		case RCAR_PRODUCT_M3N:
+		case PRR_PRODUCT_M3N:
 			bl2_realtime_cpg_init_m3n();
 			break;
-		case RCAR_PRODUCT_V3M:
+		case PRR_PRODUCT_V3M:
 			bl2_realtime_cpg_init_v3m();
 			break;
-		case RCAR_PRODUCT_E3:
+		case PRR_PRODUCT_E3:
 			bl2_realtime_cpg_init_e3();
 			break;
-		case RCAR_PRODUCT_D3:
+		case PRR_PRODUCT_D3:
 			bl2_realtime_cpg_init_d3();
 			break;
 		default:
@@ -381,25 +381,25 @@
 void bl2_system_cpg_init(void)
 {
 #if RCAR_LSI == RCAR_AUTO
-	uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
+	uint32_t product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
 
 	switch (product) {
-	case RCAR_PRODUCT_H3:
+	case PRR_PRODUCT_H3:
 		bl2_system_cpg_init_h3();
 		break;
-	case RCAR_PRODUCT_M3:
+	case PRR_PRODUCT_M3:
 		bl2_system_cpg_init_m3();
 		break;
-	case RCAR_PRODUCT_M3N:
+	case PRR_PRODUCT_M3N:
 		bl2_system_cpg_init_m3n();
 		break;
-	case RCAR_PRODUCT_V3M:
+	case PRR_PRODUCT_V3M:
 		bl2_system_cpg_init_v3m();
 		break;
-	case RCAR_PRODUCT_E3:
+	case PRR_PRODUCT_E3:
 		bl2_system_cpg_init_e3();
 		break;
-	case RCAR_PRODUCT_D3:
+	case PRR_PRODUCT_D3:
 		bl2_system_cpg_init_d3();
 		break;
 	default:
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
index 3c9b56f..ebe6ddd 100644
--- a/plat/renesas/rcar/bl2_plat_setup.c
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -65,22 +65,22 @@
 
 /* R-Car Gen3 product check */
 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
-#define TARGET_PRODUCT			RCAR_PRODUCT_H3
+#define TARGET_PRODUCT			PRR_PRODUCT_H3
 #define TARGET_NAME			"R-Car H3"
 #elif RCAR_LSI == RCAR_M3
-#define TARGET_PRODUCT			RCAR_PRODUCT_M3
+#define TARGET_PRODUCT			PRR_PRODUCT_M3
 #define TARGET_NAME			"R-Car M3"
 #elif RCAR_LSI == RCAR_M3N
-#define TARGET_PRODUCT			RCAR_PRODUCT_M3N
+#define TARGET_PRODUCT			PRR_PRODUCT_M3N
 #define TARGET_NAME			"R-Car M3N"
 #elif RCAR_LSI == RCAR_V3M
-#define TARGET_PRODUCT			RCAR_PRODUCT_V3M
+#define TARGET_PRODUCT			PRR_PRODUCT_V3M
 #define TARGET_NAME			"R-Car V3M"
 #elif RCAR_LSI == RCAR_E3
-#define TARGET_PRODUCT			RCAR_PRODUCT_E3
+#define TARGET_PRODUCT			PRR_PRODUCT_E3
 #define TARGET_NAME			"R-Car E3"
 #elif RCAR_LSI == RCAR_D3
-#define TARGET_PRODUCT			RCAR_PRODUCT_D3
+#define TARGET_PRODUCT			PRR_PRODUCT_D3
 #define TARGET_NAME			"R-Car D3"
 #elif RCAR_LSI == RCAR_AUTO
 #define TARGET_NAME			"R-Car H3/M3/M3N/V3M"
@@ -238,17 +238,17 @@
 		bl2_secure_setting();
 
 	reg = mmio_read_32(RCAR_PRR);
-	product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
-	product = reg & RCAR_PRODUCT_MASK;
-	cut = reg & RCAR_CUT_MASK;
+	product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
+	product = reg & PRR_PRODUCT_MASK;
+	cut = reg & PRR_CUT_MASK;
 
-	if (product == RCAR_PRODUCT_M3 && RCAR_CUT_VER30 > cut)
+	if (product == PRR_PRODUCT_M3 && PRR_PRODUCT_30 > cut)
 		goto tlb;
 
-	if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut)
+	if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut)
 		goto tlb;
 
-	if (product == RCAR_PRODUCT_D3)
+	if (product == PRR_PRODUCT_D3)
 		goto tlb;
 
 	/* Disable MFIS write protection */
@@ -261,28 +261,28 @@
 	    boot_cpu != MODEMR_BOOT_CPU_CA53)
 		goto mmu;
 
-	if (product_cut == RCAR_PRODUCT_H3_CUT20) {
+	if (product_cut == PRR_PRODUCT_H3_CUT20) {
 		mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
 		mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE);
 		mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
 		mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE);
 		mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE);
 		mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE);
-	} else if (product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) ||
-		   product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11)) {
+	} else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
+		   product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) {
 		mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
 		mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
-	} else if ((product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) ||
-		   (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER11))) {
+	} else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) ||
+		   (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) {
 		mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
 		mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE);
 		mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
 	}
 
-	if (product_cut == (RCAR_PRODUCT_H3_CUT20) ||
-	    product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) ||
-	    product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11) ||
-	    product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) {
+	if (product_cut == (PRR_PRODUCT_H3_CUT20) ||
+	    product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
+	    product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) ||
+	    product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) {
 		mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE);
 		mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE);
 		mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE);
@@ -458,28 +458,28 @@
 	}
 
 	reg = mmio_read_32(RCAR_PRR);
-	switch (reg & RCAR_PRODUCT_MASK) {
-	case RCAR_PRODUCT_H3:
+	switch (reg & PRR_PRODUCT_MASK) {
+	case PRR_PRODUCT_H3:
 		ret = fdt_appendprop_string(fdt, 0, "compatible",
 					    "renesas,r8a7795");
 		break;
-	case RCAR_PRODUCT_M3:
+	case PRR_PRODUCT_M3:
 		ret = fdt_appendprop_string(fdt, 0, "compatible",
 					    "renesas,r8a7796");
 		break;
-	case RCAR_PRODUCT_M3N:
+	case PRR_PRODUCT_M3N:
 		ret = fdt_appendprop_string(fdt, 0, "compatible",
 					    "renesas,r8a77965");
 		break;
-	case RCAR_PRODUCT_V3M:
+	case PRR_PRODUCT_V3M:
 		ret = fdt_appendprop_string(fdt, 0, "compatible",
 					    "renesas,r8a77970");
 		break;
-	case RCAR_PRODUCT_E3:
+	case PRR_PRODUCT_E3:
 		ret = fdt_appendprop_string(fdt, 0, "compatible",
 					    "renesas,r8a77990");
 		break;
-	case RCAR_PRODUCT_D3:
+	case PRR_PRODUCT_D3:
 		ret = fdt_appendprop_string(fdt, 0, "compatible",
 					    "renesas,r8a77995");
 		break;
@@ -572,7 +572,7 @@
 	};
 
 	switch (product) {
-	case RCAR_PRODUCT_H3:
+	case PRR_PRODUCT_H3:
 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
 		/* 4GB(1GBx4) */
 		dram_config[1] = 0x40000000ULL;
@@ -594,7 +594,7 @@
 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */
 		break;
 
-	case RCAR_PRODUCT_M3:
+	case PRR_PRODUCT_M3:
 #if (RCAR_GEN3_ULCB == 1)
 		/* 2GB(1GBx2 2ch split) */
 		dram_config[1] = 0x40000000ULL;
@@ -606,17 +606,17 @@
 #endif
 		break;
 
-	case RCAR_PRODUCT_M3N:
+	case PRR_PRODUCT_M3N:
 		/* 2GB(1GBx2) */
 		dram_config[1] = 0x80000000ULL;
 		break;
 
-	case RCAR_PRODUCT_V3M:
+	case PRR_PRODUCT_V3M:
 		/* 1GB(512MBx2) */
 		dram_config[1] = 0x40000000ULL;
 		break;
 
-	case RCAR_PRODUCT_E3:
+	case PRR_PRODUCT_E3:
 #if (RCAR_DRAM_DDR3L_MEMCONF == 0)
 		/* 1GB(512MBx2) */
 		dram_config[1] = 0x40000000ULL;
@@ -629,7 +629,7 @@
 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */
 		break;
 
-	case RCAR_PRODUCT_D3:
+	case PRR_PRODUCT_D3:
 		/* 512MB */
 		dram_config[1] = 0x20000000ULL;
 		break;
@@ -716,26 +716,26 @@
 	       version_of_renesas);
 
 	reg = mmio_read_32(RCAR_PRR);
-	product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
-	product = reg & RCAR_PRODUCT_MASK;
+	product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
+	product = reg & PRR_PRODUCT_MASK;
 
 	switch (product) {
-	case RCAR_PRODUCT_H3:
+	case PRR_PRODUCT_H3:
 		str = product_h3;
 		break;
-	case RCAR_PRODUCT_M3:
+	case PRR_PRODUCT_M3:
 		str = product_m3;
 		break;
-	case RCAR_PRODUCT_M3N:
+	case PRR_PRODUCT_M3N:
 		str = product_m3n;
 		break;
-	case RCAR_PRODUCT_V3M:
+	case PRR_PRODUCT_V3M:
 		str = product_v3m;
 		break;
-	case RCAR_PRODUCT_E3:
+	case PRR_PRODUCT_E3:
 		str = product_e3;
 		break;
-	case RCAR_PRODUCT_D3:
+	case PRR_PRODUCT_D3:
 		str = product_d3;
 		break;
 	default:
@@ -743,9 +743,9 @@
 		break;
 	}
 
-	if ((RCAR_PRODUCT_M3 == product) &&
-	    (RCAR_CUT_VER20 == (reg & RCAR_MAJOR_MASK))) {
-		if (RCAR_M3_CUT_VER11 == (reg & RCAR_CUT_MASK)) {
+	if ((PRR_PRODUCT_M3 == product) &&
+	    (PRR_PRODUCT_20 == (reg & RCAR_MAJOR_MASK))) {
+		if (RCAR_M3_CUT_VER11 == (reg & PRR_CUT_MASK)) {
 			/* M3 Ver.1.1 or Ver.1.2 */
 			NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n",
 				str);
@@ -761,7 +761,7 @@
 		NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor);
 	}
 
-	if (product == RCAR_PRODUCT_E3) {
+	if (product == PRR_PRODUCT_E3) {
 		reg = mmio_read_32(RCAR_MODEMR);
 		sscg = reg & RCAR_SSCG_MASK;
 		str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off;
@@ -930,7 +930,7 @@
 		mmio_write_32(CPG_CA53DBGRCR,
 			      DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR));
 
-	if (product_cut == RCAR_PRODUCT_H3_CUT10) {
+	if (product_cut == PRR_PRODUCT_H3_CUT10) {
 		reg = mmio_read_32(CPG_PLL2CR);
 		reg &= ~((uint32_t) 1 << 5);
 		mmio_write_32(CPG_PLL2CR, reg);
@@ -1016,7 +1016,7 @@
 
 	/* Set frequency data in CNTFID0 */
 	reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT];
-	reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+	reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
 	switch (modemr_pll) {
 	case MD14_MD13_TYPE_0:
 		rcar_get_board_type(&board_type, &board_rev);
@@ -1025,7 +1025,7 @@
 		}
 		break;
 	case MD14_MD13_TYPE_3:
-		if (RCAR_PRODUCT_H3_CUT10 == reg) {
+		if (PRR_PRODUCT_H3_CUT10 == reg) {
 			reg_cntfid = reg_cntfid >> 1U;
 		}
 		break;
diff --git a/plat/renesas/rcar/bl31_plat_setup.c b/plat/renesas/rcar/bl31_plat_setup.c
index 4fff233..bd83c41 100644
--- a/plat/renesas/rcar/bl31_plat_setup.c
+++ b/plat/renesas/rcar/bl31_plat_setup.c
@@ -44,9 +44,9 @@
 {
 	uint32_t prd;
 
-	prd = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+	prd = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
 
-	if (RCAR_PRODUCT_H3_CUT10 == prd || RCAR_PRODUCT_H3_CUT11 == prd) {
+	if (PRR_PRODUCT_H3_CUT10 == prd || PRR_PRODUCT_H3_CUT11 == prd) {
 		cci_map[0U] = CCI500_CLUSTER0_SL_IFACE_IX;
 		cci_map[1U] = CCI500_CLUSTER1_SL_IFACE_IX;
 	}
diff --git a/plat/renesas/rcar/include/rcar_def.h b/plat/renesas/rcar/include/rcar_def.h
index ac7dc17..a60f9b6 100644
--- a/plat/renesas/rcar/include/rcar_def.h
+++ b/plat/renesas/rcar/include/rcar_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -147,31 +147,34 @@
 #define	RCAR_SYSCISCR		U(0xE6180008)	/* Interrupt stat clear */
 /* Product register */
 #define	RCAR_PRR			U(0xFFF00044)
-#define RCAR_PRODUCT_MASK		U(0x00007F00)
-#define RCAR_CUT_MASK			U(0x000000FF)
-#define RCAR_PRODUCT_H3			U(0x00004F00)
-#define RCAR_PRODUCT_M3			U(0x00005200)
-#define RCAR_PRODUCT_V3M		U(0x00005400)
-#define RCAR_PRODUCT_M3N		U(0x00005500)
-#define RCAR_PRODUCT_E3			U(0x00005700)
-#define RCAR_PRODUCT_D3			U(0x00005800)
-#define RCAR_CUT_VER10			U(0x00000000)
-#define RCAR_CUT_VER11			U(0x00000001)	/* H3/M3N/E3 Ver.1.1 */
 #define RCAR_M3_CUT_VER11		U(0x00000010)	/* M3 Ver.1.1/Ver.1.2 */
-#define RCAR_CUT_VER20			U(0x00000010)
-#define RCAR_CUT_VER30			U(0x00000020)
 #define RCAR_MAJOR_MASK			U(0x000000F0)
 #define RCAR_MINOR_MASK			U(0x0000000F)
-#define RCAR_PRODUCT_SHIFT		U(8)
+#define PRR_PRODUCT_SHIFT		U(8)
 #define RCAR_MAJOR_SHIFT		U(4)
 #define RCAR_MINOR_SHIFT		U(0)
 #define RCAR_MAJOR_OFFSET		U(1)
 #define RCAR_M3_MINOR_OFFSET		U(2)
-#define RCAR_PRODUCT_H3_CUT10		(RCAR_PRODUCT_H3 | U(0x00))	/* 1.0 */
-#define RCAR_PRODUCT_H3_CUT11		(RCAR_PRODUCT_H3 | U(0x01))	/* 1.1 */
-#define RCAR_PRODUCT_H3_CUT20		(RCAR_PRODUCT_H3 | U(0x10))	/* 2.0 */
-#define RCAR_PRODUCT_M3_CUT10		(RCAR_PRODUCT_M3 | U(0x00))	/* 1.0 */
-#define RCAR_PRODUCT_M3_CUT11		(RCAR_PRODUCT_M3 | U(0x10))
+#define PRR_PRODUCT_H3_CUT10		(PRR_PRODUCT_H3 | U(0x00))	/* 1.0 */
+#define PRR_PRODUCT_H3_CUT11		(PRR_PRODUCT_H3 | U(0x01))	/* 1.1 */
+#define PRR_PRODUCT_H3_CUT20		(PRR_PRODUCT_H3 | U(0x10))	/* 2.0 */
+#define PRR_PRODUCT_M3_CUT10		(PRR_PRODUCT_M3 | U(0x00))	/* 1.0 */
+#define PRR_PRODUCT_M3_CUT11		(PRR_PRODUCT_M3 | U(0x10))
+#define PRR				0xFFF00044U
+#define PRR_PRODUCT_MASK		0x00007F00U
+#define PRR_CUT_MASK			0x000000FFU
+#define PRR_PRODUCT_H3			0x00004F00U	/* R-Car H3 */
+#define PRR_PRODUCT_M3			0x00005200U	/* R-Car M3-W */
+#define PRR_PRODUCT_V3M			0x00005400U	/* R-Car V3M */
+#define PRR_PRODUCT_M3N			0x00005500U	/* R-Car M3-N */
+#define PRR_PRODUCT_V3H			0x00005600U	/* R-Car V3H */
+#define PRR_PRODUCT_E3			0x00005700U	/* R-Car E3 */
+#define PRR_PRODUCT_D3			0x00005800U	/* R-Car D3 */
+#define PRR_PRODUCT_10			0x00U		/* Ver.1.0 */
+#define PRR_PRODUCT_11			0x01U		/* Ver.1.1 */
+#define PRR_PRODUCT_20			0x10U		/* Ver.2.0 */
+#define PRR_PRODUCT_21			0x11U		/* Ver.2.1 */
+#define PRR_PRODUCT_30			0x20U		/* Ver.3.0 */
 #define RCAR_CPU_MASK_CA57		U(0x80000000)
 #define RCAR_CPU_MASK_CA53		U(0x04000000)
 #define RCAR_CPU_HAVE_CA57		U(0x00000000)
diff --git a/tools/cert_create/src/ext.c b/tools/cert_create/src/ext.c
index 055ddbf..57fb47d 100644
--- a/tools/cert_create/src/ext.c
+++ b/tools/cert_create/src/ext.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -284,6 +284,7 @@
 	ex = ext_new(nid, crit, p, sz);
 
 	/* Clean up */
+	BIO_free(mem);
 	OPENSSL_free(p);
 
 	return ex;
diff --git a/tools/cert_create/src/key.c b/tools/cert_create/src/key.c
index 871f9ee..fece770 100644
--- a/tools/cert_create/src/key.c
+++ b/tools/cert_create/src/key.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -73,6 +73,7 @@
 		goto err;
 	}
 
+	BN_free(e);
 	return 1;
 err:
 	RSA_free(rsa);
diff --git a/tools/cert_create/src/main.c b/tools/cert_create/src/main.c
index ed56620..0f588cc 100644
--- a/tools/cert_create/src/main.c
+++ b/tools/cert_create/src/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */