| commit | 960a12b3fb4699cad83973c853fb5064ed6a75d0 | [log] [tgz] |
|---|---|---|
| author | Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> | Fri Aug 16 11:08:14 2019 +0800 |
| committer | Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> | Mon Aug 19 10:56:31 2019 +0800 |
| tree | 6a33c0a28c429705fcc976f2addae8c758dc8098 | |
| parent | d1b6013d8485094d948e6b6039b8d119a907ecf8 [diff] |
intel: agilex: Clear PLL lostlock bypass mode To provide glitchless clock to downstream logic even if clock toggles Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1