tree bf9ccdb0c877be6a4d43a097d19f42ad811a21c5
parent 57f4b6f83974b17e0aae04e17f9d95a5659ac88b
author Antonio Borneo <antonio.borneo@st.com> 1564404376 +0200
committer Yann Gautier <yann.gautier@st.com> 1570094260 +0200

fdts: stm32mp1: move FDCAN to PLL4_R

LTDC modifies the clock frequency to adapt it to the display. Such
frequency change is not detected by the FDCAN driver that instead
caches the value at probe and pretends to use it later.

This change fixes the issue by moving the FDCAN to PLL4_R,
leaving the LTDC alone on PLL4_Q.

Signed-off-by: Antonio Borneo <antonio.borneo@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I8230868b2b5fd6deb6e3f9dc3911030d8d484c58