| /* |
| * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| */ |
| #ifndef SPM_H |
| #define SPM_H |
| |
| #define SPM_POWERON_CONFIG_SET (SPM_BASE + 0x000) |
| #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x010) |
| #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x014) |
| #define SPM_CLK_SETTLE (SPM_BASE + 0x100) |
| #define SPM_CA7_CPU1_PWR_CON (SPM_BASE + 0x218) |
| #define SPM_CA7_CPU2_PWR_CON (SPM_BASE + 0x21c) |
| #define SPM_CA7_CPU3_PWR_CON (SPM_BASE + 0x220) |
| #define SPM_CA7_CPU1_L1_PDN (SPM_BASE + 0x264) |
| #define SPM_CA7_CPU2_L1_PDN (SPM_BASE + 0x26c) |
| #define SPM_CA7_CPU3_L1_PDN (SPM_BASE + 0x274) |
| #define SPM_MD32_SRAM_CON (SPM_BASE + 0x2c8) |
| #define SPM_PCM_CON0 (SPM_BASE + 0x310) |
| #define SPM_PCM_CON1 (SPM_BASE + 0x314) |
| #define SPM_PCM_IM_PTR (SPM_BASE + 0x318) |
| #define SPM_PCM_IM_LEN (SPM_BASE + 0x31c) |
| #define SPM_PCM_REG_DATA_INI (SPM_BASE + 0x320) |
| #define SPM_PCM_EVENT_VECTOR0 (SPM_BASE + 0x340) |
| #define SPM_PCM_EVENT_VECTOR1 (SPM_BASE + 0x344) |
| #define SPM_PCM_EVENT_VECTOR2 (SPM_BASE + 0x348) |
| #define SPM_PCM_EVENT_VECTOR3 (SPM_BASE + 0x34c) |
| #define SPM_PCM_MAS_PAUSE_MASK (SPM_BASE + 0x354) |
| #define SPM_PCM_PWR_IO_EN (SPM_BASE + 0x358) |
| #define SPM_PCM_TIMER_VAL (SPM_BASE + 0x35c) |
| #define SPM_PCM_TIMER_OUT (SPM_BASE + 0x360) |
| #define SPM_PCM_REG0_DATA (SPM_BASE + 0x380) |
| #define SPM_PCM_REG1_DATA (SPM_BASE + 0x384) |
| #define SPM_PCM_REG2_DATA (SPM_BASE + 0x388) |
| #define SPM_PCM_REG3_DATA (SPM_BASE + 0x38c) |
| #define SPM_PCM_REG4_DATA (SPM_BASE + 0x390) |
| #define SPM_PCM_REG5_DATA (SPM_BASE + 0x394) |
| #define SPM_PCM_REG6_DATA (SPM_BASE + 0x398) |
| #define SPM_PCM_REG7_DATA (SPM_BASE + 0x39c) |
| #define SPM_PCM_REG8_DATA (SPM_BASE + 0x3a0) |
| #define SPM_PCM_REG9_DATA (SPM_BASE + 0x3a4) |
| #define SPM_PCM_REG10_DATA (SPM_BASE + 0x3a8) |
| #define SPM_PCM_REG11_DATA (SPM_BASE + 0x3ac) |
| #define SPM_PCM_REG12_DATA (SPM_BASE + 0x3b0) |
| #define SPM_PCM_REG13_DATA (SPM_BASE + 0x3b4) |
| #define SPM_PCM_REG14_DATA (SPM_BASE + 0x3b8) |
| #define SPM_PCM_REG15_DATA (SPM_BASE + 0x3bc) |
| #define SPM_PCM_EVENT_REG_STA (SPM_BASE + 0x3c0) |
| #define SPM_PCM_FSM_STA (SPM_BASE + 0x3c4) |
| #define SPM_PCM_IM_HOST_RW_PTR (SPM_BASE + 0x3c8) |
| #define SPM_PCM_IM_HOST_RW_DAT (SPM_BASE + 0x3cc) |
| #define SPM_PCM_EVENT_VECTOR4 (SPM_BASE + 0x3d0) |
| #define SPM_PCM_EVENT_VECTOR5 (SPM_BASE + 0x3d4) |
| #define SPM_PCM_EVENT_VECTOR6 (SPM_BASE + 0x3d8) |
| #define SPM_PCM_EVENT_VECTOR7 (SPM_BASE + 0x3dc) |
| #define SPM_PCM_SW_INT_SET (SPM_BASE + 0x3e0) |
| #define SPM_PCM_SW_INT_CLEAR (SPM_BASE + 0x3e4) |
| #define SPM_CLK_CON (SPM_BASE + 0x400) |
| #define SPM_SLEEP_PTPOD2_CON (SPM_BASE + 0x408) |
| #define SPM_APMCU_PWRCTL (SPM_BASE + 0x600) |
| #define SPM_AP_DVFS_CON_SET (SPM_BASE + 0x604) |
| #define SPM_AP_STANBY_CON (SPM_BASE + 0x608) |
| #define SPM_PWR_STATUS (SPM_BASE + 0x60c) |
| #define SPM_PWR_STATUS_2ND (SPM_BASE + 0x610) |
| #define SPM_AP_BSI_REQ (SPM_BASE + 0x614) |
| #define SPM_SLEEP_TIMER_STA (SPM_BASE + 0x720) |
| #define SPM_SLEEP_WAKEUP_EVENT_MASK (SPM_BASE + 0x810) |
| #define SPM_SLEEP_CPU_WAKEUP_EVENT (SPM_BASE + 0x814) |
| #define SPM_SLEEP_MD32_WAKEUP_EVENT_MASK (SPM_BASE + 0x818) |
| #define SPM_PCM_WDT_TIMER_VAL (SPM_BASE + 0x824) |
| #define SPM_PCM_WDT_TIMER_OUT (SPM_BASE + 0x828) |
| #define SPM_PCM_MD32_MAILBOX (SPM_BASE + 0x830) |
| #define SPM_PCM_MD32_IRQ (SPM_BASE + 0x834) |
| #define SPM_SLEEP_ISR_MASK (SPM_BASE + 0x900) |
| #define SPM_SLEEP_ISR_STATUS (SPM_BASE + 0x904) |
| #define SPM_SLEEP_ISR_RAW_STA (SPM_BASE + 0x910) |
| #define SPM_SLEEP_MD32_ISR_RAW_STA (SPM_BASE + 0x914) |
| #define SPM_SLEEP_WAKEUP_MISC (SPM_BASE + 0x918) |
| #define SPM_SLEEP_BUS_PROTECT_RDY (SPM_BASE + 0x91c) |
| #define SPM_SLEEP_SUBSYS_IDLE_STA (SPM_BASE + 0x920) |
| #define SPM_PCM_RESERVE (SPM_BASE + 0xb00) |
| #define SPM_PCM_RESERVE2 (SPM_BASE + 0xb04) |
| #define SPM_PCM_FLAGS (SPM_BASE + 0xb08) |
| #define SPM_PCM_SRC_REQ (SPM_BASE + 0xb0c) |
| #define SPM_PCM_DEBUG_CON (SPM_BASE + 0xb20) |
| #define SPM_CA7_CPU0_IRQ_MASK (SPM_BASE + 0xb30) |
| #define SPM_CA7_CPU1_IRQ_MASK (SPM_BASE + 0xb34) |
| #define SPM_CA7_CPU2_IRQ_MASK (SPM_BASE + 0xb38) |
| #define SPM_CA7_CPU3_IRQ_MASK (SPM_BASE + 0xb3c) |
| #define SPM_CA15_CPU0_IRQ_MASK (SPM_BASE + 0xb40) |
| #define SPM_CA15_CPU1_IRQ_MASK (SPM_BASE + 0xb44) |
| #define SPM_CA15_CPU2_IRQ_MASK (SPM_BASE + 0xb48) |
| #define SPM_CA15_CPU3_IRQ_MASK (SPM_BASE + 0xb4c) |
| #define SPM_PCM_PASR_DPD_0 (SPM_BASE + 0xb60) |
| #define SPM_PCM_PASR_DPD_1 (SPM_BASE + 0xb64) |
| #define SPM_PCM_PASR_DPD_2 (SPM_BASE + 0xb68) |
| #define SPM_PCM_PASR_DPD_3 (SPM_BASE + 0xb6c) |
| #define SPMC_MP0_CPU0_PWR_CON (SPM_BASE + 0xc40) |
| #define SPMC_MP0_CPU1_PWR_CON (SPM_BASE + 0xc44) |
| #define SPMC_MP0_CPU2_PWR_CON (SPM_BASE + 0xc48) |
| #define SPMC_MP0_CPU3_PWR_CON (SPM_BASE + 0xc4c) |
| #define SPMC_MP0_CPUTOP_PWR_CON (SPM_BASE + 0xc50) |
| #define SPMC_MP0_CPUTOP_CLK_DIS (SPM_BASE + 0xc58) |
| #define SPMC_BYPASS (SPM_BASE + 0xc5c) |
| #define SPM_DDRPHY_MISC (SPM_BASE + 0xc60) |
| #define SPM_SLEEP_CA7_WFI0_EN (SPM_BASE + 0xf00) |
| #define SPM_SLEEP_CA7_WFI1_EN (SPM_BASE + 0xf04) |
| #define SPM_SLEEP_CA7_WFI2_EN (SPM_BASE + 0xf08) |
| #define SPM_SLEEP_CA7_WFI3_EN (SPM_BASE + 0xf0c) |
| #define SPM_SLEEP_CA15_WFI0_EN (SPM_BASE + 0xf10) |
| #define SPM_SLEEP_CA15_WFI1_EN (SPM_BASE + 0xf14) |
| #define SPM_SLEEP_CA15_WFI2_EN (SPM_BASE + 0xf18) |
| #define SPM_SLEEP_CA15_WFI3_EN (SPM_BASE + 0xf1c) |
| |
| #define AP_PLL_CON3 0x1020900c |
| #define AP_PLL_CON4 0x10209010 |
| |
| #define SPM_PROJECT_CODE 0xb16 |
| |
| #define SPM_REGWR_EN (1U << 0) |
| #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) |
| |
| |
| /* #define SPMC_MP0_CPU0_PWR_CON (SPM_BASE + 0xc40) */ |
| /* #define SPMC_MP0_CPU1_PWR_CON (SPM_BASE + 0xc44) */ |
| /* #define SPMC_MP0_CPU2_PWR_CON (SPM_BASE + 0xc48) */ |
| /* #define SPMC_MP0_CPU3_PWR_CON (SPM_BASE + 0xc4c) */ |
| #define SPMC_PWR_ON_2ND (1U << 0) |
| #define SPMC_PWR_RST_B (1U << 1) |
| #define SPMC_PWR_ON (1U << 2) |
| #define SPMC_PWR_CLK_DIS (1U << 0) |
| |
| /* #define SPM_MP0_CPU1_PWR_CON (SPM_BASE + 0x218) */ |
| /* #define SPM_MP0_CPU2_PWR_CON (SPM_BASE + 0x21c) */ |
| /* #define SPM_MP0_CPU3_PWR_CON (SPM_BASE + 0x220) */ |
| //#define PWR_RST_B (1U << 0) |
| //#define PWR_ISO (1U << 1) |
| //#define PWR_ON (1U << 2) |
| //#define PWR_ON_2ND (1U << 3) |
| //#define PWR_CLK_DIS (1U << 4) |
| //#define SRAM_CKISO (1U << 5) |
| //#define SRAM_ISOINT_B (1U << 6) |
| #define DDRPHY_MISC (1U << 12) |
| |
| /* SPM_MP0_CPU1_L1_PDN (SPM_BASE + 0x264) */ |
| /* SPM_MP0_CPU2_L1_PDN (SPM_BASE + 0x26c) */ |
| /* SPM_MP0_CPU3_L1_PDN (SPM_BASE + 0x274) */ |
| //#define L1_PDN (1U << 0) |
| //#define L1_PDN_ACK (1U << 8) |
| |
| /* SPM_PWR_STATUS (SPM_BASE + 0x60c) */ |
| /* SPM_PWR_STATUS_2ND (SPM_BASE + 0x610)*/ |
| #define MP0_CPUTOP (1U << 9) |
| #define MP0_CPU3 (1U << 10) |
| #define MP0_CPU2 (1U << 11) |
| #define MP0_CPU1 (1U << 12) |
| #define MP0_CPU0 (1U << 13) |
| |
| /* SPM_SLEEP_TIMER_STA (SPM_BASE + 0x720) */ |
| #define MP0_CPU0_STANDBYWFI (1U << 16) |
| #define MP0_CPU1_STANDBYWFI (1U << 17) |
| #define MP0_CPU2_STANDBYWFI (1U << 18) |
| #define MP0_CPU3_STANDBYWFI (1U << 19) |
| #define MP0_CPUTOP_STANDBYWFI (1U << 24) |
| |
| /* #define SPM_DDRPHY_MISC (SPM_BASE + 0xc60) */ |
| #define MP0_CPU0_PD_SLPB_CLAMP (1U << 0) |
| #define MP0_CPU1_PD_SLPB_CLAMP (1U << 12) |
| #define MP0_CPU2_PD_SLPB_CLAMP (1U << 13) |
| #define MP0_CPU3_PD_SLPB_CLAMP (1U << 14) |
| |
| #define SPM_CPU_PDN_DIS (1U << 0) |
| #define SPM_CPUTOP_PDN_DIS (1U << 1) |
| #define SPM_L2_DORMANT_DIS (1U << 2) |
| #define SPM_MCU_PDN_DIS (1U << 3) |
| #define SPM_BUS26M_DIS (1U << 4) |
| #define SPM_MPLLOFF_DIS (1U << 5) |
| #define SPM_DDRPHY_S1_DIS (1U << 6) |
| #define SPM_DDRPHY_S0_DIS (1U << 7) |
| #define SPM_FHC_SLEEP_DIS (1U << 8) |
| #define SPM_VPROC_LOW_DIS (1U << 9) |
| #define SPM_INFRA_PDN_DIS (1U << 10) |
| #define SPM_26M_DIS (1U << 11) |
| #define SPM_26M_OFF_DIS (1U << 12) |
| #define SPM_XO_OFF_DIS (1U << 13) |
| #define SPM_32K_LESS (1U << 14) |
| #define SPM_PLL_OFF_DIS (1U << 15) |
| #define SPM_NO_PMIC_WRAP (1U << 16) |
| #define SPM_ALL_IN_ONE_DIS (1U << 17) |
| #define SPM_PLLGP_OFF_DIS (1U << 18) |
| #define SPM_SRAMROM_PDN_DIS (1U << 19) |
| |
| #define POWER_ON_VAL1_DEF 0x01011820 |
| #define PCM_FSM_STA_DEF 0x48490 |
| #define PCM_END_FSM_STA_DEF 0x08490 |
| #define PCM_END_FSM_STA_MASK 0x3fff0 |
| #define PCM_HANDSHAKE_SEND1 0xbeefbeef |
| |
| #define PCM_WDT_TIMEOUT (30 * 32768) |
| #define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) |
| |
| #define PCM_CMD_MASK 0xffff0000 |
| #define PCM_CMD_SUSPEND_PCM 0x50d10000 |
| |
| #define CON0_PCM_KICK (1U << 0) |
| #define CON0_IM_KICK (1U << 1) |
| #define CON0_IM_SLEEP_DVS (1U << 3) |
| #define CON0_PCM_SW_RESET (1U << 15) |
| #define CON0_CFG_KEY (SPM_PROJECT_CODE << 16) |
| |
| #define CON1_IM_SLAVE (1U << 0) |
| #define CON1_MIF_APBEN (1U << 3) |
| #define CON1_PCM_TIMER_EN (1U << 5) |
| #define CON1_IM_NONRP_EN (1U << 6) |
| #define CON1_PCM_WDT_EN (1U << 8) |
| #define CON1_PCM_WDT_WAKE_MODE (1U << 9) |
| #define CON1_SPM_SRAM_SLP_B (1U << 10) |
| #define CON1_SPM_SRAM_ISO_B (1U << 11) |
| #define CON1_EVENT_LOCK_EN (1U << 12) |
| #define CON1_CFG_KEY (SPM_PROJECT_CODE << 16) |
| |
| #define PCM_PWRIO_EN_R0 (1U << 0) |
| #define PCM_PWRIO_EN_R7 (1U << 7) |
| #define PCM_RF_SYNC_R0 (1U << 16) |
| #define PCM_RF_SYNC_R2 (1U << 18) |
| #define PCM_RF_SYNC_R6 (1U << 22) |
| #define PCM_RF_SYNC_R7 (1U << 23) |
| |
| #define CC_SYSCLK0_EN_0 (1U << 0) |
| #define CC_SYSCLK0_EN_1 (1U << 1) |
| #define CC_SYSCLK1_EN_0 (1U << 2) |
| #define CC_SYSCLK1_EN_1 (1U << 3) |
| #define CC_SYSSETTLE_SEL (1U << 4) |
| #define CC_LOCK_INFRA_DCM (1U << 5) |
| #define CC_SRCLKENA_MASK_0 (1U << 6) |
| #define CC_CXO32K_RM_EN_MD1 (1U << 9) |
| #define CC_CXO32K_RM_EN_MD2 (1U << 10) |
| #define CC_CLKSQ1_SEL (1U << 12) |
| #define CC_DISABLE_DORM_PWR (1U << 14) |
| #define CC_MD32_DCM_EN (1U << 18) |
| |
| #define WFI_OP_AND 1 |
| #define WFI_OP_OR 0 |
| |
| #define WAKE_MISC_PCM_TIMER (1U << 19) |
| #define WAKE_MISC_CPU_WAKE (1U << 20) |
| |
| #define ISRM_TWAM (1U << 2) |
| #define ISRM_RET_IRQ0 (1U << 8) |
| #define ISRM_RET_IRQ1 (1U << 9) |
| #define ISRM_RET_IRQ2 (1U << 10) |
| #define ISRM_RET_IRQ3 (1U << 11) |
| #define ISRM_RET_IRQ4 (1U << 12) |
| #define ISRM_RET_IRQ5 (1U << 13) |
| #define ISRM_RET_IRQ6 (1U << 14) |
| #define ISRM_RET_IRQ7 (1U << 15) |
| |
| #define ISRM_RET_IRQ_AUX (ISRM_RET_IRQ7 | ISRM_RET_IRQ6 | \ |
| ISRM_RET_IRQ5 | ISRM_RET_IRQ4 | \ |
| ISRM_RET_IRQ3 | ISRM_RET_IRQ2 | \ |
| ISRM_RET_IRQ1) |
| |
| enum SPM_WAKE_SRC { |
| WAKE_SRC_SPM_MERGE = (1U << 0), /* WAKE_ID_SPM_MERGE */ |
| WAKE_SRC_AUDIO_REQ = (1U << 1), /* WAKE_ID_AUDIO_REQ */ |
| WAKE_SRC_KP = (1U << 2), /* WAKE_ID_KP */ |
| WAKE_SRC_WDT = (1U << 3), /* WAKE_ID_WDT */ |
| WAKE_SRC_GPT = (1U << 4), /* WAKE_ID_GPT */ |
| WAKE_SRC_EINT = (1U << 5), /* WAKE_ID_EINT */ |
| WAKE_SRC_CONN_WDT = (1U << 6), /* WAKE_ID_CONN_WDT */ |
| WAKE_SRC_GCE = (1U << 7), /* WAKE_ID_GCE */ |
| WAKE_SRC_LOW_BAT = (1U << 9), /* WAKE_ID_LOW_BAT */ |
| WAKE_SRC_CONN2AP = (1U << 10), /* WAKE_ID_CONN2AP */ |
| WAKE_SRC_F26M_WAKE = (1U << 11), /* WAKE_ID_F26M_WAKE */ |
| WAKE_SRC_F26M_SLEE = (1U << 12), /* WAKE_ID_F26M_SLEEP */ |
| WAKE_SRC_PCM_WDT = (1U << 13), /* WAKE_ID_PCM_WDT */ |
| WAKE_SRC_USB_CD = (1U << 14), /* WAKE_ID_USB_CD */ |
| WAKE_SRC_USB_PDN = (1U << 15), /* WAKE_ID_USB_PDN */ |
| WAKE_SRC_ETH = (1U << 16), /* WAKE_ID_ETH */ |
| WAKE_SRC_DBGSYS = (1U << 18), /* WAKE_ID_DBGSYS */ |
| WAKE_SRC_UART0 = (1U << 19), /* WAKE_ID_UART0 */ |
| WAKE_SRC_AFE = (1U << 20), /* WAKE_ID_AFE */ |
| WAKE_SRC_THERM = (1U << 21), /* WAKE_ID_THERM */ |
| WAKE_SRC_CIRQ = (1U << 22), /* WAKE_ID_CIRQ */ |
| WAKE_SRC_SEJ = (1U << 23), /* WAKE_ID_SEJ */ |
| WAKE_SRC_SYSPWREQ = (1U << 24), /* WAKE_ID_SYSPWREQ */ |
| WAKE_SRC_IRRX = (1U << 25), /* WAKE_ID_IRRX */ |
| WAKE_SRC_CPU0_IRQ = (1U << 26), /* WAKE_ID_CPU0_IRQ */ |
| WAKE_SRC_CPU1_IRQ = (1U << 27), /* WAKE_ID_CPU1_IRQ */ |
| WAKE_SRC_CPU2_IRQ = (1U << 28), /* WAKE_ID_CPU2_IRQ */ |
| WAKE_SRC_CPU3_IRQ = (1U << 29), /* WAKE_ID_CPU3_IRQ */ |
| WAKE_SRC_APSRC_WAKE = (1U << 30), /* WAKE_ID_APSRC_WAKE */ |
| WAKE_SRC_APSRC_SLEEP = (1U << 31), /* WAKE_ID_APSRC_SLEEP */ |
| }; |
| |
| enum wake_reason_t { |
| WR_NONE = 0, |
| WR_UART_BUSY = 1, |
| WR_PCM_ASSERT = 2, |
| WR_PCM_TIMER = 3, |
| WR_PCM_ABORT = 4, |
| WR_WAKE_SRC = 5, |
| WR_UNKNOWN = 6, |
| }; |
| |
| struct pwr_ctrl { |
| unsigned int pcm_flags; |
| unsigned int pcm_flags_cust; |
| unsigned int pcm_reserve; |
| unsigned int timer_val; |
| unsigned int timer_val_cust; |
| unsigned int wake_src; |
| unsigned int wake_src_cust; |
| unsigned char r0_ctrl_en; |
| unsigned char r7_ctrl_en; |
| unsigned char infra_dcm_lock; |
| unsigned char pcm_apsrc_req; |
| unsigned char pcm_f26m_req; |
| unsigned char mcusys_idle_mask; |
| unsigned char ca15top_idle_mask; |
| unsigned char ca7top_idle_mask; |
| unsigned char wfi_op; |
| unsigned char ca15_wfi0_en; |
| unsigned char ca15_wfi1_en; |
| unsigned char ca15_wfi2_en; |
| unsigned char ca15_wfi3_en; |
| unsigned char ca7_wfi0_en; |
| unsigned char ca7_wfi1_en; |
| unsigned char ca7_wfi2_en; |
| unsigned char ca7_wfi3_en; |
| unsigned char conn_mask; |
| unsigned char gce_req_mask; |
| unsigned char disp0_req_mask; |
| unsigned char disp1_req_mask; |
| unsigned char mfg_req_mask; |
| unsigned char vdec_req_mask; |
| unsigned char mm_ddr_req_mask; |
| unsigned char syspwreq_mask; |
| unsigned char srclkenai_mask; |
| unsigned int param1; |
| unsigned int param2; |
| unsigned int param3; |
| }; |
| |
| struct wake_status { |
| unsigned int assert_pc; |
| unsigned int r12; |
| unsigned int raw_sta; |
| unsigned int wake_misc; |
| unsigned int timer_out; |
| unsigned int r13; |
| unsigned int idle_sta; |
| unsigned int debug_flag; |
| unsigned int event_reg; |
| unsigned int isr; |
| }; |
| |
| struct pcm_desc { |
| const char *version; /* PCM code version */ |
| const unsigned int *base; /* binary array base */ |
| const unsigned int size; /* binary array size */ |
| const unsigned char sess; /* session number */ |
| const unsigned char replace; /* replace mode */ |
| |
| unsigned int vec0; /* event vector 0 config */ |
| unsigned int vec1; /* event vector 1 config */ |
| unsigned int vec2; /* event vector 2 config */ |
| unsigned int vec3; /* event vector 3 config */ |
| unsigned int vec4; /* event vector 4 config */ |
| unsigned int vec5; /* event vector 5 config */ |
| unsigned int vec6; /* event vector 6 config */ |
| unsigned int vec7; /* event vector 7 config */ |
| }; |
| |
| struct spm_lp_scen { |
| const struct pcm_desc *pcmdesc; |
| struct pwr_ctrl *pwrctrl; |
| }; |
| |
| #define EVENT_VEC(event, resume, imme, pc) \ |
| (((pc) << 16) | \ |
| (!!(imme) << 6) | \ |
| (!!(resume) << 6) | \ |
| ((event) & 0x3f)) |
| |
| #define spm_read(addr) mmio_read_32(addr) |
| #define spm_write(addr, val) mmio_write_32(addr, val) |
| |
| #define is_cpu_pdn(flags) (!((flags) & SPM_CPU_PDN_DIS)) |
| #define is_infra_pdn(flags) (!((flags) & SPM_INFRA_PDN_DIS)) |
| #define is_ddrphy_pdn(flags) (!((flags) & SPM_DDRPHY_PDN_DIS)) |
| |
| static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl, |
| unsigned int flags) |
| { |
| if (pwrctrl->pcm_flags_cust == 0) |
| pwrctrl->pcm_flags = flags; |
| else |
| pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust; |
| } |
| |
| static inline void set_pwrctrl_pcm_data(struct pwr_ctrl *pwrctrl, |
| unsigned int data) |
| { |
| pwrctrl->pcm_reserve = data; |
| } |
| |
| void spm_reset_and_init_pcm(void); |
| |
| void spm_init_pcm_register(void); /* init r0 and r7 */ |
| void spm_set_power_control(const struct pwr_ctrl *pwrctrl); |
| void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl); |
| |
| void spm_get_wakeup_status(struct wake_status *wakesta); |
| void spm_set_sysclk_settle(void); |
| void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl); |
| void spm_clean_after_wakeup(void); |
| enum wake_reason_t spm_output_wake_reason(struct wake_status *wakesta); |
| void spm_register_init(void); |
| void spm_go_to_hotplug(void); |
| void spm_init_event_vector(const struct pcm_desc *pcmdesc); |
| void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc); |
| void spm_set_sysclk_settle(void); |
| int is_mcdi_ready(void); |
| int is_hotplug_ready(void); |
| int is_suspend_ready(void); |
| void set_mcdi_ready(void); |
| void set_hotplug_ready(void); |
| void set_suspend_ready(void); |
| void clear_all_ready(void); |
| void spm_lock_init(void); |
| void spm_lock_get(void); |
| void spm_lock_release(void); |
| void spm_boot_init(void); |
| |
| #endif /* SPM_H */ |
