commit 52a109cdf90976413509a04ebcdcdff20d5d0152
author Mark-PK Tsai <mark-pk.tsai@mediatek.com> Fri Nov 08 05:42:49 2019 +0000
committer Jérôme Forissier <jerome@forissier.org> Fri Nov 08 15:58:04 2019 +0100
tree d898ab94a3216ce841e0fa2adad96322bf47b3c0
parent abd18a27bcf0fdf89a55631ee495d62a0b3260e9

core: arm32: disable interrupt in thread_excp_vect_workaround

thread_excp_vect_workaround isn't interrupt safe because it use
the tpidr as a temporary register to save value of r0.
That means if a fiq happened when optee is processing a syscall,
the syscall argument r0 will be changed to unexpected value.

Move `write_tpidrprw r0` out of `vector_prologue_spectre` and add
`cpsid aif` before it to fix this issue.

Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Reviewed-by: Alix Wu <alix.wu@mediatek.com>
Reviewed-by: YJ Chiang <yj.chiang@mediatek.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>