blob: 3686912427ba3ebdba483a22b1f2c131b68e4a80 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Intel AGPGART routines.
3 */
4
Linus Torvalds1da177e2005-04-16 15:20:36 -07005#include <linux/module.h>
6#include <linux/pci.h>
7#include <linux/init.h>
Ahmed S. Darwish1eaf1222007-02-06 18:08:28 +02008#include <linux/kernel.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07009#include <linux/pagemap.h>
10#include <linux/agp_backend.h>
11#include "agp.h"
12
Carlos Martíne914a362008-01-24 10:34:09 +100013#define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
14#define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
Eric Anholt65c25aa2006-09-06 11:57:18 -040015#define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
16#define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
Zhenyu Wang9119f852008-01-23 15:49:26 +100017#define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980
18#define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982
Eric Anholt65c25aa2006-09-06 11:57:18 -040019#define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
20#define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
21#define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
22#define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
Wang Zhenyu4598af32007-04-09 08:51:36 +080023#define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
24#define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
Zhenyu Wangdde47872007-07-26 09:18:09 +080025#define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
Wang Zhenyuc8eebfd2007-05-31 11:34:06 +080026#define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
Zhenyu Wangdde47872007-07-26 09:18:09 +080027#define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
Wang Zhenyudf80b142007-05-31 11:51:12 +080028#define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
Shaohua Li21778322009-02-23 15:19:16 +080029#define PCI_DEVICE_ID_INTEL_IGDGM_HB 0xA010
30#define PCI_DEVICE_ID_INTEL_IGDGM_IG 0xA011
31#define PCI_DEVICE_ID_INTEL_IGDG_HB 0xA000
32#define PCI_DEVICE_ID_INTEL_IGDG_IG 0xA001
Wang Zhenyu874808c62007-06-06 11:16:25 +080033#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
34#define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
35#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
36#define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
37#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
38#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
Zhenyu Wang99d32bd2008-07-30 12:26:50 -070039#define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
40#define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
Zhenyu Wang25ce77a2008-06-19 14:17:58 +100041#define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00
42#define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02
43#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
44#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
45#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
46#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
Zhenyu Wanga50ccc62008-11-17 14:39:00 +080047#define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
48#define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
Eric Anholt65c25aa2006-09-06 11:57:18 -040049
Dave Airlief011ae72008-01-25 11:23:04 +100050/* cover 915 and 945 variants */
51#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
52 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
53 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
54 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
55 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
56 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
57
Eric Anholt65c25aa2006-09-06 11:57:18 -040058#define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
Dave Airlief011ae72008-01-25 11:23:04 +100059 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
60 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
61 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
62 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
Eric Anholt82e14a62008-10-14 11:28:58 -070063 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
Eric Anholt65c25aa2006-09-06 11:57:18 -040064
Wang Zhenyu874808c62007-06-06 11:16:25 +080065#define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
66 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
Shaohua Li21778322009-02-23 15:19:16 +080067 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
68 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
69 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
70
71#define IS_IGD (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
72 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
Eric Anholt65c25aa2006-09-06 11:57:18 -040073
Zhenyu Wang25ce77a2008-06-19 14:17:58 +100074#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
75 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
Eric Anholt82e14a62008-10-14 11:28:58 -070076 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
Zhenyu Wanga50ccc62008-11-17 14:39:00 +080077 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
78 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB)
Zhenyu Wang25ce77a2008-06-19 14:17:58 +100079
Thomas Hellstroma030ce42007-01-23 10:33:43 +010080extern int agp_memory_reserved;
81
82
Linus Torvalds1da177e2005-04-16 15:20:36 -070083/* Intel 815 register */
84#define INTEL_815_APCONT 0x51
85#define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
86
87/* Intel i820 registers */
88#define INTEL_I820_RDCR 0x51
89#define INTEL_I820_ERRSTS 0xc8
90
91/* Intel i840 registers */
92#define INTEL_I840_MCHCFG 0x50
93#define INTEL_I840_ERRSTS 0xc8
94
95/* Intel i850 registers */
96#define INTEL_I850_MCHCFG 0x50
97#define INTEL_I850_ERRSTS 0xc8
98
99/* intel 915G registers */
100#define I915_GMADDR 0x18
101#define I915_MMADDR 0x10
102#define I915_PTEADDR 0x1C
103#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
104#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
Zhenyu Wang25ce77a2008-06-19 14:17:58 +1000105#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
106#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
107#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
108#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
109#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
110#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
111
Dave Airlie6c00a612007-10-29 18:06:10 +1000112#define I915_IFPADDR 0x60
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113
Eric Anholt65c25aa2006-09-06 11:57:18 -0400114/* Intel 965G registers */
115#define I965_MSAC 0x62
Dave Airlie6c00a612007-10-29 18:06:10 +1000116#define I965_IFPADDR 0x70
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117
118/* Intel 7505 registers */
119#define INTEL_I7505_APSIZE 0x74
120#define INTEL_I7505_NCAPID 0x60
121#define INTEL_I7505_NISTAT 0x6c
122#define INTEL_I7505_ATTBASE 0x78
123#define INTEL_I7505_ERRSTS 0x42
124#define INTEL_I7505_AGPCTRL 0x70
125#define INTEL_I7505_MCHCFG 0x50
126
Dave Jonese5524f32007-02-22 18:41:28 -0500127static const struct aper_size_info_fixed intel_i810_sizes[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128{
129 {64, 16384, 4},
130 /* The 32M mode still requires a 64k gatt */
131 {32, 8192, 4}
132};
133
134#define AGP_DCACHE_MEMORY 1
135#define AGP_PHYS_MEMORY 2
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100136#define INTEL_AGP_CACHED_MEMORY 3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137
138static struct gatt_mask intel_i810_masks[] =
139{
140 {.mask = I810_PTE_VALID, .type = 0},
141 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100142 {.mask = I810_PTE_VALID, .type = 0},
143 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
144 .type = INTEL_AGP_CACHED_MEMORY}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145};
146
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800147static struct _intel_private {
148 struct pci_dev *pcidev; /* device one */
149 u8 __iomem *registers;
150 u32 __iomem *gtt; /* I915G */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151 int num_dcache_entries;
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800152 /* gtt_entries is the number of gtt entries that are already mapped
153 * to stolen memory. Stolen memory is larger than the memory mapped
154 * through gtt_entries, as it includes some reserved space for the BIOS
155 * popup and for the GTT.
156 */
157 int gtt_entries; /* i830+ */
Dave Airlie2162e6a2007-11-21 16:36:31 +1000158 union {
159 void __iomem *i9xx_flush_page;
160 void *i8xx_flush_page;
161 };
162 struct page *i8xx_page;
Dave Airlie6c00a612007-10-29 18:06:10 +1000163 struct resource ifp_resource;
Dave Airlie4d64dd92008-01-23 15:34:29 +1000164 int resource_valid;
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800165} intel_private;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166
167static int intel_i810_fetch_size(void)
168{
169 u32 smram_miscc;
170 struct aper_size_info_fixed *values;
171
172 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
173 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
174
175 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700176 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177 return 0;
178 }
179 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
180 agp_bridge->previous_size =
181 agp_bridge->current_size = (void *) (values + 1);
182 agp_bridge->aperture_size_idx = 1;
183 return values[1].size;
184 } else {
185 agp_bridge->previous_size =
186 agp_bridge->current_size = (void *) (values);
187 agp_bridge->aperture_size_idx = 0;
188 return values[0].size;
189 }
190
191 return 0;
192}
193
194static int intel_i810_configure(void)
195{
196 struct aper_size_info_fixed *current_size;
197 u32 temp;
198 int i;
199
200 current_size = A_SIZE_FIX(agp_bridge->current_size);
201
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800202 if (!intel_private.registers) {
203 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
Dave Jonese4ac5e42007-02-04 17:37:42 -0500204 temp &= 0xfff80000;
205
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800206 intel_private.registers = ioremap(temp, 128 * 4096);
207 if (!intel_private.registers) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700208 dev_err(&intel_private.pcidev->dev,
209 "can't remap memory\n");
Dave Jonese4ac5e42007-02-04 17:37:42 -0500210 return -ENOMEM;
211 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700212 }
213
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800214 if ((readl(intel_private.registers+I810_DRAM_CTL)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
216 /* This will need to be dynamically assigned */
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700217 dev_info(&intel_private.pcidev->dev,
218 "detected 4MB dedicated video ram\n");
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800219 intel_private.num_dcache_entries = 1024;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220 }
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800221 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800223 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
224 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225
226 if (agp_bridge->driver->needs_scratch_page) {
227 for (i = 0; i < current_size->num_entries; i++) {
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800228 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229 }
Keith Packard44d49442008-10-14 17:18:45 -0700230 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231 }
232 global_cache_flush();
233 return 0;
234}
235
236static void intel_i810_cleanup(void)
237{
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800238 writel(0, intel_private.registers+I810_PGETBL_CTL);
239 readl(intel_private.registers); /* PCI Posting. */
240 iounmap(intel_private.registers);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241}
242
243static void intel_i810_tlbflush(struct agp_memory *mem)
244{
245 return;
246}
247
248static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
249{
250 return;
251}
252
253/* Exists to support ARGB cursors */
254static void *i8xx_alloc_pages(void)
255{
Dave Airlief011ae72008-01-25 11:23:04 +1000256 struct page *page;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257
Linus Torvalds66c669b2006-11-22 14:55:29 -0800258 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259 if (page == NULL)
260 return NULL;
261
Arjan van de Ven6d238cc2008-01-30 13:34:06 +0100262 if (set_pages_uc(page, 4) < 0) {
263 set_pages_wb(page, 4);
Jan Beulich89cf7cc2007-04-02 14:50:14 +0100264 __free_pages(page, 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265 return NULL;
266 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267 get_page(page);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268 atomic_inc(&agp_bridge->current_memory_agp);
269 return page_address(page);
270}
271
272static void i8xx_destroy_pages(void *addr)
273{
274 struct page *page;
275
276 if (addr == NULL)
277 return;
278
279 page = virt_to_page(addr);
Arjan van de Ven6d238cc2008-01-30 13:34:06 +0100280 set_pages_wb(page, 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281 put_page(page);
Jan Beulich89cf7cc2007-04-02 14:50:14 +0100282 __free_pages(page, 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283 atomic_dec(&agp_bridge->current_memory_agp);
284}
285
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100286static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
287 int type)
288{
289 if (type < AGP_USER_TYPES)
290 return type;
291 else if (type == AGP_USER_CACHED_MEMORY)
292 return INTEL_AGP_CACHED_MEMORY;
293 else
294 return 0;
295}
296
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
298 int type)
299{
300 int i, j, num_entries;
301 void *temp;
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100302 int ret = -EINVAL;
303 int mask_type;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100305 if (mem->page_count == 0)
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100306 goto out;
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100307
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308 temp = agp_bridge->current_size;
309 num_entries = A_SIZE_FIX(temp)->num_entries;
310
Dave Jones6a92a4e2006-02-28 00:54:25 -0500311 if ((pg_start + mem->page_count) > num_entries)
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100312 goto out_err;
313
Dave Jones6a92a4e2006-02-28 00:54:25 -0500314
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100316 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
317 ret = -EBUSY;
318 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320 }
321
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100322 if (type != mem->type)
323 goto out_err;
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100324
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100325 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
326
327 switch (mask_type) {
328 case AGP_DCACHE_MEMORY:
329 if (!mem->is_flushed)
330 global_cache_flush();
331 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
332 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800333 intel_private.registers+I810_PTE_BASE+(i*4));
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100334 }
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800335 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100336 break;
337 case AGP_PHYS_MEMORY:
338 case AGP_NORMAL_MEMORY:
339 if (!mem->is_flushed)
340 global_cache_flush();
341 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
342 writel(agp_bridge->driver->mask_memory(agp_bridge,
343 mem->memory[i],
344 mask_type),
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800345 intel_private.registers+I810_PTE_BASE+(j*4));
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100346 }
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800347 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100348 break;
349 default:
350 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352
353 agp_bridge->driver->tlb_flush(mem);
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100354out:
355 ret = 0;
356out_err:
Dave Airlie9516b032008-06-19 10:42:17 +1000357 mem->is_flushed = true;
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100358 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359}
360
361static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
362 int type)
363{
364 int i;
365
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100366 if (mem->page_count == 0)
367 return 0;
368
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800370 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371 }
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800372 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374 agp_bridge->driver->tlb_flush(mem);
375 return 0;
376}
377
378/*
379 * The i810/i830 requires a physical address to program its mouse
380 * pointer into hardware.
381 * However the Xserver still writes to it through the agp aperture.
382 */
383static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
384{
385 struct agp_memory *new;
386 void *addr;
387
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388 switch (pg_count) {
389 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
390 break;
391 case 4:
392 /* kludge to get 4 physical pages for ARGB cursor */
393 addr = i8xx_alloc_pages();
394 break;
395 default:
396 return NULL;
397 }
398
399 if (addr == NULL)
400 return NULL;
401
402 new = agp_create_memory(pg_count);
403 if (new == NULL)
404 return NULL;
405
Keir Fraser07eee782005-03-30 13:17:04 -0800406 new->memory[0] = virt_to_gart(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700407 if (pg_count == 4) {
408 /* kludge to get 4 physical pages for ARGB cursor */
409 new->memory[1] = new->memory[0] + PAGE_SIZE;
410 new->memory[2] = new->memory[1] + PAGE_SIZE;
411 new->memory[3] = new->memory[2] + PAGE_SIZE;
412 }
413 new->page_count = pg_count;
414 new->num_scratch_pages = pg_count;
415 new->type = AGP_PHYS_MEMORY;
416 new->physical = new->memory[0];
417 return new;
418}
419
420static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
421{
422 struct agp_memory *new;
423
424 if (type == AGP_DCACHE_MEMORY) {
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800425 if (pg_count != intel_private.num_dcache_entries)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426 return NULL;
427
428 new = agp_create_memory(1);
429 if (new == NULL)
430 return NULL;
431
432 new->type = AGP_DCACHE_MEMORY;
433 new->page_count = pg_count;
434 new->num_scratch_pages = 0;
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100435 agp_free_page_array(new);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436 return new;
437 }
438 if (type == AGP_PHYS_MEMORY)
439 return alloc_agpphysmem_i8xx(pg_count, type);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700440 return NULL;
441}
442
443static void intel_i810_free_by_type(struct agp_memory *curr)
444{
445 agp_free_key(curr->key);
Dave Jones6a92a4e2006-02-28 00:54:25 -0500446 if (curr->type == AGP_PHYS_MEMORY) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447 if (curr->page_count == 4)
Keir Fraser07eee782005-03-30 13:17:04 -0800448 i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
Alan Hourihane88d51962005-11-06 23:35:34 -0800449 else {
Jan Beulichda503fa2008-06-18 09:28:00 +0100450 void *va = gart_to_virt(curr->memory[0]);
451
452 agp_bridge->driver->agp_destroy_page(va,
Dave Airliea2721e92007-10-15 10:19:16 +1000453 AGP_PAGE_DESTROY_UNMAP);
Jan Beulichda503fa2008-06-18 09:28:00 +0100454 agp_bridge->driver->agp_destroy_page(va,
Dave Airliea2721e92007-10-15 10:19:16 +1000455 AGP_PAGE_DESTROY_FREE);
Alan Hourihane88d51962005-11-06 23:35:34 -0800456 }
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100457 agp_free_page_array(curr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700458 }
459 kfree(curr);
460}
461
462static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
463 unsigned long addr, int type)
464{
465 /* Type checking must be done elsewhere */
466 return addr | bridge->driver->masks[type].mask;
467}
468
469static struct aper_size_info_fixed intel_i830_sizes[] =
470{
471 {128, 32768, 5},
472 /* The 64M mode still requires a 128k gatt */
473 {64, 16384, 5},
474 {256, 65536, 6},
Eric Anholt65c25aa2006-09-06 11:57:18 -0400475 {512, 131072, 7},
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476};
477
Linus Torvalds1da177e2005-04-16 15:20:36 -0700478static void intel_i830_init_gtt_entries(void)
479{
480 u16 gmch_ctrl;
481 int gtt_entries;
482 u8 rdct;
483 int local = 0;
484 static const int ddt[4] = { 0, 16, 32, 64 };
Eric Anholtc41e0de2006-12-19 12:57:24 -0800485 int size; /* reserved space (in kb) at the top of stolen memory */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700486
Dave Airlief011ae72008-01-25 11:23:04 +1000487 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488
Eric Anholtc41e0de2006-12-19 12:57:24 -0800489 if (IS_I965) {
490 u32 pgetbl_ctl;
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800491 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
Eric Anholtc41e0de2006-12-19 12:57:24 -0800492
Eric Anholtc41e0de2006-12-19 12:57:24 -0800493 /* The 965 has a field telling us the size of the GTT,
494 * which may be larger than what is necessary to map the
495 * aperture.
496 */
497 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
498 case I965_PGETBL_SIZE_128KB:
499 size = 128;
500 break;
501 case I965_PGETBL_SIZE_256KB:
502 size = 256;
503 break;
504 case I965_PGETBL_SIZE_512KB:
505 size = 512;
506 break;
Zhenyu Wang4e8b6e22008-01-23 14:54:37 +1000507 case I965_PGETBL_SIZE_1MB:
508 size = 1024;
509 break;
510 case I965_PGETBL_SIZE_2MB:
511 size = 2048;
512 break;
513 case I965_PGETBL_SIZE_1_5MB:
514 size = 1024 + 512;
515 break;
Eric Anholtc41e0de2006-12-19 12:57:24 -0800516 default:
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700517 dev_info(&intel_private.pcidev->dev,
518 "unknown page table size, assuming 512KB\n");
Eric Anholtc41e0de2006-12-19 12:57:24 -0800519 size = 512;
520 }
521 size += 4; /* add in BIOS popup space */
Shaohua Li21778322009-02-23 15:19:16 +0800522 } else if (IS_G33 && !IS_IGD) {
Wang Zhenyu874808c62007-06-06 11:16:25 +0800523 /* G33's GTT size defined in gmch_ctrl */
524 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
525 case G33_PGETBL_SIZE_1M:
526 size = 1024;
527 break;
528 case G33_PGETBL_SIZE_2M:
529 size = 2048;
530 break;
531 default:
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700532 dev_info(&agp_bridge->dev->dev,
533 "unknown page table size 0x%x, assuming 512KB\n",
Wang Zhenyu874808c62007-06-06 11:16:25 +0800534 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
535 size = 512;
536 }
537 size += 4;
Shaohua Li21778322009-02-23 15:19:16 +0800538 } else if (IS_G4X || IS_IGD) {
Zhenyu Wang25ce77a2008-06-19 14:17:58 +1000539 /* On 4 series hardware, GTT stolen is separate from graphics
Eric Anholt82e14a62008-10-14 11:28:58 -0700540 * stolen, ignore it in stolen gtt entries counting. However,
541 * 4KB of the stolen memory doesn't get mapped to the GTT.
542 */
543 size = 4;
Eric Anholtc41e0de2006-12-19 12:57:24 -0800544 } else {
545 /* On previous hardware, the GTT size was just what was
546 * required to map the aperture.
547 */
548 size = agp_bridge->driver->fetch_size() + 4;
549 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700550
551 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
552 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
553 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
554 case I830_GMCH_GMS_STOLEN_512:
555 gtt_entries = KB(512) - KB(size);
556 break;
557 case I830_GMCH_GMS_STOLEN_1024:
558 gtt_entries = MB(1) - KB(size);
559 break;
560 case I830_GMCH_GMS_STOLEN_8192:
561 gtt_entries = MB(8) - KB(size);
562 break;
563 case I830_GMCH_GMS_LOCAL:
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800564 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
566 MB(ddt[I830_RDRAM_DDT(rdct)]);
567 local = 1;
568 break;
569 default:
570 gtt_entries = 0;
571 break;
572 }
573 } else {
Dave Airliee67aa272007-09-18 22:46:35 -0700574 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700575 case I855_GMCH_GMS_STOLEN_1M:
576 gtt_entries = MB(1) - KB(size);
577 break;
578 case I855_GMCH_GMS_STOLEN_4M:
579 gtt_entries = MB(4) - KB(size);
580 break;
581 case I855_GMCH_GMS_STOLEN_8M:
582 gtt_entries = MB(8) - KB(size);
583 break;
584 case I855_GMCH_GMS_STOLEN_16M:
585 gtt_entries = MB(16) - KB(size);
586 break;
587 case I855_GMCH_GMS_STOLEN_32M:
588 gtt_entries = MB(32) - KB(size);
589 break;
590 case I915_GMCH_GMS_STOLEN_48M:
591 /* Check it's really I915G */
Zhenyu Wang25ce77a2008-06-19 14:17:58 +1000592 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700593 gtt_entries = MB(48) - KB(size);
594 else
595 gtt_entries = 0;
596 break;
597 case I915_GMCH_GMS_STOLEN_64M:
598 /* Check it's really I915G */
Zhenyu Wang25ce77a2008-06-19 14:17:58 +1000599 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700600 gtt_entries = MB(64) - KB(size);
601 else
602 gtt_entries = 0;
Wang Zhenyu874808c62007-06-06 11:16:25 +0800603 break;
604 case G33_GMCH_GMS_STOLEN_128M:
Zhenyu Wang25ce77a2008-06-19 14:17:58 +1000605 if (IS_G33 || IS_I965 || IS_G4X)
Wang Zhenyu874808c62007-06-06 11:16:25 +0800606 gtt_entries = MB(128) - KB(size);
607 else
608 gtt_entries = 0;
609 break;
610 case G33_GMCH_GMS_STOLEN_256M:
Zhenyu Wang25ce77a2008-06-19 14:17:58 +1000611 if (IS_G33 || IS_I965 || IS_G4X)
Wang Zhenyu874808c62007-06-06 11:16:25 +0800612 gtt_entries = MB(256) - KB(size);
613 else
614 gtt_entries = 0;
615 break;
Zhenyu Wang25ce77a2008-06-19 14:17:58 +1000616 case INTEL_GMCH_GMS_STOLEN_96M:
617 if (IS_I965 || IS_G4X)
618 gtt_entries = MB(96) - KB(size);
619 else
620 gtt_entries = 0;
621 break;
622 case INTEL_GMCH_GMS_STOLEN_160M:
623 if (IS_I965 || IS_G4X)
624 gtt_entries = MB(160) - KB(size);
625 else
626 gtt_entries = 0;
627 break;
628 case INTEL_GMCH_GMS_STOLEN_224M:
629 if (IS_I965 || IS_G4X)
630 gtt_entries = MB(224) - KB(size);
631 else
632 gtt_entries = 0;
633 break;
634 case INTEL_GMCH_GMS_STOLEN_352M:
635 if (IS_I965 || IS_G4X)
636 gtt_entries = MB(352) - KB(size);
637 else
638 gtt_entries = 0;
639 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700640 default:
641 gtt_entries = 0;
642 break;
643 }
644 }
Lubomir Rintel9c1e8a42009-03-10 12:55:54 -0700645 if (gtt_entries > 0) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700646 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647 gtt_entries / KB(1), local ? "local" : "stolen");
Lubomir Rintel9c1e8a42009-03-10 12:55:54 -0700648 gtt_entries /= KB(4);
649 } else {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700650 dev_info(&agp_bridge->dev->dev,
651 "no pre-allocated video memory detected\n");
Lubomir Rintel9c1e8a42009-03-10 12:55:54 -0700652 gtt_entries = 0;
653 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700654
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800655 intel_private.gtt_entries = gtt_entries;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700656}
657
Dave Airlie2162e6a2007-11-21 16:36:31 +1000658static void intel_i830_fini_flush(void)
659{
660 kunmap(intel_private.i8xx_page);
661 intel_private.i8xx_flush_page = NULL;
662 unmap_page_from_agp(intel_private.i8xx_page);
Dave Airlie2162e6a2007-11-21 16:36:31 +1000663
664 __free_page(intel_private.i8xx_page);
Dave Airlie4d64dd92008-01-23 15:34:29 +1000665 intel_private.i8xx_page = NULL;
Dave Airlie2162e6a2007-11-21 16:36:31 +1000666}
667
668static void intel_i830_setup_flush(void)
669{
Dave Airlie4d64dd92008-01-23 15:34:29 +1000670 /* return if we've already set the flush mechanism up */
671 if (intel_private.i8xx_page)
672 return;
Dave Airlie2162e6a2007-11-21 16:36:31 +1000673
674 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
Dave Airlief011ae72008-01-25 11:23:04 +1000675 if (!intel_private.i8xx_page)
Dave Airlie2162e6a2007-11-21 16:36:31 +1000676 return;
Dave Airlie2162e6a2007-11-21 16:36:31 +1000677
678 /* make page uncached */
679 map_page_into_agp(intel_private.i8xx_page);
Dave Airlie2162e6a2007-11-21 16:36:31 +1000680
681 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
682 if (!intel_private.i8xx_flush_page)
683 intel_i830_fini_flush();
684}
685
686static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
687{
688 unsigned int *pg = intel_private.i8xx_flush_page;
689 int i;
690
Dave Airlief011ae72008-01-25 11:23:04 +1000691 for (i = 0; i < 256; i += 2)
Dave Airlie2162e6a2007-11-21 16:36:31 +1000692 *(pg + i) = i;
Dave Airlief011ae72008-01-25 11:23:04 +1000693
Dave Airlie2162e6a2007-11-21 16:36:31 +1000694 wmb();
695}
696
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697/* The intel i830 automatically initializes the agp aperture during POST.
698 * Use the memory already set aside for in the GTT.
699 */
700static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
701{
702 int page_order;
703 struct aper_size_info_fixed *size;
704 int num_entries;
705 u32 temp;
706
707 size = agp_bridge->current_size;
708 page_order = size->page_order;
709 num_entries = size->num_entries;
710 agp_bridge->gatt_table_real = NULL;
711
Dave Airlief011ae72008-01-25 11:23:04 +1000712 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700713 temp &= 0xfff80000;
714
Dave Airlief011ae72008-01-25 11:23:04 +1000715 intel_private.registers = ioremap(temp, 128 * 4096);
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800716 if (!intel_private.registers)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700717 return -ENOMEM;
718
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800719 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720 global_cache_flush(); /* FIXME: ?? */
721
722 /* we have to call this as early as possible after the MMIO base address is known */
723 intel_i830_init_gtt_entries();
724
725 agp_bridge->gatt_table = NULL;
726
727 agp_bridge->gatt_bus_addr = temp;
728
729 return 0;
730}
731
732/* Return the gatt table to a sane state. Use the top of stolen
733 * memory for the GTT.
734 */
735static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
736{
737 return 0;
738}
739
740static int intel_i830_fetch_size(void)
741{
742 u16 gmch_ctrl;
743 struct aper_size_info_fixed *values;
744
745 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
746
747 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
748 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
749 /* 855GM/852GM/865G has 128MB aperture size */
750 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
751 agp_bridge->aperture_size_idx = 0;
752 return values[0].size;
753 }
754
Dave Airlief011ae72008-01-25 11:23:04 +1000755 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700756
757 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
758 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
759 agp_bridge->aperture_size_idx = 0;
760 return values[0].size;
761 } else {
762 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
763 agp_bridge->aperture_size_idx = 1;
764 return values[1].size;
765 }
766
767 return 0;
768}
769
770static int intel_i830_configure(void)
771{
772 struct aper_size_info_fixed *current_size;
773 u32 temp;
774 u16 gmch_ctrl;
775 int i;
776
777 current_size = A_SIZE_FIX(agp_bridge->current_size);
778
Dave Airlief011ae72008-01-25 11:23:04 +1000779 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
781
Dave Airlief011ae72008-01-25 11:23:04 +1000782 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700783 gmch_ctrl |= I830_GMCH_ENABLED;
Dave Airlief011ae72008-01-25 11:23:04 +1000784 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700785
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800786 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
787 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700788
789 if (agp_bridge->driver->needs_scratch_page) {
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800790 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
791 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792 }
Keith Packard44d49442008-10-14 17:18:45 -0700793 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794 }
795
796 global_cache_flush();
Dave Airlie2162e6a2007-11-21 16:36:31 +1000797
798 intel_i830_setup_flush();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700799 return 0;
800}
801
802static void intel_i830_cleanup(void)
803{
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800804 iounmap(intel_private.registers);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700805}
806
Dave Airlief011ae72008-01-25 11:23:04 +1000807static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
808 int type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700809{
Dave Airlief011ae72008-01-25 11:23:04 +1000810 int i, j, num_entries;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700811 void *temp;
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100812 int ret = -EINVAL;
813 int mask_type;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100815 if (mem->page_count == 0)
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100816 goto out;
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100817
Linus Torvalds1da177e2005-04-16 15:20:36 -0700818 temp = agp_bridge->current_size;
819 num_entries = A_SIZE_FIX(temp)->num_entries;
820
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800821 if (pg_start < intel_private.gtt_entries) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700822 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
823 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
824 pg_start, intel_private.gtt_entries);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700826 dev_info(&intel_private.pcidev->dev,
827 "trying to insert into local/stolen memory\n");
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100828 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829 }
830
831 if ((pg_start + mem->page_count) > num_entries)
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100832 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700833
834 /* The i830 can't check the GTT for entries since its read only,
835 * depend on the caller to make the correct offset decisions.
836 */
837
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100838 if (type != mem->type)
839 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700840
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100841 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
842
843 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
844 mask_type != INTEL_AGP_CACHED_MEMORY)
845 goto out_err;
846
847 if (!mem->is_flushed)
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100848 global_cache_flush();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700849
850 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
851 writel(agp_bridge->driver->mask_memory(agp_bridge,
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100852 mem->memory[i], mask_type),
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800853 intel_private.registers+I810_PTE_BASE+(j*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700854 }
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800855 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700856 agp_bridge->driver->tlb_flush(mem);
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100857
858out:
859 ret = 0;
860out_err:
Dave Airlie9516b032008-06-19 10:42:17 +1000861 mem->is_flushed = true;
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100862 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700863}
864
Dave Airlief011ae72008-01-25 11:23:04 +1000865static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
866 int type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700867{
868 int i;
869
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100870 if (mem->page_count == 0)
871 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700872
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800873 if (pg_start < intel_private.gtt_entries) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700874 dev_info(&intel_private.pcidev->dev,
875 "trying to disable local/stolen memory\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876 return -EINVAL;
877 }
878
879 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800880 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700881 }
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800882 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700883
Linus Torvalds1da177e2005-04-16 15:20:36 -0700884 agp_bridge->driver->tlb_flush(mem);
885 return 0;
886}
887
Dave Airlief011ae72008-01-25 11:23:04 +1000888static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700889{
890 if (type == AGP_PHYS_MEMORY)
891 return alloc_agpphysmem_i8xx(pg_count, type);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700892 /* always return NULL for other allocation types for now */
893 return NULL;
894}
895
Dave Airlie6c00a612007-10-29 18:06:10 +1000896static int intel_alloc_chipset_flush_resource(void)
897{
898 int ret;
899 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
900 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
901 pcibios_align_resource, agp_bridge->dev);
Dave Airlie6c00a612007-10-29 18:06:10 +1000902
Dave Airlie2162e6a2007-11-21 16:36:31 +1000903 return ret;
Dave Airlie6c00a612007-10-29 18:06:10 +1000904}
905
906static void intel_i915_setup_chipset_flush(void)
907{
908 int ret;
909 u32 temp;
910
911 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
912 if (!(temp & 0x1)) {
913 intel_alloc_chipset_flush_resource();
Dave Airlie4d64dd92008-01-23 15:34:29 +1000914 intel_private.resource_valid = 1;
Dave Airlie6c00a612007-10-29 18:06:10 +1000915 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
916 } else {
917 temp &= ~1;
918
Dave Airlie4d64dd92008-01-23 15:34:29 +1000919 intel_private.resource_valid = 1;
Dave Airlie6c00a612007-10-29 18:06:10 +1000920 intel_private.ifp_resource.start = temp;
921 intel_private.ifp_resource.end = temp + PAGE_SIZE;
922 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
Dave Airlie4d64dd92008-01-23 15:34:29 +1000923 /* some BIOSes reserve this area in a pnp some don't */
924 if (ret)
925 intel_private.resource_valid = 0;
Dave Airlie6c00a612007-10-29 18:06:10 +1000926 }
927}
928
929static void intel_i965_g33_setup_chipset_flush(void)
930{
931 u32 temp_hi, temp_lo;
932 int ret;
933
934 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
935 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
936
937 if (!(temp_lo & 0x1)) {
938
939 intel_alloc_chipset_flush_resource();
940
Dave Airlie4d64dd92008-01-23 15:34:29 +1000941 intel_private.resource_valid = 1;
Andrew Morton1fa4db72007-11-29 10:00:48 +1000942 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
943 upper_32_bits(intel_private.ifp_resource.start));
Dave Airlie6c00a612007-10-29 18:06:10 +1000944 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
Dave Airlie6c00a612007-10-29 18:06:10 +1000945 } else {
946 u64 l64;
Dave Airlief011ae72008-01-25 11:23:04 +1000947
Dave Airlie6c00a612007-10-29 18:06:10 +1000948 temp_lo &= ~0x1;
949 l64 = ((u64)temp_hi << 32) | temp_lo;
950
Dave Airlie4d64dd92008-01-23 15:34:29 +1000951 intel_private.resource_valid = 1;
Dave Airlie6c00a612007-10-29 18:06:10 +1000952 intel_private.ifp_resource.start = l64;
953 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
954 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
Dave Airlie4d64dd92008-01-23 15:34:29 +1000955 /* some BIOSes reserve this area in a pnp some don't */
956 if (ret)
957 intel_private.resource_valid = 0;
Dave Airlie6c00a612007-10-29 18:06:10 +1000958 }
959}
960
Dave Airlie2162e6a2007-11-21 16:36:31 +1000961static void intel_i9xx_setup_flush(void)
962{
Dave Airlie4d64dd92008-01-23 15:34:29 +1000963 /* return if already configured */
964 if (intel_private.ifp_resource.start)
965 return;
Dave Airlie2162e6a2007-11-21 16:36:31 +1000966
Dave Airlie4d64dd92008-01-23 15:34:29 +1000967 /* setup a resource for this object */
Dave Airlie2162e6a2007-11-21 16:36:31 +1000968 intel_private.ifp_resource.name = "Intel Flush Page";
969 intel_private.ifp_resource.flags = IORESOURCE_MEM;
970
971 /* Setup chipset flush for 915 */
Zhenyu Wang7d15ddf2008-06-20 11:48:06 +1000972 if (IS_I965 || IS_G33 || IS_G4X) {
Dave Airlie2162e6a2007-11-21 16:36:31 +1000973 intel_i965_g33_setup_chipset_flush();
974 } else {
975 intel_i915_setup_chipset_flush();
976 }
977
978 if (intel_private.ifp_resource.start) {
979 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
980 if (!intel_private.i9xx_flush_page)
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700981 dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
Dave Airlie2162e6a2007-11-21 16:36:31 +1000982 }
983}
984
Linus Torvalds1da177e2005-04-16 15:20:36 -0700985static int intel_i915_configure(void)
986{
987 struct aper_size_info_fixed *current_size;
988 u32 temp;
989 u16 gmch_ctrl;
990 int i;
991
992 current_size = A_SIZE_FIX(agp_bridge->current_size);
993
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800994 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700995
996 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
997
Dave Airlief011ae72008-01-25 11:23:04 +1000998 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700999 gmch_ctrl |= I830_GMCH_ENABLED;
Dave Airlief011ae72008-01-25 11:23:04 +10001000 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001001
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001002 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1003 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001004
1005 if (agp_bridge->driver->needs_scratch_page) {
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001006 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
1007 writel(agp_bridge->scratch_page, intel_private.gtt+i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001008 }
Keith Packard44d49442008-10-14 17:18:45 -07001009 readl(intel_private.gtt+i-1); /* PCI Posting. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001010 }
1011
1012 global_cache_flush();
Dave Airlie6c00a612007-10-29 18:06:10 +10001013
Dave Airlie2162e6a2007-11-21 16:36:31 +10001014 intel_i9xx_setup_flush();
Dave Airlief011ae72008-01-25 11:23:04 +10001015
Linus Torvalds1da177e2005-04-16 15:20:36 -07001016 return 0;
1017}
1018
1019static void intel_i915_cleanup(void)
1020{
Dave Airlie2162e6a2007-11-21 16:36:31 +10001021 if (intel_private.i9xx_flush_page)
1022 iounmap(intel_private.i9xx_flush_page);
Dave Airlie4d64dd92008-01-23 15:34:29 +10001023 if (intel_private.resource_valid)
1024 release_resource(&intel_private.ifp_resource);
1025 intel_private.ifp_resource.start = 0;
1026 intel_private.resource_valid = 0;
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001027 iounmap(intel_private.gtt);
1028 iounmap(intel_private.registers);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001029}
1030
Dave Airlie6c00a612007-10-29 18:06:10 +10001031static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1032{
Dave Airlie2162e6a2007-11-21 16:36:31 +10001033 if (intel_private.i9xx_flush_page)
1034 writel(1, intel_private.i9xx_flush_page);
Dave Airlie6c00a612007-10-29 18:06:10 +10001035}
1036
Dave Airlief011ae72008-01-25 11:23:04 +10001037static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1038 int type)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001039{
Dave Airlief011ae72008-01-25 11:23:04 +10001040 int i, j, num_entries;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001041 void *temp;
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001042 int ret = -EINVAL;
1043 int mask_type;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001044
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +01001045 if (mem->page_count == 0)
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001046 goto out;
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +01001047
Linus Torvalds1da177e2005-04-16 15:20:36 -07001048 temp = agp_bridge->current_size;
1049 num_entries = A_SIZE_FIX(temp)->num_entries;
1050
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001051 if (pg_start < intel_private.gtt_entries) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07001052 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1053 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1054 pg_start, intel_private.gtt_entries);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001055
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07001056 dev_info(&intel_private.pcidev->dev,
1057 "trying to insert into local/stolen memory\n");
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001058 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001059 }
1060
1061 if ((pg_start + mem->page_count) > num_entries)
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001062 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001063
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001064 /* The i915 can't check the GTT for entries since its read only,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001065 * depend on the caller to make the correct offset decisions.
1066 */
1067
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001068 if (type != mem->type)
1069 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001070
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001071 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1072
1073 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1074 mask_type != INTEL_AGP_CACHED_MEMORY)
1075 goto out_err;
1076
1077 if (!mem->is_flushed)
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +01001078 global_cache_flush();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001079
1080 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1081 writel(agp_bridge->driver->mask_memory(agp_bridge,
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001082 mem->memory[i], mask_type), intel_private.gtt+j);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001083 }
1084
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001085 readl(intel_private.gtt+j-1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001086 agp_bridge->driver->tlb_flush(mem);
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001087
1088 out:
1089 ret = 0;
1090 out_err:
Dave Airlie9516b032008-06-19 10:42:17 +10001091 mem->is_flushed = true;
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001092 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001093}
1094
Dave Airlief011ae72008-01-25 11:23:04 +10001095static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1096 int type)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001097{
1098 int i;
1099
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +01001100 if (mem->page_count == 0)
1101 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001102
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001103 if (pg_start < intel_private.gtt_entries) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07001104 dev_info(&intel_private.pcidev->dev,
1105 "trying to disable local/stolen memory\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001106 return -EINVAL;
1107 }
1108
Dave Airlief011ae72008-01-25 11:23:04 +10001109 for (i = pg_start; i < (mem->page_count + pg_start); i++)
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001110 writel(agp_bridge->scratch_page, intel_private.gtt+i);
Dave Airlief011ae72008-01-25 11:23:04 +10001111
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001112 readl(intel_private.gtt+i-1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113
Linus Torvalds1da177e2005-04-16 15:20:36 -07001114 agp_bridge->driver->tlb_flush(mem);
1115 return 0;
1116}
1117
Eric Anholtc41e0de2006-12-19 12:57:24 -08001118/* Return the aperture size by just checking the resource length. The effect
1119 * described in the spec of the MSAC registers is just changing of the
1120 * resource size.
1121 */
1122static int intel_i9xx_fetch_size(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001123{
Ahmed S. Darwish1eaf1222007-02-06 18:08:28 +02001124 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
Eric Anholtc41e0de2006-12-19 12:57:24 -08001125 int aper_size; /* size in megabytes */
1126 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001127
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001128 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001129
Eric Anholtc41e0de2006-12-19 12:57:24 -08001130 for (i = 0; i < num_sizes; i++) {
1131 if (aper_size == intel_i830_sizes[i].size) {
1132 agp_bridge->current_size = intel_i830_sizes + i;
1133 agp_bridge->previous_size = agp_bridge->current_size;
1134 return aper_size;
1135 }
1136 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001137
Eric Anholtc41e0de2006-12-19 12:57:24 -08001138 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001139}
1140
1141/* The intel i915 automatically initializes the agp aperture during POST.
1142 * Use the memory already set aside for in the GTT.
1143 */
1144static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1145{
1146 int page_order;
1147 struct aper_size_info_fixed *size;
1148 int num_entries;
1149 u32 temp, temp2;
Zhenyu Wang47406222007-09-11 15:23:58 -07001150 int gtt_map_size = 256 * 1024;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001151
1152 size = agp_bridge->current_size;
1153 page_order = size->page_order;
1154 num_entries = size->num_entries;
1155 agp_bridge->gatt_table_real = NULL;
1156
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001157 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
Dave Airlief011ae72008-01-25 11:23:04 +10001158 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001159
Zhenyu Wang47406222007-09-11 15:23:58 -07001160 if (IS_G33)
1161 gtt_map_size = 1024 * 1024; /* 1M on G33 */
1162 intel_private.gtt = ioremap(temp2, gtt_map_size);
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001163 if (!intel_private.gtt)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001164 return -ENOMEM;
1165
1166 temp &= 0xfff80000;
1167
Dave Airlief011ae72008-01-25 11:23:04 +10001168 intel_private.registers = ioremap(temp, 128 * 4096);
Scott Thompson5bdbc7d2007-08-25 18:14:00 +10001169 if (!intel_private.registers) {
1170 iounmap(intel_private.gtt);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001171 return -ENOMEM;
Scott Thompson5bdbc7d2007-08-25 18:14:00 +10001172 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001173
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001174 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001175 global_cache_flush(); /* FIXME: ? */
1176
1177 /* we have to call this as early as possible after the MMIO base address is known */
1178 intel_i830_init_gtt_entries();
1179
1180 agp_bridge->gatt_table = NULL;
1181
1182 agp_bridge->gatt_bus_addr = temp;
1183
1184 return 0;
1185}
Linus Torvalds7d915a32006-11-22 09:37:54 -08001186
1187/*
1188 * The i965 supports 36-bit physical addresses, but to keep
1189 * the format of the GTT the same, the bits that don't fit
1190 * in a 32-bit word are shifted down to bits 4..7.
1191 *
1192 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1193 * is always zero on 32-bit architectures, so no need to make
1194 * this conditional.
1195 */
1196static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1197 unsigned long addr, int type)
1198{
1199 /* Shift high bits down */
1200 addr |= (addr >> 28) & 0xf0;
1201
1202 /* Type checking must be done elsewhere */
1203 return addr | bridge->driver->masks[type].mask;
1204}
1205
Zhenyu Wang25ce77a2008-06-19 14:17:58 +10001206static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1207{
1208 switch (agp_bridge->dev->device) {
Zhenyu Wang99d32bd2008-07-30 12:26:50 -07001209 case PCI_DEVICE_ID_INTEL_GM45_HB:
Zhenyu Wang25ce77a2008-06-19 14:17:58 +10001210 case PCI_DEVICE_ID_INTEL_IGD_E_HB:
1211 case PCI_DEVICE_ID_INTEL_Q45_HB:
1212 case PCI_DEVICE_ID_INTEL_G45_HB:
Zhenyu Wanga50ccc62008-11-17 14:39:00 +08001213 case PCI_DEVICE_ID_INTEL_G41_HB:
Zhenyu Wang25ce77a2008-06-19 14:17:58 +10001214 *gtt_offset = *gtt_size = MB(2);
1215 break;
1216 default:
1217 *gtt_offset = *gtt_size = KB(512);
1218 }
1219}
1220
Eric Anholt65c25aa2006-09-06 11:57:18 -04001221/* The intel i965 automatically initializes the agp aperture during POST.
Eric Anholtc41e0de2006-12-19 12:57:24 -08001222 * Use the memory already set aside for in the GTT.
1223 */
Eric Anholt65c25aa2006-09-06 11:57:18 -04001224static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1225{
Dave Airlie62c96b92008-06-19 14:27:53 +10001226 int page_order;
1227 struct aper_size_info_fixed *size;
1228 int num_entries;
1229 u32 temp;
1230 int gtt_offset, gtt_size;
Eric Anholt65c25aa2006-09-06 11:57:18 -04001231
Dave Airlie62c96b92008-06-19 14:27:53 +10001232 size = agp_bridge->current_size;
1233 page_order = size->page_order;
1234 num_entries = size->num_entries;
1235 agp_bridge->gatt_table_real = NULL;
Eric Anholt65c25aa2006-09-06 11:57:18 -04001236
Dave Airlie62c96b92008-06-19 14:27:53 +10001237 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
Eric Anholt65c25aa2006-09-06 11:57:18 -04001238
Dave Airlie62c96b92008-06-19 14:27:53 +10001239 temp &= 0xfff00000;
Eric Anholt65c25aa2006-09-06 11:57:18 -04001240
Zhenyu Wang25ce77a2008-06-19 14:17:58 +10001241 intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
Eric Anholt65c25aa2006-09-06 11:57:18 -04001242
Dave Airlie62c96b92008-06-19 14:27:53 +10001243 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
Eric Anholt65c25aa2006-09-06 11:57:18 -04001244
Dave Airlie62c96b92008-06-19 14:27:53 +10001245 if (!intel_private.gtt)
1246 return -ENOMEM;
Zhenyu Wang4e8b6e22008-01-23 14:54:37 +10001247
Dave Airlie62c96b92008-06-19 14:27:53 +10001248 intel_private.registers = ioremap(temp, 128 * 4096);
1249 if (!intel_private.registers) {
Scott Thompson5bdbc7d2007-08-25 18:14:00 +10001250 iounmap(intel_private.gtt);
1251 return -ENOMEM;
1252 }
Eric Anholt65c25aa2006-09-06 11:57:18 -04001253
Dave Airlie62c96b92008-06-19 14:27:53 +10001254 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1255 global_cache_flush(); /* FIXME: ? */
Eric Anholt65c25aa2006-09-06 11:57:18 -04001256
Dave Airlie62c96b92008-06-19 14:27:53 +10001257 /* we have to call this as early as possible after the MMIO base address is known */
1258 intel_i830_init_gtt_entries();
Eric Anholt65c25aa2006-09-06 11:57:18 -04001259
Dave Airlie62c96b92008-06-19 14:27:53 +10001260 agp_bridge->gatt_table = NULL;
Eric Anholt65c25aa2006-09-06 11:57:18 -04001261
Dave Airlie62c96b92008-06-19 14:27:53 +10001262 agp_bridge->gatt_bus_addr = temp;
Eric Anholt65c25aa2006-09-06 11:57:18 -04001263
Dave Airlie62c96b92008-06-19 14:27:53 +10001264 return 0;
Eric Anholt65c25aa2006-09-06 11:57:18 -04001265}
1266
Linus Torvalds1da177e2005-04-16 15:20:36 -07001267
1268static int intel_fetch_size(void)
1269{
1270 int i;
1271 u16 temp;
1272 struct aper_size_info_16 *values;
1273
1274 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1275 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1276
1277 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1278 if (temp == values[i].size_value) {
1279 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1280 agp_bridge->aperture_size_idx = i;
1281 return values[i].size;
1282 }
1283 }
1284
1285 return 0;
1286}
1287
1288static int __intel_8xx_fetch_size(u8 temp)
1289{
1290 int i;
1291 struct aper_size_info_8 *values;
1292
1293 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1294
1295 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1296 if (temp == values[i].size_value) {
1297 agp_bridge->previous_size =
1298 agp_bridge->current_size = (void *) (values + i);
1299 agp_bridge->aperture_size_idx = i;
1300 return values[i].size;
1301 }
1302 }
1303 return 0;
1304}
1305
1306static int intel_8xx_fetch_size(void)
1307{
1308 u8 temp;
1309
1310 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1311 return __intel_8xx_fetch_size(temp);
1312}
1313
1314static int intel_815_fetch_size(void)
1315{
1316 u8 temp;
1317
1318 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1319 * one non-reserved bit, so mask the others out ... */
1320 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1321 temp &= (1 << 3);
1322
1323 return __intel_8xx_fetch_size(temp);
1324}
1325
1326static void intel_tlbflush(struct agp_memory *mem)
1327{
1328 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1329 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1330}
1331
1332
1333static void intel_8xx_tlbflush(struct agp_memory *mem)
1334{
1335 u32 temp;
1336 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1337 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1338 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1339 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1340}
1341
1342
1343static void intel_cleanup(void)
1344{
1345 u16 temp;
1346 struct aper_size_info_16 *previous_size;
1347
1348 previous_size = A_SIZE_16(agp_bridge->previous_size);
1349 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1350 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1351 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1352}
1353
1354
1355static void intel_8xx_cleanup(void)
1356{
1357 u16 temp;
1358 struct aper_size_info_8 *previous_size;
1359
1360 previous_size = A_SIZE_8(agp_bridge->previous_size);
1361 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1362 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1363 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1364}
1365
1366
1367static int intel_configure(void)
1368{
1369 u32 temp;
1370 u16 temp2;
1371 struct aper_size_info_16 *current_size;
1372
1373 current_size = A_SIZE_16(agp_bridge->current_size);
1374
1375 /* aperture size */
1376 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1377
1378 /* address to map to */
1379 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1380 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1381
1382 /* attbase - aperture base */
1383 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1384
1385 /* agpctrl */
1386 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1387
1388 /* paccfg/nbxcfg */
1389 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1390 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1391 (temp2 & ~(1 << 10)) | (1 << 9));
1392 /* clear any possible error conditions */
1393 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1394 return 0;
1395}
1396
1397static int intel_815_configure(void)
1398{
1399 u32 temp, addr;
1400 u8 temp2;
1401 struct aper_size_info_8 *current_size;
1402
1403 /* attbase - aperture base */
1404 /* the Intel 815 chipset spec. says that bits 29-31 in the
1405 * ATTBASE register are reserved -> try not to write them */
1406 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07001407 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001408 return -EINVAL;
1409 }
1410
1411 current_size = A_SIZE_8(agp_bridge->current_size);
1412
1413 /* aperture size */
1414 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1415 current_size->size_value);
1416
1417 /* address to map to */
1418 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1419 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1420
1421 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1422 addr &= INTEL_815_ATTBASE_MASK;
1423 addr |= agp_bridge->gatt_bus_addr;
1424 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1425
1426 /* agpctrl */
1427 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1428
1429 /* apcont */
1430 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1431 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1432
1433 /* clear any possible error conditions */
1434 /* Oddness : this chipset seems to have no ERRSTS register ! */
1435 return 0;
1436}
1437
1438static void intel_820_tlbflush(struct agp_memory *mem)
1439{
1440 return;
1441}
1442
1443static void intel_820_cleanup(void)
1444{
1445 u8 temp;
1446 struct aper_size_info_8 *previous_size;
1447
1448 previous_size = A_SIZE_8(agp_bridge->previous_size);
1449 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1450 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1451 temp & ~(1 << 1));
1452 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1453 previous_size->size_value);
1454}
1455
1456
1457static int intel_820_configure(void)
1458{
1459 u32 temp;
1460 u8 temp2;
1461 struct aper_size_info_8 *current_size;
1462
1463 current_size = A_SIZE_8(agp_bridge->current_size);
1464
1465 /* aperture size */
1466 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1467
1468 /* address to map to */
1469 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1470 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1471
1472 /* attbase - aperture base */
1473 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1474
1475 /* agpctrl */
1476 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1477
1478 /* global enable aperture access */
1479 /* This flag is not accessed through MCHCFG register as in */
1480 /* i850 chipset. */
1481 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1482 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1483 /* clear any possible AGP-related error conditions */
1484 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1485 return 0;
1486}
1487
1488static int intel_840_configure(void)
1489{
1490 u32 temp;
1491 u16 temp2;
1492 struct aper_size_info_8 *current_size;
1493
1494 current_size = A_SIZE_8(agp_bridge->current_size);
1495
1496 /* aperture size */
1497 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1498
1499 /* address to map to */
1500 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1501 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1502
1503 /* attbase - aperture base */
1504 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1505
1506 /* agpctrl */
1507 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1508
1509 /* mcgcfg */
1510 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1511 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1512 /* clear any possible error conditions */
1513 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1514 return 0;
1515}
1516
1517static int intel_845_configure(void)
1518{
1519 u32 temp;
1520 u8 temp2;
1521 struct aper_size_info_8 *current_size;
1522
1523 current_size = A_SIZE_8(agp_bridge->current_size);
1524
1525 /* aperture size */
1526 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1527
Matthew Garrettb0825482005-07-29 14:03:39 -07001528 if (agp_bridge->apbase_config != 0) {
1529 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1530 agp_bridge->apbase_config);
1531 } else {
1532 /* address to map to */
1533 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1534 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1535 agp_bridge->apbase_config = temp;
1536 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001537
1538 /* attbase - aperture base */
1539 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1540
1541 /* agpctrl */
1542 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1543
1544 /* agpm */
1545 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1546 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1547 /* clear any possible error conditions */
1548 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
Dave Airlie2162e6a2007-11-21 16:36:31 +10001549
1550 intel_i830_setup_flush();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001551 return 0;
1552}
1553
1554static int intel_850_configure(void)
1555{
1556 u32 temp;
1557 u16 temp2;
1558 struct aper_size_info_8 *current_size;
1559
1560 current_size = A_SIZE_8(agp_bridge->current_size);
1561
1562 /* aperture size */
1563 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1564
1565 /* address to map to */
1566 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1567 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1568
1569 /* attbase - aperture base */
1570 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1571
1572 /* agpctrl */
1573 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1574
1575 /* mcgcfg */
1576 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1577 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1578 /* clear any possible AGP-related error conditions */
1579 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1580 return 0;
1581}
1582
1583static int intel_860_configure(void)
1584{
1585 u32 temp;
1586 u16 temp2;
1587 struct aper_size_info_8 *current_size;
1588
1589 current_size = A_SIZE_8(agp_bridge->current_size);
1590
1591 /* aperture size */
1592 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1593
1594 /* address to map to */
1595 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1596 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1597
1598 /* attbase - aperture base */
1599 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1600
1601 /* agpctrl */
1602 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1603
1604 /* mcgcfg */
1605 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1606 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1607 /* clear any possible AGP-related error conditions */
1608 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1609 return 0;
1610}
1611
1612static int intel_830mp_configure(void)
1613{
1614 u32 temp;
1615 u16 temp2;
1616 struct aper_size_info_8 *current_size;
1617
1618 current_size = A_SIZE_8(agp_bridge->current_size);
1619
1620 /* aperture size */
1621 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1622
1623 /* address to map to */
1624 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1625 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1626
1627 /* attbase - aperture base */
1628 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1629
1630 /* agpctrl */
1631 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1632
1633 /* gmch */
1634 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1635 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1636 /* clear any possible AGP-related error conditions */
1637 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1638 return 0;
1639}
1640
1641static int intel_7505_configure(void)
1642{
1643 u32 temp;
1644 u16 temp2;
1645 struct aper_size_info_8 *current_size;
1646
1647 current_size = A_SIZE_8(agp_bridge->current_size);
1648
1649 /* aperture size */
1650 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1651
1652 /* address to map to */
1653 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1654 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1655
1656 /* attbase - aperture base */
1657 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1658
1659 /* agpctrl */
1660 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1661
1662 /* mchcfg */
1663 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1664 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1665
1666 return 0;
1667}
1668
1669/* Setup function */
Dave Jonese5524f32007-02-22 18:41:28 -05001670static const struct gatt_mask intel_generic_masks[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001671{
1672 {.mask = 0x00000017, .type = 0}
1673};
1674
Dave Jonese5524f32007-02-22 18:41:28 -05001675static const struct aper_size_info_8 intel_815_sizes[2] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001676{
1677 {64, 16384, 4, 0},
1678 {32, 8192, 3, 8},
1679};
1680
Dave Jonese5524f32007-02-22 18:41:28 -05001681static const struct aper_size_info_8 intel_8xx_sizes[7] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001682{
1683 {256, 65536, 6, 0},
1684 {128, 32768, 5, 32},
1685 {64, 16384, 4, 48},
1686 {32, 8192, 3, 56},
1687 {16, 4096, 2, 60},
1688 {8, 2048, 1, 62},
1689 {4, 1024, 0, 63}
1690};
1691
Dave Jonese5524f32007-02-22 18:41:28 -05001692static const struct aper_size_info_16 intel_generic_sizes[7] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001693{
1694 {256, 65536, 6, 0},
1695 {128, 32768, 5, 32},
1696 {64, 16384, 4, 48},
1697 {32, 8192, 3, 56},
1698 {16, 4096, 2, 60},
1699 {8, 2048, 1, 62},
1700 {4, 1024, 0, 63}
1701};
1702
Dave Jonese5524f32007-02-22 18:41:28 -05001703static const struct aper_size_info_8 intel_830mp_sizes[4] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001704{
1705 {256, 65536, 6, 0},
1706 {128, 32768, 5, 32},
1707 {64, 16384, 4, 48},
1708 {32, 8192, 3, 56}
1709};
1710
Dave Jonese5524f32007-02-22 18:41:28 -05001711static const struct agp_bridge_driver intel_generic_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001712 .owner = THIS_MODULE,
1713 .aperture_sizes = intel_generic_sizes,
1714 .size_type = U16_APER_SIZE,
1715 .num_aperture_sizes = 7,
1716 .configure = intel_configure,
1717 .fetch_size = intel_fetch_size,
1718 .cleanup = intel_cleanup,
1719 .tlb_flush = intel_tlbflush,
1720 .mask_memory = agp_generic_mask_memory,
1721 .masks = intel_generic_masks,
1722 .agp_enable = agp_generic_enable,
1723 .cache_flush = global_cache_flush,
1724 .create_gatt_table = agp_generic_create_gatt_table,
1725 .free_gatt_table = agp_generic_free_gatt_table,
1726 .insert_memory = agp_generic_insert_memory,
1727 .remove_memory = agp_generic_remove_memory,
1728 .alloc_by_type = agp_generic_alloc_by_type,
1729 .free_by_type = agp_generic_free_by_type,
1730 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001731 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001732 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001733 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001734 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001735};
1736
Dave Jonese5524f32007-02-22 18:41:28 -05001737static const struct agp_bridge_driver intel_810_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001738 .owner = THIS_MODULE,
1739 .aperture_sizes = intel_i810_sizes,
1740 .size_type = FIXED_APER_SIZE,
1741 .num_aperture_sizes = 2,
Joe Perchesc7258012008-03-26 14:10:02 -07001742 .needs_scratch_page = true,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001743 .configure = intel_i810_configure,
1744 .fetch_size = intel_i810_fetch_size,
1745 .cleanup = intel_i810_cleanup,
1746 .tlb_flush = intel_i810_tlbflush,
1747 .mask_memory = intel_i810_mask_memory,
1748 .masks = intel_i810_masks,
1749 .agp_enable = intel_i810_agp_enable,
1750 .cache_flush = global_cache_flush,
1751 .create_gatt_table = agp_generic_create_gatt_table,
1752 .free_gatt_table = agp_generic_free_gatt_table,
1753 .insert_memory = intel_i810_insert_entries,
1754 .remove_memory = intel_i810_remove_entries,
1755 .alloc_by_type = intel_i810_alloc_by_type,
1756 .free_by_type = intel_i810_free_by_type,
1757 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001758 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001759 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001760 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001761 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001762};
1763
Dave Jonese5524f32007-02-22 18:41:28 -05001764static const struct agp_bridge_driver intel_815_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001765 .owner = THIS_MODULE,
1766 .aperture_sizes = intel_815_sizes,
1767 .size_type = U8_APER_SIZE,
1768 .num_aperture_sizes = 2,
1769 .configure = intel_815_configure,
1770 .fetch_size = intel_815_fetch_size,
1771 .cleanup = intel_8xx_cleanup,
1772 .tlb_flush = intel_8xx_tlbflush,
1773 .mask_memory = agp_generic_mask_memory,
1774 .masks = intel_generic_masks,
1775 .agp_enable = agp_generic_enable,
1776 .cache_flush = global_cache_flush,
1777 .create_gatt_table = agp_generic_create_gatt_table,
1778 .free_gatt_table = agp_generic_free_gatt_table,
1779 .insert_memory = agp_generic_insert_memory,
1780 .remove_memory = agp_generic_remove_memory,
1781 .alloc_by_type = agp_generic_alloc_by_type,
1782 .free_by_type = agp_generic_free_by_type,
1783 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001784 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001785 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001786 .agp_destroy_pages = agp_generic_destroy_pages,
Dave Airlie62c96b92008-06-19 14:27:53 +10001787 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001788};
1789
Dave Jonese5524f32007-02-22 18:41:28 -05001790static const struct agp_bridge_driver intel_830_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001791 .owner = THIS_MODULE,
1792 .aperture_sizes = intel_i830_sizes,
1793 .size_type = FIXED_APER_SIZE,
Dave Jonesc14635e2006-09-06 11:59:35 -04001794 .num_aperture_sizes = 4,
Joe Perchesc7258012008-03-26 14:10:02 -07001795 .needs_scratch_page = true,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001796 .configure = intel_i830_configure,
1797 .fetch_size = intel_i830_fetch_size,
1798 .cleanup = intel_i830_cleanup,
1799 .tlb_flush = intel_i810_tlbflush,
1800 .mask_memory = intel_i810_mask_memory,
1801 .masks = intel_i810_masks,
1802 .agp_enable = intel_i810_agp_enable,
1803 .cache_flush = global_cache_flush,
1804 .create_gatt_table = intel_i830_create_gatt_table,
1805 .free_gatt_table = intel_i830_free_gatt_table,
1806 .insert_memory = intel_i830_insert_entries,
1807 .remove_memory = intel_i830_remove_entries,
1808 .alloc_by_type = intel_i830_alloc_by_type,
1809 .free_by_type = intel_i810_free_by_type,
1810 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001811 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001812 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001813 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001814 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
Dave Airlie2162e6a2007-11-21 16:36:31 +10001815 .chipset_flush = intel_i830_chipset_flush,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001816};
1817
Dave Jonese5524f32007-02-22 18:41:28 -05001818static const struct agp_bridge_driver intel_820_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001819 .owner = THIS_MODULE,
1820 .aperture_sizes = intel_8xx_sizes,
1821 .size_type = U8_APER_SIZE,
1822 .num_aperture_sizes = 7,
1823 .configure = intel_820_configure,
1824 .fetch_size = intel_8xx_fetch_size,
1825 .cleanup = intel_820_cleanup,
1826 .tlb_flush = intel_820_tlbflush,
1827 .mask_memory = agp_generic_mask_memory,
1828 .masks = intel_generic_masks,
1829 .agp_enable = agp_generic_enable,
1830 .cache_flush = global_cache_flush,
1831 .create_gatt_table = agp_generic_create_gatt_table,
1832 .free_gatt_table = agp_generic_free_gatt_table,
1833 .insert_memory = agp_generic_insert_memory,
1834 .remove_memory = agp_generic_remove_memory,
1835 .alloc_by_type = agp_generic_alloc_by_type,
1836 .free_by_type = agp_generic_free_by_type,
1837 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001838 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001839 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001840 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001841 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001842};
1843
Dave Jonese5524f32007-02-22 18:41:28 -05001844static const struct agp_bridge_driver intel_830mp_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001845 .owner = THIS_MODULE,
1846 .aperture_sizes = intel_830mp_sizes,
1847 .size_type = U8_APER_SIZE,
1848 .num_aperture_sizes = 4,
1849 .configure = intel_830mp_configure,
1850 .fetch_size = intel_8xx_fetch_size,
1851 .cleanup = intel_8xx_cleanup,
1852 .tlb_flush = intel_8xx_tlbflush,
1853 .mask_memory = agp_generic_mask_memory,
1854 .masks = intel_generic_masks,
1855 .agp_enable = agp_generic_enable,
1856 .cache_flush = global_cache_flush,
1857 .create_gatt_table = agp_generic_create_gatt_table,
1858 .free_gatt_table = agp_generic_free_gatt_table,
1859 .insert_memory = agp_generic_insert_memory,
1860 .remove_memory = agp_generic_remove_memory,
1861 .alloc_by_type = agp_generic_alloc_by_type,
1862 .free_by_type = agp_generic_free_by_type,
1863 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001864 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001865 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001866 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001867 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001868};
1869
Dave Jonese5524f32007-02-22 18:41:28 -05001870static const struct agp_bridge_driver intel_840_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001871 .owner = THIS_MODULE,
1872 .aperture_sizes = intel_8xx_sizes,
1873 .size_type = U8_APER_SIZE,
1874 .num_aperture_sizes = 7,
1875 .configure = intel_840_configure,
1876 .fetch_size = intel_8xx_fetch_size,
1877 .cleanup = intel_8xx_cleanup,
1878 .tlb_flush = intel_8xx_tlbflush,
1879 .mask_memory = agp_generic_mask_memory,
1880 .masks = intel_generic_masks,
1881 .agp_enable = agp_generic_enable,
1882 .cache_flush = global_cache_flush,
1883 .create_gatt_table = agp_generic_create_gatt_table,
1884 .free_gatt_table = agp_generic_free_gatt_table,
1885 .insert_memory = agp_generic_insert_memory,
1886 .remove_memory = agp_generic_remove_memory,
1887 .alloc_by_type = agp_generic_alloc_by_type,
1888 .free_by_type = agp_generic_free_by_type,
1889 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001890 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001891 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001892 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001893 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001894};
1895
Dave Jonese5524f32007-02-22 18:41:28 -05001896static const struct agp_bridge_driver intel_845_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001897 .owner = THIS_MODULE,
1898 .aperture_sizes = intel_8xx_sizes,
1899 .size_type = U8_APER_SIZE,
1900 .num_aperture_sizes = 7,
1901 .configure = intel_845_configure,
1902 .fetch_size = intel_8xx_fetch_size,
1903 .cleanup = intel_8xx_cleanup,
1904 .tlb_flush = intel_8xx_tlbflush,
1905 .mask_memory = agp_generic_mask_memory,
1906 .masks = intel_generic_masks,
1907 .agp_enable = agp_generic_enable,
1908 .cache_flush = global_cache_flush,
1909 .create_gatt_table = agp_generic_create_gatt_table,
1910 .free_gatt_table = agp_generic_free_gatt_table,
1911 .insert_memory = agp_generic_insert_memory,
1912 .remove_memory = agp_generic_remove_memory,
1913 .alloc_by_type = agp_generic_alloc_by_type,
1914 .free_by_type = agp_generic_free_by_type,
1915 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001916 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001917 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001918 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001919 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Dave Airlie2162e6a2007-11-21 16:36:31 +10001920 .chipset_flush = intel_i830_chipset_flush,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001921};
1922
Dave Jonese5524f32007-02-22 18:41:28 -05001923static const struct agp_bridge_driver intel_850_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001924 .owner = THIS_MODULE,
1925 .aperture_sizes = intel_8xx_sizes,
1926 .size_type = U8_APER_SIZE,
1927 .num_aperture_sizes = 7,
1928 .configure = intel_850_configure,
1929 .fetch_size = intel_8xx_fetch_size,
1930 .cleanup = intel_8xx_cleanup,
1931 .tlb_flush = intel_8xx_tlbflush,
1932 .mask_memory = agp_generic_mask_memory,
1933 .masks = intel_generic_masks,
1934 .agp_enable = agp_generic_enable,
1935 .cache_flush = global_cache_flush,
1936 .create_gatt_table = agp_generic_create_gatt_table,
1937 .free_gatt_table = agp_generic_free_gatt_table,
1938 .insert_memory = agp_generic_insert_memory,
1939 .remove_memory = agp_generic_remove_memory,
1940 .alloc_by_type = agp_generic_alloc_by_type,
1941 .free_by_type = agp_generic_free_by_type,
1942 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001943 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001944 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001945 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001946 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001947};
1948
Dave Jonese5524f32007-02-22 18:41:28 -05001949static const struct agp_bridge_driver intel_860_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001950 .owner = THIS_MODULE,
1951 .aperture_sizes = intel_8xx_sizes,
1952 .size_type = U8_APER_SIZE,
1953 .num_aperture_sizes = 7,
1954 .configure = intel_860_configure,
1955 .fetch_size = intel_8xx_fetch_size,
1956 .cleanup = intel_8xx_cleanup,
1957 .tlb_flush = intel_8xx_tlbflush,
1958 .mask_memory = agp_generic_mask_memory,
1959 .masks = intel_generic_masks,
1960 .agp_enable = agp_generic_enable,
1961 .cache_flush = global_cache_flush,
1962 .create_gatt_table = agp_generic_create_gatt_table,
1963 .free_gatt_table = agp_generic_free_gatt_table,
1964 .insert_memory = agp_generic_insert_memory,
1965 .remove_memory = agp_generic_remove_memory,
1966 .alloc_by_type = agp_generic_alloc_by_type,
1967 .free_by_type = agp_generic_free_by_type,
1968 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001969 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001970 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001971 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001972 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001973};
1974
Dave Jonese5524f32007-02-22 18:41:28 -05001975static const struct agp_bridge_driver intel_915_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001976 .owner = THIS_MODULE,
1977 .aperture_sizes = intel_i830_sizes,
1978 .size_type = FIXED_APER_SIZE,
Dave Jonesc14635e2006-09-06 11:59:35 -04001979 .num_aperture_sizes = 4,
Joe Perchesc7258012008-03-26 14:10:02 -07001980 .needs_scratch_page = true,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001981 .configure = intel_i915_configure,
Eric Anholtc41e0de2006-12-19 12:57:24 -08001982 .fetch_size = intel_i9xx_fetch_size,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001983 .cleanup = intel_i915_cleanup,
1984 .tlb_flush = intel_i810_tlbflush,
1985 .mask_memory = intel_i810_mask_memory,
1986 .masks = intel_i810_masks,
1987 .agp_enable = intel_i810_agp_enable,
1988 .cache_flush = global_cache_flush,
1989 .create_gatt_table = intel_i915_create_gatt_table,
1990 .free_gatt_table = intel_i830_free_gatt_table,
1991 .insert_memory = intel_i915_insert_entries,
1992 .remove_memory = intel_i915_remove_entries,
1993 .alloc_by_type = intel_i830_alloc_by_type,
1994 .free_by_type = intel_i810_free_by_type,
1995 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001996 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001997 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001998 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001999 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
Dave Airlie6c00a612007-10-29 18:06:10 +10002000 .chipset_flush = intel_i915_chipset_flush,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002001};
2002
Dave Jonese5524f32007-02-22 18:41:28 -05002003static const struct agp_bridge_driver intel_i965_driver = {
Dave Airlie62c96b92008-06-19 14:27:53 +10002004 .owner = THIS_MODULE,
2005 .aperture_sizes = intel_i830_sizes,
2006 .size_type = FIXED_APER_SIZE,
2007 .num_aperture_sizes = 4,
2008 .needs_scratch_page = true,
Dave Airlie0e480e52008-06-19 14:57:31 +10002009 .configure = intel_i915_configure,
2010 .fetch_size = intel_i9xx_fetch_size,
Dave Airlie62c96b92008-06-19 14:27:53 +10002011 .cleanup = intel_i915_cleanup,
2012 .tlb_flush = intel_i810_tlbflush,
2013 .mask_memory = intel_i965_mask_memory,
2014 .masks = intel_i810_masks,
2015 .agp_enable = intel_i810_agp_enable,
2016 .cache_flush = global_cache_flush,
2017 .create_gatt_table = intel_i965_create_gatt_table,
2018 .free_gatt_table = intel_i830_free_gatt_table,
2019 .insert_memory = intel_i915_insert_entries,
2020 .remove_memory = intel_i915_remove_entries,
2021 .alloc_by_type = intel_i830_alloc_by_type,
2022 .free_by_type = intel_i810_free_by_type,
2023 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08002024 .agp_alloc_pages = agp_generic_alloc_pages,
Dave Airlie62c96b92008-06-19 14:27:53 +10002025 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08002026 .agp_destroy_pages = agp_generic_destroy_pages,
Dave Airlie62c96b92008-06-19 14:27:53 +10002027 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
Dave Airlie6c00a612007-10-29 18:06:10 +10002028 .chipset_flush = intel_i915_chipset_flush,
Eric Anholt65c25aa2006-09-06 11:57:18 -04002029};
Linus Torvalds1da177e2005-04-16 15:20:36 -07002030
Dave Jonese5524f32007-02-22 18:41:28 -05002031static const struct agp_bridge_driver intel_7505_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002032 .owner = THIS_MODULE,
2033 .aperture_sizes = intel_8xx_sizes,
2034 .size_type = U8_APER_SIZE,
2035 .num_aperture_sizes = 7,
2036 .configure = intel_7505_configure,
2037 .fetch_size = intel_8xx_fetch_size,
2038 .cleanup = intel_8xx_cleanup,
2039 .tlb_flush = intel_8xx_tlbflush,
2040 .mask_memory = agp_generic_mask_memory,
2041 .masks = intel_generic_masks,
2042 .agp_enable = agp_generic_enable,
2043 .cache_flush = global_cache_flush,
2044 .create_gatt_table = agp_generic_create_gatt_table,
2045 .free_gatt_table = agp_generic_free_gatt_table,
2046 .insert_memory = agp_generic_insert_memory,
2047 .remove_memory = agp_generic_remove_memory,
2048 .alloc_by_type = agp_generic_alloc_by_type,
2049 .free_by_type = agp_generic_free_by_type,
2050 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08002051 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002052 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08002053 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01002054 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002055};
2056
Wang Zhenyu874808c62007-06-06 11:16:25 +08002057static const struct agp_bridge_driver intel_g33_driver = {
Dave Airlie62c96b92008-06-19 14:27:53 +10002058 .owner = THIS_MODULE,
2059 .aperture_sizes = intel_i830_sizes,
2060 .size_type = FIXED_APER_SIZE,
2061 .num_aperture_sizes = 4,
2062 .needs_scratch_page = true,
2063 .configure = intel_i915_configure,
2064 .fetch_size = intel_i9xx_fetch_size,
2065 .cleanup = intel_i915_cleanup,
2066 .tlb_flush = intel_i810_tlbflush,
2067 .mask_memory = intel_i965_mask_memory,
2068 .masks = intel_i810_masks,
2069 .agp_enable = intel_i810_agp_enable,
2070 .cache_flush = global_cache_flush,
2071 .create_gatt_table = intel_i915_create_gatt_table,
2072 .free_gatt_table = intel_i830_free_gatt_table,
2073 .insert_memory = intel_i915_insert_entries,
2074 .remove_memory = intel_i915_remove_entries,
2075 .alloc_by_type = intel_i830_alloc_by_type,
2076 .free_by_type = intel_i810_free_by_type,
2077 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08002078 .agp_alloc_pages = agp_generic_alloc_pages,
Dave Airlie62c96b92008-06-19 14:27:53 +10002079 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08002080 .agp_destroy_pages = agp_generic_destroy_pages,
Dave Airlie62c96b92008-06-19 14:27:53 +10002081 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
Dave Airlie6c00a612007-10-29 18:06:10 +10002082 .chipset_flush = intel_i915_chipset_flush,
Wang Zhenyu874808c62007-06-06 11:16:25 +08002083};
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002084
2085static int find_gmch(u16 device)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002086{
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002087 struct pci_dev *gmch_device;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002088
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002089 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2090 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
2091 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
Dave Airlief011ae72008-01-25 11:23:04 +10002092 device, gmch_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002093 }
2094
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002095 if (!gmch_device)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002096 return 0;
2097
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002098 intel_private.pcidev = gmch_device;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002099 return 1;
2100}
2101
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002102/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
2103 * driver and gmch_driver must be non-null, and find_gmch will determine
2104 * which one should be used if a gmch_chip_id is present.
2105 */
2106static const struct intel_driver_description {
2107 unsigned int chip_id;
2108 unsigned int gmch_chip_id;
Wang Zhenyu88889852007-06-14 10:01:04 +08002109 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002110 char *name;
2111 const struct agp_bridge_driver *driver;
2112 const struct agp_bridge_driver *gmch_driver;
2113} intel_agp_chipsets[] = {
Wang Zhenyu88889852007-06-14 10:01:04 +08002114 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2115 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2116 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2117 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002118 NULL, &intel_810_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002119 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002120 NULL, &intel_810_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002121 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002122 NULL, &intel_810_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002123 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2124 &intel_815_driver, &intel_810_driver },
2125 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2126 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2127 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002128 &intel_830mp_driver, &intel_830_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002129 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2130 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2131 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002132 &intel_845_driver, &intel_830_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002133 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
Stefan Husemann347486b2009-04-13 14:40:10 -07002134 { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854",
2135 &intel_845_driver, &intel_830_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002136 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2137 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002138 &intel_845_driver, &intel_830_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002139 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2140 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002141 &intel_845_driver, &intel_830_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002142 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
Carlos Martíne914a362008-01-24 10:34:09 +10002143 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2144 NULL, &intel_915_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002145 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002146 NULL, &intel_915_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002147 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002148 NULL, &intel_915_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002149 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002150 NULL, &intel_915_driver },
Zhenyu Wangdde47872007-07-26 09:18:09 +08002151 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002152 NULL, &intel_915_driver },
Zhenyu Wangdde47872007-07-26 09:18:09 +08002153 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002154 NULL, &intel_915_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002155 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002156 NULL, &intel_i965_driver },
Zhenyu Wang9119f852008-01-23 15:49:26 +10002157 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002158 NULL, &intel_i965_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002159 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002160 NULL, &intel_i965_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002161 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002162 NULL, &intel_i965_driver },
Zhenyu Wangdde47872007-07-26 09:18:09 +08002163 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002164 NULL, &intel_i965_driver },
Zhenyu Wangdde47872007-07-26 09:18:09 +08002165 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002166 NULL, &intel_i965_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002167 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2168 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2169 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002170 NULL, &intel_g33_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002171 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002172 NULL, &intel_g33_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002173 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002174 NULL, &intel_g33_driver },
Shaohua Li21778322009-02-23 15:19:16 +08002175 { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, 0, "IGD",
2176 NULL, &intel_g33_driver },
2177 { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, 0, "IGD",
2178 NULL, &intel_g33_driver },
Zhenyu Wang99d32bd2008-07-30 12:26:50 -07002179 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
Eric Anholtb854b2a2008-12-22 18:56:27 -08002180 "Mobile Intel® GM45 Express", NULL, &intel_i965_driver },
Zhenyu Wang25ce77a2008-06-19 14:17:58 +10002181 { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
2182 "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2183 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2184 "Q45/Q43", NULL, &intel_i965_driver },
2185 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2186 "G45/G43", NULL, &intel_i965_driver },
Zhenyu Wanga50ccc62008-11-17 14:39:00 +08002187 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2188 "G41", NULL, &intel_i965_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002189 { 0, 0, 0, NULL, NULL, NULL }
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002190};
2191
Linus Torvalds1da177e2005-04-16 15:20:36 -07002192static int __devinit agp_intel_probe(struct pci_dev *pdev,
2193 const struct pci_device_id *ent)
2194{
2195 struct agp_bridge_data *bridge;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002196 u8 cap_ptr = 0;
2197 struct resource *r;
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002198 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002199
2200 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2201
2202 bridge = agp_alloc_bridge();
2203 if (!bridge)
2204 return -ENOMEM;
2205
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002206 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2207 /* In case that multiple models of gfx chip may
2208 stand on same host bridge type, this can be
2209 sure we detect the right IGD. */
Wang Zhenyu88889852007-06-14 10:01:04 +08002210 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2211 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2212 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2213 bridge->driver =
2214 intel_agp_chipsets[i].gmch_driver;
2215 break;
2216 } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2217 continue;
2218 } else {
2219 bridge->driver = intel_agp_chipsets[i].driver;
2220 break;
2221 }
2222 }
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002223 }
2224
2225 if (intel_agp_chipsets[i].name == NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002226 if (cap_ptr)
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07002227 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
2228 pdev->vendor, pdev->device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002229 agp_put_bridge(bridge);
2230 return -ENODEV;
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002231 }
2232
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002233 if (bridge->driver == NULL) {
Wang Zhenyu47d46372007-06-21 13:43:18 +08002234 /* bridge has no AGP and no IGD detected */
2235 if (cap_ptr)
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07002236 dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
2237 intel_agp_chipsets[i].gmch_chip_id);
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002238 agp_put_bridge(bridge);
2239 return -ENODEV;
Dave Airlief011ae72008-01-25 11:23:04 +10002240 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002241
2242 bridge->dev = pdev;
2243 bridge->capndx = cap_ptr;
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08002244 bridge->dev_private_data = &intel_private;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002245
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07002246 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002247
2248 /*
2249 * The following fixes the case where the BIOS has "forgotten" to
2250 * provide an address range for the GART.
2251 * 20030610 - hamish@zot.org
2252 */
2253 r = &pdev->resource[0];
2254 if (!r->start && r->end) {
Dave Jones6a92a4e2006-02-28 00:54:25 -05002255 if (pci_assign_resource(pdev, 0)) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07002256 dev_err(&pdev->dev, "can't assign resource 0\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002257 agp_put_bridge(bridge);
2258 return -ENODEV;
2259 }
2260 }
2261
2262 /*
2263 * If the device has not been properly setup, the following will catch
2264 * the problem and should stop the system from crashing.
2265 * 20030610 - hamish@zot.org
2266 */
2267 if (pci_enable_device(pdev)) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07002268 dev_err(&pdev->dev, "can't enable PCI device\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002269 agp_put_bridge(bridge);
2270 return -ENODEV;
2271 }
2272
2273 /* Fill in the mode register */
2274 if (cap_ptr) {
2275 pci_read_config_dword(pdev,
2276 bridge->capndx+PCI_AGP_STATUS,
2277 &bridge->mode);
2278 }
2279
2280 pci_set_drvdata(pdev, bridge);
2281 return agp_add_bridge(bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002282}
2283
2284static void __devexit agp_intel_remove(struct pci_dev *pdev)
2285{
2286 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2287
2288 agp_remove_bridge(bridge);
2289
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08002290 if (intel_private.pcidev)
2291 pci_dev_put(intel_private.pcidev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002292
2293 agp_put_bridge(bridge);
2294}
2295
Alexey Dobriyan85be7d62006-08-12 02:02:02 +04002296#ifdef CONFIG_PM
Linus Torvalds1da177e2005-04-16 15:20:36 -07002297static int agp_intel_resume(struct pci_dev *pdev)
2298{
2299 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
Keith Packarda8c84df2008-07-31 15:48:07 +10002300 int ret_val;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002301
2302 pci_restore_state(pdev);
2303
Wang Zhenyu4b953202007-01-17 11:07:54 +08002304 /* We should restore our graphics device's config space,
2305 * as host bridge (00:00) resumes before graphics device (02:00),
2306 * then our access to its pci space can work right.
2307 */
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08002308 if (intel_private.pcidev)
2309 pci_restore_state(intel_private.pcidev);
Wang Zhenyu4b953202007-01-17 11:07:54 +08002310
Linus Torvalds1da177e2005-04-16 15:20:36 -07002311 if (bridge->driver == &intel_generic_driver)
2312 intel_configure();
2313 else if (bridge->driver == &intel_850_driver)
2314 intel_850_configure();
2315 else if (bridge->driver == &intel_845_driver)
2316 intel_845_configure();
2317 else if (bridge->driver == &intel_830mp_driver)
2318 intel_830mp_configure();
2319 else if (bridge->driver == &intel_915_driver)
2320 intel_i915_configure();
2321 else if (bridge->driver == &intel_830_driver)
2322 intel_i830_configure();
2323 else if (bridge->driver == &intel_810_driver)
2324 intel_i810_configure();
Dave Jones08da3f42006-09-10 21:09:26 -04002325 else if (bridge->driver == &intel_i965_driver)
2326 intel_i915_configure();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002327
Keith Packarda8c84df2008-07-31 15:48:07 +10002328 ret_val = agp_rebind_memory();
2329 if (ret_val != 0)
2330 return ret_val;
2331
Linus Torvalds1da177e2005-04-16 15:20:36 -07002332 return 0;
2333}
Alexey Dobriyan85be7d62006-08-12 02:02:02 +04002334#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002335
2336static struct pci_device_id agp_intel_pci_table[] = {
2337#define ID(x) \
2338 { \
2339 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2340 .class_mask = ~0, \
2341 .vendor = PCI_VENDOR_ID_INTEL, \
2342 .device = x, \
2343 .subvendor = PCI_ANY_ID, \
2344 .subdevice = PCI_ANY_ID, \
2345 }
2346 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2347 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2348 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2349 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2350 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2351 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2352 ID(PCI_DEVICE_ID_INTEL_82815_MC),
2353 ID(PCI_DEVICE_ID_INTEL_82820_HB),
2354 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2355 ID(PCI_DEVICE_ID_INTEL_82830_HB),
2356 ID(PCI_DEVICE_ID_INTEL_82840_HB),
2357 ID(PCI_DEVICE_ID_INTEL_82845_HB),
2358 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2359 ID(PCI_DEVICE_ID_INTEL_82850_HB),
Stefan Husemann347486b2009-04-13 14:40:10 -07002360 ID(PCI_DEVICE_ID_INTEL_82854_HB),
Linus Torvalds1da177e2005-04-16 15:20:36 -07002361 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2362 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2363 ID(PCI_DEVICE_ID_INTEL_82860_HB),
2364 ID(PCI_DEVICE_ID_INTEL_82865_HB),
2365 ID(PCI_DEVICE_ID_INTEL_82875_HB),
2366 ID(PCI_DEVICE_ID_INTEL_7505_0),
2367 ID(PCI_DEVICE_ID_INTEL_7205_0),
Carlos Martíne914a362008-01-24 10:34:09 +10002368 ID(PCI_DEVICE_ID_INTEL_E7221_HB),
Linus Torvalds1da177e2005-04-16 15:20:36 -07002369 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2370 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
Alan Hourihaned0de98f2005-05-31 19:50:49 +01002371 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
Alan Hourihane3b0e8ea2006-01-19 14:08:40 +00002372 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
Zhenyu Wangdde47872007-07-26 09:18:09 +08002373 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
Shaohua Li21778322009-02-23 15:19:16 +08002374 ID(PCI_DEVICE_ID_INTEL_IGDGM_HB),
2375 ID(PCI_DEVICE_ID_INTEL_IGDG_HB),
Eric Anholt65c25aa2006-09-06 11:57:18 -04002376 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
Zhenyu Wang9119f852008-01-23 15:49:26 +10002377 ID(PCI_DEVICE_ID_INTEL_82G35_HB),
Eric Anholt65c25aa2006-09-06 11:57:18 -04002378 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2379 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
Wang Zhenyu4598af32007-04-09 08:51:36 +08002380 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
Zhenyu Wangdde47872007-07-26 09:18:09 +08002381 ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
Wang Zhenyu874808c62007-06-06 11:16:25 +08002382 ID(PCI_DEVICE_ID_INTEL_G33_HB),
2383 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2384 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
Zhenyu Wang99d32bd2008-07-30 12:26:50 -07002385 ID(PCI_DEVICE_ID_INTEL_GM45_HB),
Zhenyu Wang25ce77a2008-06-19 14:17:58 +10002386 ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
2387 ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2388 ID(PCI_DEVICE_ID_INTEL_G45_HB),
Zhenyu Wanga50ccc62008-11-17 14:39:00 +08002389 ID(PCI_DEVICE_ID_INTEL_G41_HB),
Linus Torvalds1da177e2005-04-16 15:20:36 -07002390 { }
2391};
2392
2393MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2394
2395static struct pci_driver agp_intel_pci_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002396 .name = "agpgart-intel",
2397 .id_table = agp_intel_pci_table,
2398 .probe = agp_intel_probe,
2399 .remove = __devexit_p(agp_intel_remove),
Alexey Dobriyan85be7d62006-08-12 02:02:02 +04002400#ifdef CONFIG_PM
Linus Torvalds1da177e2005-04-16 15:20:36 -07002401 .resume = agp_intel_resume,
Alexey Dobriyan85be7d62006-08-12 02:02:02 +04002402#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002403};
2404
2405static int __init agp_intel_init(void)
2406{
2407 if (agp_off)
2408 return -EINVAL;
2409 return pci_register_driver(&agp_intel_pci_driver);
2410}
2411
2412static void __exit agp_intel_cleanup(void)
2413{
2414 pci_unregister_driver(&agp_intel_pci_driver);
2415}
2416
2417module_init(agp_intel_init);
2418module_exit(agp_intel_cleanup);
2419
Dave Jonesf4432c52008-10-20 13:31:45 -04002420MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002421MODULE_LICENSE("GPL and additional rights");