/*************************************************************************/ /*!
@File
@Title          OS and CPU d-cache maintenance mechanisms
@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
@Description    Defines for cache management which are visible internally only
@License        Dual MIT/GPLv2

The contents of this file are subject to the MIT license as set out below.

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of this software and associated documentation files (the "Software"), to deal
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*/ /**************************************************************************/

#ifndef _OS_CPU_CACHE_H_
#define _OS_CPU_CACHE_H_

#include "info_page_defs.h"

#define PVRSRV_CACHE_OP_GLOBAL				0x4 /*!< Extends cache_ops.h with explicit global flush w/ invalidate */
#define PVRSRV_CACHE_OP_TIMELINE			0x8 /*!< Request SW_SYNC timeline notification when executed */

#define CACHEFLUSH_ISA_X86					0x1	/*!< x86/x64 specific UM range-based cache flush */
#define CACHEFLUSH_ISA_ARM64				0x2	/*!< Aarch64 specific UM range-based cache flush */
#define CACHEFLUSH_ISA_GENERIC				0x3	/*!< Other ISA's without UM range-based cache flush */
#ifndef CACHEFLUSH_ISA_TYPE
	#if defined(__i386__) || defined(__x86_64__)
		#define CACHEFLUSH_ISA_TYPE CACHEFLUSH_ISA_X86
	#elif defined(__arm64__) || defined(__aarch64__)
		#define CACHEFLUSH_ISA_TYPE CACHEFLUSH_ISA_ARM64
	#else
		#define CACHEFLUSH_ISA_TYPE CACHEFLUSH_ISA_GENERIC
	#endif
#endif

#if (CACHEFLUSH_ISA_TYPE == CACHEFLUSH_ISA_X86) || (CACHEFLUSH_ISA_TYPE == CACHEFLUSH_ISA_ARM64)
#define CACHEFLUSH_ISA_SUPPORTS_UM_FLUSH		/*!< x86/x86_64/ARM64 supports user-mode d-cache flush */
#endif

#if !defined(__mips__)
#define CACHEFLUSH_ISA_SUPPORTS_GLOBAL_FLUSH	/*!< MIPS32/64 has no concept of a global d-cache flush */
#endif

#endif	/* _OS_CPU_CACHE_H_ */