[
    {
        "EventCode": "0x05",
        "UMask": "0x1",
        "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
        "Counter": "0,1,2,3",
        "EventName": "MISALIGN_MEM_REF.LOADS",
        "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x05",
        "UMask": "0x2",
        "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
        "Counter": "0,1,2,3",
        "EventName": "MISALIGN_MEM_REF.STORES",
        "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x54",
        "UMask": "0x1",
        "BriefDescription": "Number of times a TSX line had a cache conflict",
        "Counter": "0,1,2,3",
        "EventName": "TX_MEM.ABORT_CONFLICT",
        "PublicDescription": "Number of times a TSX line had a cache conflict.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x54",
        "UMask": "0x2",
        "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
        "Counter": "0,1,2,3",
        "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
        "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x54",
        "UMask": "0x4",
        "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
        "Counter": "0,1,2,3",
        "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
        "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x54",
        "UMask": "0x8",
        "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
        "Counter": "0,1,2,3",
        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
        "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x54",
        "UMask": "0x10",
        "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
        "Counter": "0,1,2,3",
        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
        "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x54",
        "UMask": "0x20",
        "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
        "Counter": "0,1,2,3",
        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
        "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x54",
        "UMask": "0x40",
        "BriefDescription": "Number of times we could not allocate Lock Buffer",
        "Counter": "0,1,2,3",
        "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
        "PublicDescription": "Number of times we could not allocate Lock Buffer.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x5d",
        "UMask": "0x1",
        "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
        "Counter": "0,1,2,3",
        "EventName": "TX_EXEC.MISC1",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x5d",
        "UMask": "0x2",
        "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
        "Counter": "0,1,2,3",
        "EventName": "TX_EXEC.MISC2",
        "PublicDescription": "Unfriendly TSX abort triggered by  a vzeroupper instruction.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x5d",
        "UMask": "0x4",
        "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
        "Counter": "0,1,2,3",
        "EventName": "TX_EXEC.MISC3",
        "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x5d",
        "UMask": "0x8",
        "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
        "Counter": "0,1,2,3",
        "EventName": "TX_EXEC.MISC4",
        "PublicDescription": "RTM region detected inside HLE.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x5d",
        "UMask": "0x10",
        "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
        "Counter": "0,1,2,3",
        "EventName": "TX_EXEC.MISC5",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC3",
        "UMask": "0x2",
        "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
        "Counter": "0,1,2,3",
        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
        "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xc8",
        "UMask": "0x1",
        "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
        "Counter": "0,1,2,3",
        "EventName": "HLE_RETIRED.START",
        "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xc8",
        "UMask": "0x2",
        "BriefDescription": "Number of times HLE commit succeeded",
        "Counter": "0,1,2,3",
        "EventName": "HLE_RETIRED.COMMIT",
        "PublicDescription": "Number of times HLE commit succeeded.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xc8",
        "UMask": "0x4",
        "BriefDescription": "Number of times HLE abort was triggered (PEBS)",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "HLE_RETIRED.ABORTED",
        "PublicDescription": "Number of times HLE abort was triggered (PEBS).",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xc8",
        "UMask": "0x8",
        "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
        "Counter": "0,1,2,3",
        "EventName": "HLE_RETIRED.ABORTED_MISC1",
        "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xc8",
        "UMask": "0x10",
        "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
        "Counter": "0,1,2,3",
        "EventName": "HLE_RETIRED.ABORTED_MISC2",
        "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xc8",
        "UMask": "0x20",
        "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
        "Counter": "0,1,2,3",
        "EventName": "HLE_RETIRED.ABORTED_MISC3",
        "PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xc8",
        "UMask": "0x40",
        "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
        "Counter": "0,1,2,3",
        "EventName": "HLE_RETIRED.ABORTED_MISC4",
        "PublicDescription": "Number of times HLE caused a fault.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xc8",
        "UMask": "0x80",
        "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
        "Counter": "0,1,2,3",
        "EventName": "HLE_RETIRED.ABORTED_MISC5",
        "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xc9",
        "UMask": "0x1",
        "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
        "Counter": "0,1,2,3",
        "EventName": "RTM_RETIRED.START",
        "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xc9",
        "UMask": "0x2",
        "BriefDescription": "Number of times RTM commit succeeded",
        "Counter": "0,1,2,3",
        "EventName": "RTM_RETIRED.COMMIT",
        "PublicDescription": "Number of times RTM commit succeeded.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xc9",
        "UMask": "0x4",
        "BriefDescription": "Number of times RTM abort was triggered (PEBS)",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "RTM_RETIRED.ABORTED",
        "PublicDescription": "Number of times RTM abort was triggered (PEBS).",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xc9",
        "UMask": "0x8",
        "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
        "Counter": "0,1,2,3",
        "EventName": "RTM_RETIRED.ABORTED_MISC1",
        "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xc9",
        "UMask": "0x10",
        "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
        "Counter": "0,1,2,3",
        "EventName": "RTM_RETIRED.ABORTED_MISC2",
        "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xc9",
        "UMask": "0x20",
        "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
        "Counter": "0,1,2,3",
        "EventName": "RTM_RETIRED.ABORTED_MISC3",
        "PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xc9",
        "UMask": "0x40",
        "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
        "Counter": "0,1,2,3",
        "EventName": "RTM_RETIRED.ABORTED_MISC4",
        "PublicDescription": "Number of times a RTM caused a fault.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xc9",
        "UMask": "0x80",
        "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
        "Counter": "0,1,2,3",
        "EventName": "RTM_RETIRED.ABORTED_MISC5",
        "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xCD",
        "UMask": "0x1",
        "BriefDescription": "Loads with latency value being above 4",
        "PEBS": "2",
        "MSRValue": "0x4",
        "Counter": "3",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
        "MSRIndex": "0x3F6",
        "Errata": "BDM100, BDM35",
        "PublicDescription": "This event counts loads with latency value being above four.",
        "TakenAlone": "1",
        "SampleAfterValue": "100003",
        "CounterHTOff": "3"
    },
    {
        "EventCode": "0xCD",
        "UMask": "0x1",
        "BriefDescription": "Loads with latency value being above 8",
        "PEBS": "2",
        "MSRValue": "0x8",
        "Counter": "3",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
        "MSRIndex": "0x3F6",
        "Errata": "BDM100, BDM35",
        "PublicDescription": "This event counts loads with latency value being above eight.",
        "TakenAlone": "1",
        "SampleAfterValue": "50021",
        "CounterHTOff": "3"
    },
    {
        "EventCode": "0xCD",
        "UMask": "0x1",
        "BriefDescription": "Loads with latency value being above 16",
        "PEBS": "2",
        "MSRValue": "0x10",
        "Counter": "3",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
        "MSRIndex": "0x3F6",
        "Errata": "BDM100, BDM35",
        "PublicDescription": "This event counts loads with latency value being above 16.",
        "TakenAlone": "1",
        "SampleAfterValue": "20011",
        "CounterHTOff": "3"
    },
    {
        "EventCode": "0xCD",
        "UMask": "0x1",
        "BriefDescription": "Loads with latency value being above 32",
        "PEBS": "2",
        "MSRValue": "0x20",
        "Counter": "3",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
        "MSRIndex": "0x3F6",
        "Errata": "BDM100, BDM35",
        "PublicDescription": "This event counts loads with latency value being above 32.",
        "TakenAlone": "1",
        "SampleAfterValue": "100007",
        "CounterHTOff": "3"
    },
    {
        "EventCode": "0xCD",
        "UMask": "0x1",
        "BriefDescription": "Loads with latency value being above 64",
        "PEBS": "2",
        "MSRValue": "0x40",
        "Counter": "3",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
        "MSRIndex": "0x3F6",
        "Errata": "BDM100, BDM35",
        "PublicDescription": "This event counts loads with latency value being above 64.",
        "TakenAlone": "1",
        "SampleAfterValue": "2003",
        "CounterHTOff": "3"
    },
    {
        "EventCode": "0xCD",
        "UMask": "0x1",
        "BriefDescription": "Loads with latency value being above 128",
        "PEBS": "2",
        "MSRValue": "0x80",
        "Counter": "3",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
        "MSRIndex": "0x3F6",
        "Errata": "BDM100, BDM35",
        "PublicDescription": "This event counts loads with latency value being above 128.",
        "TakenAlone": "1",
        "SampleAfterValue": "1009",
        "CounterHTOff": "3"
    },
    {
        "EventCode": "0xCD",
        "UMask": "0x1",
        "BriefDescription": "Loads with latency value being above 256",
        "PEBS": "2",
        "MSRValue": "0x100",
        "Counter": "3",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
        "MSRIndex": "0x3F6",
        "Errata": "BDM100, BDM35",
        "PublicDescription": "This event counts loads with latency value being above 256.",
        "TakenAlone": "1",
        "SampleAfterValue": "503",
        "CounterHTOff": "3"
    },
    {
        "EventCode": "0xCD",
        "UMask": "0x1",
        "BriefDescription": "Loads with latency value being above 512",
        "PEBS": "2",
        "MSRValue": "0x200",
        "Counter": "3",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
        "MSRIndex": "0x3F6",
        "Errata": "BDM100, BDM35",
        "PublicDescription": "This event counts loads with latency value being above 512.",
        "TakenAlone": "1",
        "SampleAfterValue": "101",
        "CounterHTOff": "3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all requests that miss in the L3",
        "MSRValue": "0x3fbfc08fff",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all requests that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache",
        "MSRValue": "0x087fc007f7",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache",
        "MSRValue": "0x103fc007f7",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram",
        "MSRValue": "0x063bc007f7",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram",
        "MSRValue": "0x06040007f7",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3",
        "MSRValue": "0x3fbfc007f7",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram",
        "MSRValue": "0x0604000244",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch code reads that miss in the L3",
        "MSRValue": "0x3fbfc00244",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram",
        "MSRValue": "0x0604000122",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3",
        "MSRValue": "0x3fbfc00122",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache",
        "MSRValue": "0x087fc00091",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache",
        "MSRValue": "0x103fc00091",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram",
        "MSRValue": "0x063bc00091",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram",
        "MSRValue": "0x0604000091",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3",
        "MSRValue": "0x3fbfc00091",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3",
        "MSRValue": "0x3fbfc00200",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3",
        "MSRValue": "0x3fbfc00100",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache",
        "MSRValue": "0x103fc00002",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3",
        "MSRValue": "0x3fbfc00002",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand data writes (RFOs) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    }
]