)]}'
{
  "commit": "cf719012b23278c65d0bca4975a7ea46e5bb75be",
  "tree": "55ef3d9f2d96e3546304fd07619e6c1dffcb6e08",
  "parents": [
    "cdb8b80b60935515b86cfe534f69934b13937052"
  ],
  "author": {
    "name": "Chen-Yu Tsai",
    "email": "wens@csie.org",
    "time": "Wed Apr 05 14:37:42 2017 +0800"
  },
  "committer": {
    "name": "Maxime Ripard",
    "email": "maxime.ripard@free-electrons.com",
    "time": "Wed Apr 05 09:01:41 2017 +0200"
  },
  "message": "clk: sunxi-ng: mult: Support PLL lock detection\n\nSome PLL clocks are N (multiplier) type clocks, or can be simplified\nas such. An example of the former is the DDR1 PLL clock on the A33.\nAn example of the latter is the CPU PLL clock on the A80, in which\nthe P divider is only used for low frequencies that are of little\nuse. Both clocks support PLL lock detection.\n\nThe mult clock macro implies support for this, but that is not true.\nThe field is simply discarded. This patch adds proper support for it.\n\nSigned-off-by: Chen-Yu Tsai \u003cwens@csie.org\u003e\nSigned-off-by: Maxime Ripard \u003cmaxime.ripard@free-electrons.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8724c01171b1758f00d1151a55e86ffea593c344",
      "old_mode": 33188,
      "old_path": "drivers/clk/sunxi-ng/ccu_mult.c",
      "new_id": "671141359895290a9dc6d6ea20efa9e8347eb421",
      "new_mode": 33188,
      "new_path": "drivers/clk/sunxi-ng/ccu_mult.c"
    },
    {
      "type": "modify",
      "old_id": "524acddfcb2eaf480b992b4f9761ad9b46fb8d70",
      "old_mode": 33188,
      "old_path": "drivers/clk/sunxi-ng/ccu_mult.h",
      "new_id": "f9c37b987d72b560d096faf7b24356863fd17cbc",
      "new_mode": 33188,
      "new_path": "drivers/clk/sunxi-ng/ccu_mult.h"
    }
  ]
}