)]}'
{
  "commit": "b60b08b02ca8d9575985ae6711bd656dd67e9039",
  "tree": "9178d2431c98688c2d4665b6e79c12fba0bf768b",
  "parents": [
    "426c457a3216fac74e3d44dd39729b0689f4c7ab"
  ],
  "author": {
    "name": "Kevin Cernekee",
    "email": "cernekee@gmail.com",
    "time": "Tue May 04 20:58:10 2010 -0700"
  },
  "committer": {
    "name": "David Woodhouse",
    "email": "David.Woodhouse@intel.com",
    "time": "Fri May 14 01:56:12 2010 +0100"
  },
  "message": "mtd: nand: support alternate BB marker locations on MLC\n\nThis is a slightly modified version of a patch submitted last year by\nReuben Dowle \u003creuben.dowle@navico.com\u003e.  His original comments follow:\n\nThis patch adds support for some MLC NAND flashes that place the BB\nmarker in the LAST page of the bad block rather than the FIRST page used\nfor SLC NAND and other types of MLC nand.\n\nLifted from Samsung datasheet for K9LG8G08U0A (1Gbyte MLC NAND):\n\"\nIdentifying Initial Invalid Block(s)\nAll device locations are erased(FFh) except locations where the initial\ninvalid block(s) information is written prior to shipping. The initial\ninvalid block(s) status is defined by the 1st byte in the spare area.\nSamsung makes sure that the last page of every initial invalid block has\nnon-FFh data at the column address of 2,048.\n...\n\"\n\nAs far as I can tell, this is the same for all Samsung MLC nand, and in\nfact the samsung bsp for the processor used in our project (s3c6410)\nactually contained a hack similar to this patch but less portable to\nenable use of their NAND parts. I discovered this problem when trying to\nuse a Micron NAND which does not used this layout - I wish samsung would\nput their stuff in main-line to avoid this type of problem.\n\nCurrently this patch causes all MLC nand with manufacturer codes from\nSamsung and ST(Numonyx) to use this alternative location, since these\nare the manufactures that I know of that use this layout.\n\nSigned-off-by: Kevin Cernekee \u003ccernekee@gmail.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "85891dcc27ad2b5c71f27ad36a54370b7afb9413",
      "old_mode": 33188,
      "old_path": "drivers/mtd/nand/nand_base.c",
      "new_id": "4a7b86423ee96fb749537f871cb776a2bc172eb3",
      "new_mode": 33188,
      "new_path": "drivers/mtd/nand/nand_base.c"
    },
    {
      "type": "modify",
      "old_id": "387c45c366fe5ed3a53b50445514f2f8e13bd1d7",
      "old_mode": 33188,
      "old_path": "drivers/mtd/nand/nand_bbt.c",
      "new_id": "ad97c0ce73b265a018c75871afe21bc17dc743c5",
      "new_mode": 33188,
      "new_path": "drivers/mtd/nand/nand_bbt.c"
    },
    {
      "type": "modify",
      "old_id": "50f3aa00a4522fd2e8b596adb0fb0a7cc0d590d4",
      "old_mode": 33188,
      "old_path": "include/linux/mtd/nand.h",
      "new_id": "a81b185e23a754f0474fa5eecf24acd96661fb5f",
      "new_mode": 33188,
      "new_path": "include/linux/mtd/nand.h"
    }
  ]
}