)]}'
{
  "commit": "b2ab4f08e84d4031f82255447180c559bd076bbf",
  "tree": "c43f3abc03b50d68c73c33750528819e349422e6",
  "parents": [
    "fea7a08acb13524b47711625eebea40a0ede69a0"
  ],
  "author": {
    "name": "Steven J. Hill",
    "email": "sjhill@mips.com",
    "time": "Thu Sep 13 16:47:58 2012 -0500"
  },
  "committer": {
    "name": "Steven J. Hill",
    "email": "sjhill@mips.com",
    "time": "Thu Sep 13 16:55:53 2012 -0500"
  },
  "message": "MIPS: Add base architecture support for RI and XI.\n\nOriginally both Read Inhibit (RI) and Execute Inhibit (XI) were\nsupported by the TLB only for a SmartMIPS core. The MIPSr3(TM)\nArchitecture now defines an optional feature to implement these\nTLB bits separately. Support for one or both features can be\nchecked by looking at the Config3.RXI bit.\n\nSigned-off-by: Steven J. Hill \u003csjhill@mips.com\u003e\nAcked-by: David Daney \u003cdavid.daney@cavium.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ca400f7c3f594944d31a7b1341b6aa04d7e4c757",
      "old_mode": 33188,
      "old_path": "arch/mips/include/asm/cpu-features.h",
      "new_id": "3af9aca65ab5d0e1098475a2078e6caa04547470",
      "new_mode": 33188,
      "new_path": "arch/mips/include/asm/cpu-features.h"
    },
    {
      "type": "modify",
      "old_id": "f21b7c04e95a2f70073e087e69d384e53d11862f",
      "old_mode": 33188,
      "old_path": "arch/mips/include/asm/cpu.h",
      "new_id": "1037d54f0597b8c6758943946c1bd8ad4bc666b6",
      "new_mode": 33188,
      "new_path": "arch/mips/include/asm/cpu.h"
    },
    {
      "type": "modify",
      "old_id": "7f87d824eeb089ca3be7aa4f56efa889ec98c40d",
      "old_mode": 33188,
      "old_path": "arch/mips/include/asm/mipsregs.h",
      "new_id": "4199dd3f8d549e3604b96b5029e47010d5fa203e",
      "new_mode": 33188,
      "new_path": "arch/mips/include/asm/mipsregs.h"
    },
    {
      "type": "modify",
      "old_id": "1b51046191e85a77dfb56aa284b96e66b035b083",
      "old_mode": 33188,
      "old_path": "arch/mips/kernel/cpu-probe.c",
      "new_id": "0beb75fb398090d5a7a4f9a458eb87a6b3edc539",
      "new_mode": 33188,
      "new_path": "arch/mips/kernel/cpu-probe.c"
    }
  ]
}