dt-bindings: Add binding for MT2712 MIPI-CSI2
Add MIPI-CSI2 dt-binding for Mediatek MT2712 SoC
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
diff --git a/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt b/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt
new file mode 100644
index 0000000..e30b6a4
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+++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt
@@ -0,0 +1,58 @@
+* Mediatek MIPI-CSI2 receiver
+
+Mediatek MIPI-CSI2 receiver is the MIPI Signal capture hardware present in Mediatek SoCs
+
+Required properties:
+- compatible: should be "mediatek,mt2712-mipicsi"
+- reg : physical base address of the mipicsi receiver registers and length of
+ memory mapped region.
+- power-domains: a phandle to the power domain, see
+ Documentation/devicetree/bindings/power/power_domain.txt for details.
+- mediatek,larb: must contain the local arbiters in the current Socs, see
+ Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+ for details.
+- iommus: should point to the respective IOMMU block with master port as
+ argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+ for details.
+- mediatek,seninf_mux_camsv: seninf_mux_camsv the data go through of the mipicsi port
+ any mipicsi port can contain max four seninf_mux_camsv
+ The Total seninf_mux_camsv is six for mt2712
+- mediatek,mipicsiid: the id of the mipicsi port, there are two port for mt2712
+- mediatek,mipicsi: the common component of the two mipicsi port
+- mediatek,mipicsi_max_vc: the number of virtual channel which subdev used
+- mediatek,serdes_link_reg: the register of subdev to get the link status
+
+Example:
+ mipicsi0: mipicsi@10217000 {
+ compatible = "mediatek,mt2712-mipicsi";
+ mediatek,mipicsi = <&mipicsi>;
+ iommus = <&iommu0 M4U_PORT_CAM_DMA0>,
+ <&iommu0 M4U_PORT_CAM_DMA1>;
+ mediatek,larb = <&larb2>;
+ power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>;
+
+ mediatek,seninf_mux_camsv = <&seninf1_mux_camsv0
+ &seninf2_mux_camsv1
+ &seninf3_mux_camsv2
+ &seninf4_mux_camsv3>;
+ reg = <0 0x10217000 0 0x60>,
+ <0 0x15002100 0 0x4>,
+ <0 0x15002300 0 0x100>;
+ mediatek,mipicsiid = <0>;
+ mediatek,mipicsi_max_vc = <4>;
+ mediatek,serdes_link_reg = <0x49>;
+ };
+
+ mipicsi1: mipicsi@10218000 {
+ compatible = "mediatek,mt2712-mipicsi";
+ mediatek,mipicsi = <&mipicsi>;
+ iommus = <&iommu0 M4U_PORT_CAM_DMA2>;
+ mediatek,larb = <&larb2>;
+ power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>;
+ mediatek,seninf_mux_camsv = <&seninf5_mux_camsv4
+ &seninf6_mux_camsv5>;
+ reg = <0 0x10218000 0 0x60>,
+ <0 0x15002500 0 0x4>,
+ <0 0x15002700 0 0x100>;
+ mediatek,mipicsiid = <1>;
+ };
