// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2019 MediaTek Inc.
 * Copyright (c) 2019 BayLibre, SAS.
 * Author: Fabien Parent <fparent@baylibre.com>
 */

#include <dt-bindings/clock/mt8167-clk.h>
#include <dt-bindings/power/mt8167-power.h>
#include <dt-bindings/memory/mt8167-larb-port.h>

#include "mt8167-pinfunc.h"

#include "mt8516.dtsi"

/ {
	compatible = "mediatek,mt8167";

	aliases {
		dpi1 = &dpi1;
		rdma1 = &rdma1;

		ovl0 = &ovl0;
		color0 = &color;
		ccorr0 = &ccorr;
		aal0 = &aal;
		dither0 = &dither;
		rdma0 = &rdma0;
		dsi0 = &dsi;

		pwm0 = &disp_pwm;

		mdp_rdma0 = &mdp_rdma;
		mdp_rsz0 = &mdp_rsz0;
		mdp_rsz1 = &mdp_rsz1;
		mdp_tdshp0 = &mdp_tdshp;
		mdp_wdma0 = &mdp_wdma;
		mdp_wrot0 = &mdp_wrot;
	};

	soc {
		scpsys: scpsys@10006000 {
			compatible = "mediatek,mt8516-scpsys", "mediatek,mt8167-scpsys", "syscon";
			#power-domain-cells = <1>;
			reg = <0 0x10006000 0 0x1000>;
			interrupts =	<GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>,
					<GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>,
					<GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>,
					<GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>;
			infracfg = <&infracfg>;
			clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
				 <&topckgen CLK_TOP_RG_SLOW_MFG>,
				 <&topckgen CLK_TOP_SMI_MM>,
				 <&topckgen CLK_TOP_RG_VDEC>;
			clock-names = "axi_mfg", "mfg", "mm", "vdec";
			mediatek,pwrap-regmap = <&pwrap>;
		};

		mmsys: mmsys@14000000 {
			compatible = "mediatek,mt8167-mmsys", "syscon";
			reg = <0 0x14000000 0 0x1000>;
			#clock-cells = <1>;
		};

		mmsys2: mmsys2@14000000 {
			compatible = "mediatek,mt8167-mmsys2", "syscon";
			reg = <0 0x14000000 0 0x1000>;
			#clock-cells = <1>;
		};

		imgsys: imgsys@15000000 {
			compatible = "mediatek,mt8167-imgsys", "syscon";
			reg = <0 0x15000000 0 0x1000>;
			#clock-cells = <1>;
		};

		vdecsys: syscon@16000000 {
			compatible = "mediatek,mt8167-vdecsys", "syscon";
			reg = <0 0x16000000 0 0x1000>;
			#clock-cells = <1>;
		};

		mutex: mutex@14015000 {
			compatible = "mediatek,mt8167-disp-mutex";
			reg = <0 0x14015000 0 0x1000>;
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MM>;
		};

		iommu: m4u@10203000 {
			cell-index = <0>;
			compatible = "mediatek,mt8167-m4u";
			reg = <0 0x10203000 0 0x1000>;
			mediatek,larbs = <&larb0 &larb1 &larb2>;
			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
			#iommu-cells = <1>;
		};

		mfg: clark@13000000 {
			compatible = "mediatek,mt8167-clark";
			reg = <0 0x13000000 0 0x80000>, <0 0x13ffe000 0 0x1000>;
			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
			interrupt-names = "RGX";
			power-domains =  <&scpsys MT8167_POWER_DOMAIN_MFG>;
			clocks = <&topckgen CLK_TOP_MFG_MM_SEL>,
				 <&topckgen CLK_TOP_AXI_MFG_IN_SEL>,
				 <&topckgen CLK_TOP_SLOW_MFG_SEL>,
				 <&topckgen CLK_TOP_RG_SLOW_MFG>,
				 <&topckgen CLK_TOP_RG_AXI_MFG>,
				 <&topckgen CLK_TOP_MFG_MM>,
				 <&topckgen CLK_TOP_CLK26M>,
				 <&topckgen CLK_TOP_UNIVPLL_D24>,
				 <&topckgen CLK_TOP_MAINPLL_D11>,
				 <&topckgen CLK_TOP_CSW_MUX_MFG_SEL>;
			clock-names = "mfg_mm_in_sel",
				      "mfg_axi_in_sel",
				      "mfg_slow_in_sel",
				      "top_slow",
				      "top_axi",
				      "top_mm",
				      "slow_clk26m",
				      "bus_univpll_d24",
				      "bus_mainpll_d11",
				      "engine_csw_mux";
			clock-frequency = <400000000>;
		};

		mfgcfg: mfgcfg@13ffe000 {
			compatible = "mediatek,mt8167-mfgcfg", "syscon";
			reg = <0 0x13ffe000 0 0x1000>;
			#clock-cells = <1>;
		};


		mfg_async: mfgsys-async {
			compatible = "mediatek,mt8167-mfg-async";
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MFG_ASYNC>;
		};

		mfg_2d: mfgsys-2d {
			compatible = "mediatek,mt8167-mfg-2d";
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MFG_2D>;
		};

		smi_common: smi@14017000 {
			compatible = "mediatek,mt8167-smi-common";
			reg = <0 0x14017000 0 0x1000>;
			clocks = <&mmsys CLK_MM_SMI_COMMON>,
				 <&mmsys CLK_MM_SMI_COMMON>;
			clock-names = "apb", "smi";
			power-domains = <&scpsys MT8167_POWER_DOMAIN_DISP>;
		};

		dpi1: dpi1@14019000 {
			compatible = "mediatek,mt8167-dpi", "hdmi-connector";
			reg = <0 0x14019000 0 0x1000>;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DPI1_PXL>,
				 <&mmsys CLK_MM_DPI1_ENGINE>,
				 <&apmixedsys CLK_APMIXED_TVDPLL>,
				 <&topckgen CLK_TOP_DPI1_MM_SEL>,
				 <&topckgen CLK_TOP_TVDPLL_D2>,
				 <&topckgen CLK_TOP_TVDPLL_D4>,
				 <&topckgen CLK_TOP_TVDPLL_D8>,
				 <&topckgen CLK_TOP_TVDPLL_D16>;
			clock-names = "pixel", "engine", "pll", "dpi_sel",
				      "tvd_d2", "tvd_d4", "tvd_d8", "tvd_d16";
			status = "disabled";
		};

		hdmiddc: i2c@11011000 {
			compatible = "mediatek,mt8167-hdmi-ddc",
				     "mediatek,mt8173-hdmi-ddc";
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
			reg = <0 0x11011000 0 0x10>;
			clocks = <&topckgen CLK_TOP_26M_HDMI_SIFM>;
			clock-names = "ddc-i2c";
		};

		hdmi_phy: hdmi-phy@10018300 {
			compatible = "mediatek,mt8167-hdmi-phy";
			reg = <0 0x10018300 0 0x20>;
			clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
			clock-names = "pll_ref";
			clock-output-names = "hdmtx_dig_cts";
			mediatek,ibias = <0xa>;
			mediatek,ibias_up = <0x1c>;
			#clock-cells = <0>;
			#phy-cells = <0>;
			status = "disabled";
		};

		hdmi: hdmi@1401b000 {
			compatible = "mediatek,mt8167-hdmi";
			reg = <0 0x1401b000 0 0x1000>;
			clocks = <&mmsys CLK_MM_HDMI_PXL>,
				 <&mmsys CLK_MM_HDMI_PLL>,
				 <&mmsys CLK_MM_HDMI_ADSP_BCK>,
				 <&mmsys CLK_MM_HDMI_SPDIF>;
			clock-names = "pixel", "pll", "bclk", "spdif";
			pinctrl-names = "default";
			pinctrl-0 = <&hdmi_pin>;
			phys = <&hdmi_phy>;
			phy-names = "hdmi";
			mediatek,syscon-hdmi = <&mmsys 0x100>;
			cec = <&cec>;
			ddc-i2c-bus = <&hdmiddc>;
			status = "disabled";
		};

		cec: cec@0x1001a000 {
			compatible = "mediatek,mt8167-cec",
				     "mediatek,mt8173-cec";
			reg = <0 0x1001a000 0 0xbc>;
			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&topckgen CLK_TOP_26M_CEC>;
			gpio-base = <&syscfg_pctl_a>;
			status = "disabled";
		};

		larb0: larb@14016000 {
			compatible = "mediatek,mt8167-smi-larb";
			reg = <0 0x14016000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			mediatek,larbid = <0>;
			clocks = <&mmsys CLK_MM_SMI_LARB0>,
				 <&mmsys CLK_MM_SMI_LARB0>;
			clock-names = "apb", "smi";
			power-domains = <&scpsys MT8167_POWER_DOMAIN_DISP>;
		};

		larb1: larb@15001000 {
			compatible = "mediatek,mt8167-smi-larb";
			reg = <0 0x15001000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			mediatek,larbid = <1>;
			clocks = <&imgsys CLK_IMG_LARB1_SMI>,
				 <&imgsys CLK_IMG_LARB1_SMI>;
			clock-names = "apb", "smi";
			power-domains = <&scpsys MT8167_POWER_DOMAIN_ISP>;
		};

		larb2: larb@16010000 {
			compatible = "mediatek,mt8167-smi-larb";
			reg = <0 0x16010000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			mediatek,larbid = <2>;
			clocks = <&vdecsys CLK_VDEC_CKEN>,
				 <&vdecsys CLK_VDEC_LARB1_CKEN>;
			clock-names = "apb", "smi";
			power-domains = <&scpsys MT8167_POWER_DOMAIN_VDEC>;
		};

		rdma1: rdma1@1400a000 {
			compatible = "mediatek,mt2701-disp-rdma";
			reg = <0 0x1400a000 0 0x1000>;
			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
			iommus = <&iommu M4U_PORT_DISP_RDMA1>;
			mediatek,larb = <&larb0>;
		};

		disp_pwm: disp_pwm@1100f000 {
			compatible = "mediatek,mt8167-disp-pwm";
			reg = <0 0x1100f000 0 0x1000>;
			#pwm-cells = <2>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MM>;
			clocks = <&topckgen CLK_TOP_PWM_SEL>,
				 <&topckgen CLK_TOP_PWM_MM>,
				  <&mmsys CLK_MM_DISP_PWM_26M>,
				  <&mmsys CLK_MM_DISP_PWM_MM>;
			clock-names = "pwm_sel",
				      "pwm_mm",
				      "main",
				      "mm";
			status = "disabled";
		};

		dsi: dsi@14012000 {
			compatible = "mediatek,mt8167-dsi";
			reg = <0 0x14012000 0 0x1000>;
			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DSI_ENGINE>,
				 <&mmsys CLK_MM_DSI_DIGITAL>,
				 <&topckgen CLK_TOP_MIPI_26M_DBG>,
				 <&mipi_tx>;
			clock-names = "engine", "digital", "mipi26mdbg", "hs";
			phys = <&mipi_tx>;
			phy-names = "dphy";
			status = "disabled";
		};

		mipi_tx: mipi_dphy@14018000 {
			compatible = "mediatek,mt8167-mipi-tx";
			reg = <0 0x14018000 0 0x90>;
			clocks = <&clk26m>;
			clock-output-names = "mipi_tx0_pll";
			#clock-cells = <0>;
			#phy-cells = <0>;
			status = "disabled";
		};

		ovl0: disp_ovl0@14007000 {
			compatible = "mediatek,mt8167-disp-ovl";
			reg = <0 0x14007000 0 0x1000>;
			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_OVL0>;
			iommus = <&iommu M4U_PORT_DISP_OVL0>;
			mediatek,larb = <&larb0>;
		};

		rdma0: disp_rdma0@14009000 {
			compatible = "mediatek,mt2701-disp-rdma";
			reg = <0 0x14009000 0 0x1000>;
			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
			iommus = <&iommu M4U_PORT_DISP_RDMA0>;
			mediatek,larb = <&larb0>;
		};

		color: disp_color@1400c000 {
			compatible = "mediatek,mt8167-disp-color";
			reg = <0 0x1400c000 0 0x1000>;
			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_COLOR>;
		};

		ccorr: disp_ccorr@1400d000 {
			compatible = "mediatek,mt8167-disp-ccorr";
			reg = <0 0x1400d000 0 0x1000>;
			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_CCORR>;
		};

		aal: disp_aal@1400e000 {
			compatible = "mediatek,mt8167-disp-aal";
			reg = <0 0x1400e000 0 0x1000>;
			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_AAL>;
		};

		gamma: disp_gamma@1400f000 {
			compatible = "mediatek,mt8167-disp-gamma";
			reg = <0 0x1400f000 0 0x1000>;
			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_GAMMA>;
		};

		dither: disp_dither@14010000 {
			compatible = "mediatek,mt8167-disp-dither";
			reg = <0 0x14010000 0 0x1000>;
			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_DITHER>;
		};

		gce: gce@1020a000 {
			compatible = "mediatek,mt8167-gce",
				     "mediatek,mt8173-gce";
			reg = <0 0x1020a000 0 0x900>;
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&topckgen CLK_TOP_GCE>;
			clock-names = "gce";

			#mbox-cells = <3>;
			#subsys-cells = <3>;
		};

		vcu: vcu@0 {
			compatible = "mediatek,mt8167-vcu";
			mediatek,vcuid = <0>;
			mediatek,vcuname = "vpu";
			reg = <0 0x16000000 0 0x40000>,	/* VDEC_BASE */
			      <0 0x15009000 0 0x1000>,	/* VENC_BASE */
			      <0 0x19002000 0 0x1000>;	/* VENC_LT_BASE */
			iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>;
		};

		mdp_vcu: vcu@1 {
			compatible = "mediatek,mt8167-vcu";
			mediatek,vcuid = <1>;
			mediatek,vcuname = "vpu1";
			iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>;
		};

		mdp_rdma: rdma@14001000 {
			compatible = "mediatek,mt8167-mdp-rdma",
				     "mediatek,mt8167-mdp";
			reg = <0 0x14001000 0 0x1000>;
			mediatek,mdpid = <0>;
			clocks = <&mmsys CLK_MM_MDP_RDMA>,
				 <&mmsys CLK_MM_MDP_RDMA>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MM>;
			iommus = <&iommu M4U_PORT_MDP_RDMA>;
			mediatek,larb = <&larb0>;
			mediatek,vpu = <&mdp_vcu>;
			mediatek,gce = <&gce>;
			mboxes = <&gce 0 0 1>;
		};

		mdp_rsz0: rsz@14002000 {
			compatible = "mediatek,mt8167-mdp-rsz";
			reg = <0 14002000 0 0x1000>;
			clocks = <&mmsys CLK_MM_MDP_RSZ0>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MM>;
		};

		mdp_rsz1: rsz@14003000 {
			compatible = "mediatek,mt8167-mdp-rsz";
			reg = <0 14003000 0 0x1000>;
			clocks = <&mmsys CLK_MM_MDP_RSZ1>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MM>;
		};

		mdp_wdma: wdma@14004000 {
			compatible = "mediatek,mt8167-mdp-wdma";
			reg = <0 14004000 0 0x1000>;
			clocks = <&mmsys CLK_MM_MDP_WDMA>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MM>;
			iommus = <&iommu M4U_PORT_MDP_WDMA>;
			mediatek,larb = <&larb0>;
		};

		mdp_wrot: wrot@14005000 {
			compatible = "mediatek,mt8167-mdp-wrot";
			reg = <0 14005000 0 0x1000>;
			clocks = <&mmsys CLK_MM_MDP_WROT>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MM>;
			iommus = <&iommu M4U_PORT_MDP_WROT>;
			mediatek,larb = <&larb0>;
		};

		mdp_tdshp: tdshp@14006000 {
			compatible = "mediatek,mt8167-mdp-tdshp";
			reg = <0 14006000 0 0x1000>;
			clocks = <&mmsys CLK_MM_MDP_TDSHP>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_MM>;
		};

		vcodec_dec: codec@16000000 {
			compatible = "mediatek,mt8167-vcodec-dec";
			reg = <0 0x16000000 0 0x100>,		/* VDEC_SYS */
			      <0 0x16025000 0 0x1000>,		/* VDEC_MISC */
			      <0 0x16020000 0 0x800>,		/* VDEC_LD */
			      <0 0x16020800 0 0x800>,		/* VDEC_TOP */
			      <0 0x16021000 0 0x1000>,		/* VDEC_CM */
			      <0 0x16022000 0 0x1000>,		/* VDEC_AD */
			      <0 0x16023000 0 0x1000>,		/* VDEC_AV */
			      <0 0x16024000 0 0x1000>,		/* VDEC_PP */
			      <0 0x16026800 0 0x800>,		/* VP8_VD */
			      <0 0x16026000 0 0x800>,		/* VP6_VD */
			      <0 0x16027800 0 0x800>,		/* VP8_VL */
			      <0 0x16028000 0 0x400>,		/* HEVC_VD */
			      <0 0x16028400 0 0x400>,		/* VP9_VD */
			      <0 0x16030000 0 0x1000>;		/* IMAGE_RESZ */
			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
			mediatek,larb = <&larb2>;
			iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
				 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
				 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
				 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
				 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
				 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
				 <&iommu M4U_PORT_HW_VDEC_PPWRAP_EXT>;
			mediatek,vpu = <&vcu>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_VDEC>;
			clocks = <&topckgen CLK_TOP_VDEC_MM_SEL>,
			      <&topckgen CLK_TOP_UNIVPLL_D4>;
			clock-names = "vdec_sel",
			      "normal";
		};

		seninf1_mux_camsv0: seninf_mux_camsv@15004000 {
			reg = <0 0x15008120 0 0x40>, //seninf_mux
				  <0 0x15004000 0 0x1000>, //cam
				  <0 0x15008200 0 0x20>; //seninf_TG
			reg-names = "seninf_mux",
						"camsv",
						"seninf_TG";
			clocks = <&imgsys CLK_IMG_SEN_TG>; //?
			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; //<GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; //183:seninf
		};

		mipicsi: mipicsi@15008000 {
			compatible = "mediatek,mt8167s-mipicsi-common", "syscon"; //?
			reg = <0 0x15008000 0 0x10>;
			reg-names = "seninf_top";
			clocks =  
				  <&topckgen CLK_TOP_UNIVPLL_D4>,
				  <&topckgen CLK_TOP_SMI_MM_SEL>,
				  <&topckgen CLK_TOP_CAMTG_MM_SEL>,
				  <&topckgen CLK_TOP_USB_PHY48M>,
				  <&topckgen CLK_TOP_UNIVPLL_D6>,
				  <&imgsys CLK_IMG_LARB1_SMI>,
				  <&imgsys CLK_IMG_CAM_SMI>,
				  <&imgsys CLK_IMG_CAM_CAM>,
				  <&imgsys CLK_IMG_SEN_TG>,
				  <&imgsys CLK_IMG_SEN_CAM>,
				  <&mmsys CLK_MM_SMI_COMMON>,
				  <&topckgen CLK_TOP_CAM_MM>,
				  <&topckgen CLK_TOP_MIPI_26M>,
				  <&topckgen CLK_TOP_MIPI_26M_DBG>,
				  <&topckgen CLK_TOP_MFG_MM>,
				  <&mmsys CLK_MM_CAM_MDP>;
			clock-names = 
					"TOP_UNIVPLL_D4",
					"TOP_SMI_MM_SEL",
					  "top_camtg_sel",
				      "TOP_CAM_TG_48M",  /* 48M */
				      "TOP_CAM_TG_208M",  /* 208M, divided in setTgPhase */
					  "img_larb1_smi",
					  "img_cam_smi",
					  "img_cam_cam",
					  "img_sen_tg",
					  "img_sen_cam",
					  "img_venc",
					  "top_cam",
					  "mipi",
					  "mipi_dbg",
					  "mfg_mm",
					  "cam_mdp";
			assigned-clocks = <&topckgen CLK_TOP_SMI_MM_SEL>;
			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
		};

		mipicsi0: mipicsi@10011800 {
			compatible = "mediatek,mt8167s-mipicsi";
			mediatek,mipicsi = <&mipicsi>;
			iommus = <&iommu M4U_PORT_CAM_IMGO>; //?
			mediatek,larb = <&larb1>;
			power-domains = <&scpsys MT8167_POWER_DOMAIN_ISP>;

			mediatek,seninf_mux_camsv = <&seninf1_mux_camsv0>;
			reg = <0 0x10011800 0 0x60>,  // (ana)
				  <0 0x15008100 0 0x4>, // (seninf_ctrl)
				  <0 0x15008300 0 0x100>; // (seninf)
			reg-names = "mipi_rx_config",
						"seninf",
						"ncsi2";
			mediatek,mipicsiid = <0>;
			status="okay";
		};

	};
};

&topckgen {
	compatible = "mediatek,mt8167-topckgen",
		     "mediatek,mt8516-topckgen", "syscon";
	reg = <0 0x10000000 0 0x1000>;
	#clock-cells = <1>;
};

&infracfg {
	compatible = "mediatek,mt8167-infracfg",
		     "mediatek,mt8516-infracfg", "syscon";
	reg = <0 0x10001000 0 0x1000>;
	#clock-cells = <1>;
};

&apmixedsys {
	compatible = "mediatek,mt8167-apmixedsys",
		     "mediatel,mt8516-apmixedsys", "syscon";
	reg = <0 0x10018000 0 0x710>;
	#clock-cells = <1>;
};

&syscfg_pctl_a {
	compatible = "mediatek,mt8167-pctl-a-syscfg",
		     "mediatek,mt8516-pctl-a-syscfg", "syscon";
	reg = <0 0x10005000 0 0x1000>;
};

&pio {
	compatible = "mediatek,mt8167-pinctrl", "mediatek,mt8516-pinctrl";
	reg = <0 0x1000b000 0 0x1000>;
	mediatek,pctl-regmap = <&syscfg_pctl_a>;
	pins-are-numbered;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;

	hdmi_pin: htplg {
		pins_cmd_dat {
			pinmux = <MT8167_PIN_122_HTPLG__FUNC_HTPLG>;
			input-enable;
			bias-pull-down;
		};
	};

	camera_default: camera_interposer_default {
		pins_camera {
			pinmux = <MT8167_PIN_84_RDN0__FUNC_RDN0>,
				<MT8167_PIN_85_RDP0__FUNC_RDP0>,
				<MT8167_PIN_86_RDN1__FUNC_RDN1>,
				<MT8167_PIN_87_RDP1__FUNC_RDP1>,
				<MT8167_PIN_88_RCN__FUNC_RCN>,
				<MT8167_PIN_89_RCP__FUNC_RCP>,
				<MT8167_PIN_90_RDN2__FUNC_RDN2>,
				<MT8167_PIN_91_RDP2__FUNC_RDP2>,
				<MT8167_PIN_92_RDN3__FUNC_RDN3>,
				<MT8167_PIN_93_RDP3__FUNC_RDP3>,
				<MT8167_PIN_94_RCN_A__FUNC_RCN_A>,
				<MT8167_PIN_95_RCP_A__FUNC_RCP_A>,
				<MT8167_PIN_96_RDN1_A__FUNC_RDN1_A>,
				<MT8167_PIN_97_RDP1_A__FUNC_RDP1_A>,
				<MT8167_PIN_98_RDN0_A__FUNC_RDN0_A>,
				<MT8167_PIN_99_RDP0_A__FUNC_RDP0_A>,
				<MT8167_PIN_102_CMMCLK__FUNC_CMMCLK>;
		};
	};

};