| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (c) 2019 MediaTek Inc. |
| * Copyright (c) 2019 BayLibre, SAS. |
| * Author: Fabien Parent <fparent@baylibre.com> |
| */ |
| |
| #include <dt-bindings/clock/mt8516-clk.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/phy/phy.h> |
| |
| #include "mt8516-pinfunc.h" |
| |
| / { |
| compatible = "mediatek,mt8516"; |
| interrupt-parent = <&sysirq>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cluster0_opp: opp_table0 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| opp-598000000 { |
| opp-hz = /bits/ 64 <598000000>; |
| opp-microvolt = <1150000>; |
| }; |
| opp-747500000 { |
| opp-hz = /bits/ 64 <747500000>; |
| opp-microvolt = <1150000>; |
| }; |
| opp-1040000000 { |
| opp-hz = /bits/ 64 <1040000000>; |
| opp-microvolt = <1200000>; |
| }; |
| opp-1196000000 { |
| opp-hz = /bits/ 64 <1196000000>; |
| opp-microvolt = <1250000>; |
| }; |
| opp-1300000000 { |
| opp-hz = /bits/ 64 <1300000000>; |
| opp-microvolt = <1300000>; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a35"; |
| reg = <0x0>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, |
| <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; |
| clocks = <&infracfg CLK_IFR_MUX1_SEL>, |
| <&topckgen CLK_TOP_MAINPLL_D2>, |
| <&apmixedsys CLK_APMIXED_ARMPLL>; |
| clock-names = "cpu", "intermediate", "armpll"; |
| #cooling-cells = <2>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a35"; |
| reg = <0x1>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, |
| <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; |
| clocks = <&infracfg CLK_IFR_MUX1_SEL>, |
| <&topckgen CLK_TOP_MAINPLL_D2>, |
| <&apmixedsys CLK_APMIXED_ARMPLL>; |
| clock-names = "cpu", "intermediate", "armpll"; |
| #cooling-cells = <2>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| |
| cpu2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a35"; |
| reg = <0x2>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, |
| <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; |
| clocks = <&infracfg CLK_IFR_MUX1_SEL>, |
| <&topckgen CLK_TOP_MAINPLL_D2>, |
| <&apmixedsys CLK_APMIXED_ARMPLL>; |
| clock-names = "cpu", "intermediate", "armpll"; |
| #cooling-cells = <2>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| |
| cpu3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a35"; |
| reg = <0x3>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, |
| <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; |
| clocks = <&infracfg CLK_IFR_MUX1_SEL>, |
| <&topckgen CLK_TOP_MAINPLL_D2>, |
| <&apmixedsys CLK_APMIXED_ARMPLL>; |
| clock-names = "cpu", "intermediate", "armpll"; |
| #cooling-cells = <2>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| |
| idle-states { |
| entry-method = "psci"; |
| |
| CPU_SLEEP_0_0: cpu-sleep-0-0 { |
| compatible = "arm,idle-state"; |
| entry-latency-us = <600>; |
| exit-latency-us = <600>; |
| min-residency-us = <1200>; |
| arm,psci-suspend-param = <0x0010000>; |
| }; |
| |
| CLUSTER_SLEEP_0: cluster-sleep-0 { |
| compatible = "arm,idle-state"; |
| entry-latency-us = <800>; |
| exit-latency-us = <1000>; |
| min-residency-us = <2000>; |
| arm,psci-suspend-param = <0x2010000>; |
| }; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; |
| method = "smc"; |
| }; |
| |
| clk26m: clk26m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <26000000>; |
| clock-output-names = "clk26m"; |
| }; |
| |
| clk32k: clk32k { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32000>; |
| clock-output-names = "clk32k"; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ |
| bl31_secmon_reserved: secmon@43000000 { |
| no-map; |
| reg = <0 0x43000000 0 0x20000>; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 13 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| |
| pmu { |
| compatible = "arm,armv8-pmuv3"; |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>; |
| interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; |
| }; |
| |
| soc { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| compatible = "simple-bus"; |
| ranges; |
| |
| topckgen: topckgen@10000000 { |
| compatible = "mediatek,mt8516-topckgen", "syscon"; |
| reg = <0 0x10000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| infracfg: infracfg@10001000 { |
| compatible = "mediatek,mt8516-infracfg", "syscon"; |
| reg = <0 0x10001000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| apmixedsys: apmixedsys@10018000 { |
| compatible = "mediatek,mt8516-apmixedsys", "syscon"; |
| reg = <0 0x10018000 0 0x710>; |
| #clock-cells = <1>; |
| }; |
| |
| toprgu: toprgu@10007000 { |
| compatible = "mediatek,mt8516-wdt", |
| "mediatek,mt6589-wdt"; |
| reg = <0 0x10007000 0 0x1000>; |
| interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>; |
| #reset-cells = <1>; |
| }; |
| |
| timer: timer@10008000 { |
| compatible = "mediatek,mt8516-timer", |
| "mediatek,mt6577-timer"; |
| reg = <0 0x10008000 0 0x1000>; |
| interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_CLK26M_D2>, |
| <&clk32k>, |
| <&topckgen CLK_TOP_APXGPT>; |
| clock-names = "clk13m", "clk32k", "bus"; |
| }; |
| |
| syscfg_pctl_a: syscfg_pctl_a@10005000 { |
| compatible = "mediatek,mt8516-pctl-a-syscfg", "syscon"; |
| reg = <0 0x10005000 0 0x1000>; |
| }; |
| |
| pio: pinctrl@10005000 { |
| compatible = "mediatek,mt8516-pinctrl"; |
| reg = <0 0x1000b000 0 0x1000>; |
| mediatek,pctl-regmap = <&syscfg_pctl_a>; |
| pins-are-numbered; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pwrap: pwrap@1000f000 { |
| compatible = "mediatek,mt8516-pwrap"; |
| reg = <0 0x1000f000 0 0x1000>; |
| reg-names = "pwrap"; |
| interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_PMICWRAP_26M>, |
| <&topckgen CLK_TOP_PMICWRAP_AP>; |
| clock-names = "spi", "wrap"; |
| }; |
| |
| sysirq: intpol-controller@10200620 { |
| compatible = "mediatek,mt8516-sysirq", |
| "mediatek,mt6577-sysirq"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupt-parent = <&gic>; |
| reg = <0 0x10200620 0 0x20>; |
| }; |
| |
| gic: interrupt-controller@10310000 { |
| compatible = "arm,gic-400"; |
| #interrupt-cells = <3>; |
| interrupt-parent = <&gic>; |
| interrupt-controller; |
| reg = <0 0x10310000 0 0x1000>, |
| <0 0x10320000 0 0x1000>, |
| <0 0x10340000 0 0x2000>, |
| <0 0x10360000 0 0x2000>; |
| interrupts = <GIC_PPI 9 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| uart0: serial@11005000 { |
| compatible = "mediatek,mt8516-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11005000 0 0x1000>; |
| interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_UART0_SEL>, |
| <&topckgen CLK_TOP_UART0>; |
| clock-names = "baud","bus"; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@11006000 { |
| compatible = "mediatek,mt8516-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11006000 0 0x1000>; |
| interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_UART1_SEL>, |
| <&topckgen CLK_TOP_UART1>; |
| clock-names = "baud","bus"; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@11007000 { |
| compatible = "mediatek,mt8516-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11007000 0 0x1000>; |
| interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_UART2_SEL>, |
| <&topckgen CLK_TOP_UART2>; |
| clock-names = "baud","bus"; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@11009000 { |
| compatible = "mediatek,mt8516-i2c", |
| "mediatek,mt2712-i2c"; |
| reg = <0 0x11009000 0 0x90>, |
| <0 0x11000180 0 0x80>; |
| interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, |
| <&infracfg CLK_IFR_I2C0_SEL>, |
| <&topckgen CLK_TOP_I2C0>, |
| <&topckgen CLK_TOP_APDMA>; |
| clock-names = "main-source", |
| "main-sel", |
| "main", |
| "dma"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@1100a000 { |
| compatible = "mediatek,mt8516-i2c", |
| "mediatek,mt2712-i2c"; |
| reg = <0 0x1100a000 0 0x90>, |
| <0 0x11000200 0 0x80>; |
| interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, |
| <&infracfg CLK_IFR_I2C1_SEL>, |
| <&topckgen CLK_TOP_I2C1>, |
| <&topckgen CLK_TOP_APDMA>; |
| clock-names = "main-source", |
| "main-sel", |
| "main", |
| "dma"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@1100b000 { |
| compatible = "mediatek,mt8516-i2c", |
| "mediatek,mt2712-i2c"; |
| reg = <0 0x1100b000 0 0x90>, |
| <0 0x11000280 0 0x80>; |
| interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, |
| <&infracfg CLK_IFR_I2C2_SEL>, |
| <&topckgen CLK_TOP_I2C2>, |
| <&topckgen CLK_TOP_APDMA>; |
| clock-names = "main-source", |
| "main-sel", |
| "main", |
| "dma"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi: spi@1100c000 { |
| compatible = "mediatek,mt8516-spi", |
| "mediatek,mt2712-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x1100c000 0 0x1000>; |
| interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_UNIVPLL_D12>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&topckgen CLK_TOP_SPI>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| mmc0: mmc@11120000 { |
| compatible = "mediatek,mt8516-mmc"; |
| reg = <0 0x11120000 0 0x1000>; |
| interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_MSDC0>, |
| <&topckgen CLK_TOP_AHB_INFRA_SEL>, |
| <&topckgen CLK_TOP_MSDC0_INFRA>; |
| clock-names = "source", "hclk", "source_cg"; |
| status = "disabled"; |
| }; |
| |
| mmc1: mmc@11130000 { |
| compatible = "mediatek,mt8516-mmc"; |
| reg = <0 0x11130000 0 0x1000>; |
| interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_AHB_INFRA_SEL>, |
| <&topckgen CLK_TOP_MSDC1>, |
| <&topckgen CLK_TOP_MSDC1_INFRA>; |
| clock-names = "source", "hclk", "source_cg"; |
| status = "disabled"; |
| }; |
| |
| mmc2: mmc@11170000 { |
| compatible = "mediatek,mt8516-mmc"; |
| reg = <0 0x11170000 0 0x1000>; |
| interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_MSDC2>, |
| <&topckgen CLK_TOP_RG_MSDC2>, |
| <&topckgen CLK_TOP_MSDC2_INFRA>; |
| clock-names = "source", "hclk", "source_cg"; |
| status = "disabled"; |
| }; |
| |
| ethernet: ethernet@11180000 { |
| compatible = "mediatek,mt8516-ethernet"; |
| reg = <0 0x11180000 0 0x1000>, |
| <0 0x10003400 0 0x1000>; |
| interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_RG_ETH>, |
| <&topckgen CLK_TOP_66M_ETH>, |
| <&topckgen CLK_TOP_133M_ETH>; |
| clock-names = "core", "reg", "trans"; |
| status = "disabled"; |
| }; |
| |
| usb0: usb@11100000 { |
| compatible = "mediatek,mt8516-musb", |
| "mediatek,mtk-musb"; |
| reg = <0 0x11100000 0 0x1000>; |
| interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; |
| interrupt-names = "mc"; |
| phys = <&usb0_port PHY_TYPE_USB2>; |
| clocks = <&topckgen CLK_TOP_USB>, |
| <&topckgen CLK_TOP_USBIF>, |
| <&topckgen CLK_TOP_USB_1P>; |
| clock-names = "main","mcu","univpll"; |
| status = "disabled"; |
| }; |
| |
| usb0_phy: usb@11110000 { |
| compatible = "mediatek,generic-tphy-v1"; |
| reg = <0 0x11110000 0 0x800>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| status = "disabled"; |
| |
| usb0_port: usb-phy@11110800{ |
| reg = <0 0x11110800 0 0x100>; |
| clocks = <&topckgen CLK_TOP_USB_PHY48M>; |
| clock-names = "ref"; |
| #phy-cells = <1>; |
| }; |
| }; |
| |
| usb1: usb@11190000 { |
| compatible = "mediatek,mt8167-usb11"; |
| cell-index = <1>; |
| reg = <0 0x11190000 0 0x10000>, |
| <0 0x11110000 0 0x10000>; |
| interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_LOW>; |
| mode = <2>; |
| multipoint = <1>; |
| dyn_fifo = <1>; |
| soft_con = <1>; |
| dma = <1>; |
| num_eps = <8>; |
| dma_channels = <4>; |
| status = "disabled"; |
| }; |
| |
| afe: audio-controller@11140000 { |
| compatible = "mediatek,mt8167-afe-pcm"; |
| #sound-dai-cells = <0>; |
| reg = <0 0x11140000 0 0x1000>, |
| <0 0x11141000 0 0x9000>; |
| interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_AUDIO>, |
| <&topckgen CLK_TOP_APLL12_DIV0>, |
| <&topckgen CLK_TOP_APLL12_DIV1>, |
| <&topckgen CLK_TOP_APLL12_DIV2>, |
| <&topckgen CLK_TOP_APLL12_DIV3>, |
| <&topckgen CLK_TOP_APLL12_DIV4>, |
| <&topckgen CLK_TOP_APLL12_DIV4B>, |
| <&topckgen CLK_TOP_APLL12_DIV5>, |
| <&topckgen CLK_TOP_APLL12_DIV5B>, |
| <&topckgen CLK_TOP_APLL12_DIV6>, |
| <&topckgen CLK_TOP_RG_AUD_SPDIF_IN>, |
| <&topckgen CLK_TOP_RG_AUD_ENGEN1>, |
| <&topckgen CLK_TOP_RG_AUD_ENGEN2>, |
| <&topckgen CLK_TOP_RG_AUD1>, |
| <&topckgen CLK_TOP_RG_AUD2>, |
| <&topckgen CLK_TOP_AUD_I2S0_M_SEL>, |
| <&topckgen CLK_TOP_AUD_I2S1_M_SEL>, |
| <&topckgen CLK_TOP_AUD_I2S2_M_SEL>, |
| <&topckgen CLK_TOP_AUD_I2S3_M_SEL>, |
| <&topckgen CLK_TOP_AUD_I2S4_M_SEL>, |
| <&topckgen CLK_TOP_AUD_I2S5_M_SEL>, |
| <&topckgen CLK_TOP_AUD_SPDIF_B_SEL>, |
| <&topckgen CLK_TOP_AUD_SPDIFIN_SEL>, |
| <&topckgen CLK_TOP_UNIVPLL_D2>; |
| clock-names = "top_pdn_audio", |
| "apll12_div0", |
| "apll12_div1", |
| "apll12_div2", |
| "apll12_div3", |
| "apll12_div4", |
| "apll12_div4b", |
| "apll12_div5", |
| "apll12_div5b", |
| "apll12_div6", |
| "spdif_in", |
| "engen1", |
| "engen2", |
| "aud1", |
| "aud2", |
| "i2s0_m_sel", |
| "i2s1_m_sel", |
| "i2s2_m_sel", |
| "i2s3_m_sel", |
| "i2s4_m_sel", |
| "i2s5_m_sel", |
| "spdif_b_sel", |
| "spdifin_sel", |
| "univpll_div2"; |
| assigned-clocks = <&topckgen CLK_TOP_AUD1_SEL>, |
| <&topckgen CLK_TOP_AUD2_SEL>, |
| <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, |
| <&topckgen CLK_TOP_AUD_ENGEN2_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, |
| <&topckgen CLK_TOP_APLL2>, |
| <&topckgen CLK_TOP_RG_APLL1_D8_EN>, |
| <&topckgen CLK_TOP_RG_APLL2_D8_EN>; |
| }; |
| |
| xo: xo@10210000 { |
| compatible = "mediatek,mt8167-xo"; |
| reg = <0 0x10210000 0 0x1000>; |
| default_capid = <0x00>; |
| clocks = <&topckgen CLK_TOP_BSI>, |
| <&topckgen CLK_TOP_RG_BSI>, |
| <&topckgen CLK_TOP_BSI_SEL>, |
| <&topckgen CLK_TOP_CLK26M>; |
| clock-names = "bsi", |
| "rgbsi", |
| "bsisel", |
| "clk26m"; |
| }; |
| |
| pwm: pwm@11008000 { |
| compatible = "mediatek,mt8516-pwm"; |
| reg = <0 0x11008000 0 0x1000>; |
| interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_PWM>, |
| <&topckgen CLK_TOP_PWM_B>, |
| <&topckgen CLK_TOP_PWM1_FB>, |
| <&topckgen CLK_TOP_PWM2_FB>, |
| <&topckgen CLK_TOP_PWM3_FB>, |
| <&topckgen CLK_TOP_PWM4_FB>, |
| <&topckgen CLK_TOP_PWM5_FB>; |
| clock-names = "top", "main", "pwm1", "pwm2", "pwm3", |
| "pwm4", "pwm5"; |
| }; |
| |
| rng: rng@1020c000 { |
| compatible = "mediatek,mt8516-rng", |
| "mediatek,mt7623-rng"; |
| reg = <0 0x1020c000 0 0x100>; |
| clocks = <&topckgen CLK_TOP_TRNG>; |
| clock-names = "rng"; |
| }; |
| }; |
| }; |
