/* SPDX-License-Identifier: GPL-2.0 */
/*
 * tlv320adc3101.h
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */


#ifndef _TLV320ADC3101_H
#define _TLV320ADC3101_H

struct device;
struct regmap_config;

extern const struct regmap_config adc3101_regmap_config;
int adc3101_probe(struct device *dev, struct regmap *regmap);
int adc3101_remove(struct device *dev);

/* tlv320adc3101 register space */

#define ADC3101_REG(page, reg)	((page * 128) + reg)

#define	ADC3101_PSEL			ADC3101_REG(0, 0)
#define	ADC3101_RESET			ADC3101_REG(0, 1)
#define	ADC3101_CLKMUX			ADC3101_REG(0, 4)
#define	ADC3101_PLLPR			ADC3101_REG(0, 5)
#define	ADC3101_PLLJ			ADC3101_REG(0, 6)
#define	ADC3101_PLLDMSB			ADC3101_REG(0, 7)
#define	ADC3101_PLLDLSB			ADC3101_REG(0, 8)
#define	ADC3101_NADC			ADC3101_REG(0, 18)
#define	ADC3101_MADC			ADC3101_REG(0, 19)
#define ADC3101_AOSR			ADC3101_REG(0, 20)
#define ADC3101_CLKMUX2			ADC3101_REG(0, 25)
#define ADC3101_CLKOUTM			ADC3101_REG(0, 26)
#define ADC3101_IFACE1			ADC3101_REG(0, 27)
#define ADC3101_CH_OFFSET_1		ADC3101_REG(0, 28)
#define ADC3101_IFACE2			ADC3101_REG(0, 29)
#define ADC3101_I2S_SYNC		ADC3101_REG(0, 34)
#define ADC3101_CH_OFFSET_2		ADC3101_REG(0, 37)
#define ADC3101_I2S_TDM			ADC3101_REG(0, 38)
#define ADC3101_ADC_DIGITAL		ADC3101_REG(0, 81)
#define ADC3101_FADCVOL			ADC3101_REG(0, 82)
#define ADC3101_LADCVOL			ADC3101_REG(0, 83)
#define ADC3101_RADCVOL			ADC3101_REG(0, 84)
#define ADC3101_LAGCMAX			ADC3101_REG(0, 88)
#define ADC3101_RAGCMAX			ADC3101_REG(0, 96)
#define ADC3101_MICBIAS			ADC3101_REG(1, 51)
#define ADC3101_LPGAPIN			ADC3101_REG(1, 52)
#define ADC3101_LPGAPIN2		ADC3101_REG(1, 54)
#define ADC3101_RPGAPIN			ADC3101_REG(1, 55)
#define ADC3101_RPGAPIN2		ADC3101_REG(1, 57)
#define ADC3101_LAPGAVOL		ADC3101_REG(1, 59)
#define ADC3101_RAPGAVOL		ADC3101_REG(1, 60)
#define ADC3101_APGAFLAGS		ADC3101_REG(1, 62)

/* Bits, masks, and shifts */

/*  ADC3101_RESET */
#define	ADC3101_RESET_VALUE				0x01

/* ADC3101_CLKMUX */
#define ADC3101_PLL_CLKIN_MASK			GENMASK(3, 2)
#define ADC3101_PLL_CLKIN_SHIFT			(2)
#define ADC3101_PLL_CLKIN_MCLK			(0x00)
#define ADC3101_PLL_CLKIN_BCKL			(0x01)
#define ADC3101_PLL_CLKIN_GPIO1			(0x02)
#define ADC3101_PLL_CLKIN_DIN			(0x03)
#define ADC3101_CODEC_CLKIN_MASK		GENMASK(1, 0)
#define ADC3101_CODEC_CLKIN_SHIFT		(0)
#define ADC3101_CODEC_CLKIN_MCLK		(0x00)
#define ADC3101_CODEC_CLKIN_BCLK		(0x01)
#define ADC3101_CODEC_CLKIN_GPIO1		(0x02)
#define ADC3101_CODEC_CLKIN_PLL			(0x03)

/* ADC3101_MUTE */
#define ADC3101_MUTE_MASK				0x88
#define ADC3101_MUTE					0x88

/* ADC3101_NADC */
#define ADC3101_NADCEN					BIT(7)
#define ADC3101_NADC_MASK				GENMASK(6, 0)

/* ADC3101_MADC */
#define ADC3101_MADCEN					BIT(7)
#define ADC3101_MADC_MASK				GENMASK(6, 0)

/* ADC3101_IFACE1 */
#define ADC3101_IFACE1_DATATYPE_MASK	GENMASK(7, 6)
#define ADC3101_IFACE1_DATATYPE_SHIFT	(6)
#define ADC3101_I2S_MODE				(0x00)
#define ADC3101_DSP_MODE				(0x01)
#define ADC3101_RIGHT_J_MODE			(0x02)
#define ADC3101_LEFT_J_MODE				(0x03)
#define ADC3101_IFACE1_DATALEN_MASK		GENMASK(5, 4)
#define ADC3101_IFACE1_DATALEN_SHIFT	(4)
#define ADC3101_WORD_LEN_16BITS			(0x00)
#define ADC3101_WORD_LEN_20BITS			(0x01)
#define ADC3101_WORD_LEN_24BITS			(0x02)
#define ADC3101_WORD_LEN_32BITS			(0x03)
#define ADC3101_IFACE1_MASTER_MASK		GENMASK(3, 2)
#define ADC3101_BCLKMASTER				BIT(2)
#define ADC3101_WCLKMASTER				BIT(3)
#define ADC3101_3STATE					BIT(0)

/* ADC3101_IFACE2 */
#define ADC3101_BCLKINV_MASK			BIT(3)
#define ADC3101_BDIVCLKIN_MASK			GENMASK(1, 0)
#define ADC3101_BDIVCLKIN_SHIFT			(0)
#define ADC3101_BDIVCLKIN_ADC_CLK		(0x02)
#define ADC3101_BDIVCLKIN_ADC_MOD_CLK	(0x03)

/* ADC3101_I2S_TDM */
#define ADC3101_TDM_EN					BIT(0)
#define ADC3101_EARLY_STATE_EN			BIT(1)

/* ADC3101_PGAPIN */
#define ADC3101_PGAPIN_SEL_MASK			GENMASK(1, 0)
#define ADC3101_PGAPIN_6DB_MASK			0x55
#define ADC3101_PGAPIN2_6DB_MASK		0x15

/* ADC3101_APGAVOL */
#define ADC3101_APGA_MUTE				BIT(7)

/* ADC3101_ADC_DIGITAL */
#define ADC3101_LADC_EN					BIT(7)
#define ADC3101_RADC_EN					BIT(6)
#define ADC3101_SOFT_STEPPING_MASK		GENMASK(1, 0)
#define ADC3101_SOFT_STEPPING_SHIFT		(0)
#define ADC3101_SOFT_STEPPING_DISABLE	(0x02)
#define ADC3101_SOFT_STEPPING_HALFSTEP	(0x01)
#define ADC3101_SOFT_STEPPING_1STEP		(0x00)

enum adc_input_selection {
	CH_SEL1 = 0,
	CH_SEL2,
	CH_SEL3,
	CH_SEL4,
	CH_SEL1X,
	CH_SEL2X,
	CH_SEL3X
};

#endif				/* _TLV320ADC3101_H */