diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
index fcde737..484d117 100644
--- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
@@ -494,23 +494,35 @@
 			compatible = "mediatek,mt8167s-mipicsi-common", "syscon"; //?
 			reg = <0 15008000 0 0x10>;
 			reg-names = "seninf_top";
-			clocks =  <&imgsys CLK_IMG_LARB1_SMI>,
+			clocks =  
+				  <&topckgen CLK_TOP_CAMTG_MM_SEL>,
+				  <&topckgen CLK_TOP_USB_PHY48M>,
+				  <&topckgen CLK_TOP_UNIVPLL_D6>,
+				  <&imgsys CLK_IMG_LARB1_SMI>,
 				  <&imgsys CLK_IMG_CAM_SMI>,
 				  <&imgsys CLK_IMG_CAM_CAM>,
 				  <&imgsys CLK_IMG_SEN_TG>,
 				  <&imgsys CLK_IMG_SEN_CAM>,
 				  <&mmsys CLK_MM_SMI_COMMON>,
-				  <&topckgen CLK_TOP_CAMTG_MM_SEL>,
 				  <&topckgen CLK_TOP_CAM_MM>,
-				  <&topckgen CLK_TOP_MFG_MM>;
-			clock-names = "img_larb1_smi",
+				  <&topckgen CLK_TOP_MIPI_26M>,
+				  <&topckgen CLK_TOP_MIPI_26M_DBG>,
+				  <&topckgen CLK_TOP_MFG_MM>,
+				  <&mmsys CLK_MM_CAM_MDP>;
+			clock-names = 
+					  "top_camtg_sel",
+				      "TOP_CAM_TG_48M",  /* 48M */
+				      "TOP_CAM_TG_208M",  /* 208M, divided in setTgPhase */
+					  "img_larb1_smi",
 					  "img_cam_smi",
 					  "img_cam_cam",
 					  "img_sen_tg",
 					  "img_sen_cam",
 					  "img_venc",
-					  "top_camtg_sel",
 					  "top_cam",
+					  "mipi",
+					  "mipi_dbg",
+					  "mfg_mm",
 					  "cam_mdp";
 		};
 
@@ -524,13 +536,16 @@
 			mediatek,seninf_mux_camsv = <&seninf1_mux_camsv0>;
 			reg = <0 0x10011800 0 0x60>,  // (ana)
 				  <0 0x15008100 0 0x4>, // (seninf_ctrl)
-				  <0 0x15008300 0 0x100>; // (seninf)
+				  <0 0x15008300 0 0x100>, // (seninf)
+				  <0 0x15008000 0 0x10>; // (seninf_top)
 			reg-names = "mipi_rx_config",
 						"seninf",
-						"ncsi2";
+						"ncsi2",
+						"seninf_top";
 			mediatek,mipicsiid = <0>;
 			status="okay";
 		};
+
 	};
 };
 
@@ -579,4 +594,27 @@
 			bias-pull-down;
 		};
 	};
+
+	camera_default: camera_interposer_default {
+		pins_camera {
+			pinmux = <MT8167_PIN_84_RDN0__FUNC_RDN0>,
+				<MT8167_PIN_85_RDP0__FUNC_RDP0>,
+				<MT8167_PIN_86_RDN1__FUNC_RDN1>,
+				<MT8167_PIN_87_RDP1__FUNC_RDP1>,
+				<MT8167_PIN_88_RCN__FUNC_RCN>,
+				<MT8167_PIN_89_RCP__FUNC_RCP>,
+				<MT8167_PIN_90_RDN2__FUNC_RDN2>,
+				<MT8167_PIN_91_RDP2__FUNC_RDP2>,
+				<MT8167_PIN_92_RDN3__FUNC_RDN3>,
+				<MT8167_PIN_93_RDP3__FUNC_RDP3>,
+				<MT8167_PIN_94_RCN_A__FUNC_RCN_A>,
+				<MT8167_PIN_95_RCP_A__FUNC_RCP_A>,
+				<MT8167_PIN_96_RDN1_A__FUNC_RDN1_A>,
+				<MT8167_PIN_97_RDP1_A__FUNC_RDP1_A>,
+				<MT8167_PIN_98_RDN0_A__FUNC_RDN0_A>,
+				<MT8167_PIN_99_RDP0_A__FUNC_RDP0_A>,
+				<MT8167_PIN_102_CMMCLK__FUNC_CMMCLK>;
+		};
+	};
+
 };