)]}'
{
  "commit": "22b1908610dd7ff68471cd4fbd383dbdfe5e0ecd",
  "tree": "696d910ef791433a6a6bbd30ae841a106ce78a88",
  "parents": [
    "264edb35ce5c85749bfdd2942c74b786ea1cde41"
  ],
  "author": {
    "name": "Russell King",
    "email": "rmk@dyn-67.arm.linux.org.uk",
    "time": "Thu Jun 29 15:09:57 2006 +0100"
  },
  "committer": {
    "name": "Russell King",
    "email": "rmk+kernel@arm.linux.org.uk",
    "time": "Thu Jun 29 15:09:57 2006 +0100"
  },
  "message": "[ARM] nommu: provide a way for correct control register value selection\n\nMost MMU-based CPUs have a restriction on the setting of the data cache\nenable and mmu enable bits in the control register, whereby if the data\ncache is enabled, the MMU must also be enabled.  Enabling the data\ncache without the MMU is an invalid combination.\n\nHowever, there are CPUs where the data cache can be enabled without the\nMMU.\n\nIn order to allow these CPUs to take advantage of that, provide a\nmethod whereby each proc-*.S file defines the control regsiter value\nfor use with nommu (with the MMU disabled.)  Later on, when we add\nsupport for enabling the MMU on these devices, we can adjust the\n\"crval\" macro to also enable the data cache for nommu.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n",
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