[MIPS] Add back support for LASAT platforms
Signed-off-by: Brian Murphy <brian@murphy.dk>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index c0f052b..1bb4bf6 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -175,6 +175,13 @@
#define MACH_HP_LASERJET 1
/*
+ * Valid machtype for group LASAT
+ */
+#define MACH_GROUP_LASAT 21
+#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */
+#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */
+
+/*
* Valid machtype for group TITAN
*/
#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
diff --git a/include/asm-mips/lasat/ds1603.h b/include/asm-mips/lasat/ds1603.h
new file mode 100644
index 0000000..edcd754
--- /dev/null
+++ b/include/asm-mips/lasat/ds1603.h
@@ -0,0 +1,18 @@
+#include <asm/addrspace.h>
+
+/* Lasat 100 */
+#define DS1603_REG_100 (KSEG1ADDR(0x1c810000))
+#define DS1603_RST_100 (1 << 2)
+#define DS1603_CLK_100 (1 << 0)
+#define DS1603_DATA_SHIFT_100 1
+#define DS1603_DATA_100 (1 << DS1603_DATA_SHIFT_100)
+
+/* Lasat 200 */
+#define DS1603_REG_200 (KSEG1ADDR(0x11000000))
+#define DS1603_RST_200 (1 << 3)
+#define DS1603_CLK_200 (1 << 4)
+#define DS1603_DATA_200 (1 << 5)
+
+#define DS1603_DATA_REG_200 (DS1603_REG_200 + 0x10000)
+#define DS1603_DATA_READ_SHIFT_200 9
+#define DS1603_DATA_READ_200 (1 << DS1603_DATA_READ_SHIFT_200)
diff --git a/include/asm-mips/lasat/eeprom.h b/include/asm-mips/lasat/eeprom.h
new file mode 100644
index 0000000..3dac2036
--- /dev/null
+++ b/include/asm-mips/lasat/eeprom.h
@@ -0,0 +1,17 @@
+#include <asm/addrspace.h>
+
+/* lasat 100 */
+#define AT93C_REG_100 KSEG1ADDR(0x1c810000)
+#define AT93C_RDATA_REG_100 AT93C_REG_100
+#define AT93C_RDATA_SHIFT_100 4
+#define AT93C_WDATA_SHIFT_100 4
+#define AT93C_CS_M_100 (1 << 5)
+#define AT93C_CLK_M_100 (1 << 3)
+
+/* lasat 200 */
+#define AT93C_REG_200 KSEG1ADDR(0x11000000)
+#define AT93C_RDATA_REG_200 (AT93C_REG_200+0x10000)
+#define AT93C_RDATA_SHIFT_200 8
+#define AT93C_WDATA_SHIFT_200 2
+#define AT93C_CS_M_200 (1 << 0)
+#define AT93C_CLK_M_200 (1 << 1)
diff --git a/include/asm-mips/lasat/head.h b/include/asm-mips/lasat/head.h
new file mode 100644
index 0000000..f5589f3
--- /dev/null
+++ b/include/asm-mips/lasat/head.h
@@ -0,0 +1,22 @@
+/*
+ * Image header stuff
+ */
+#ifndef _HEAD_H
+#define _HEAD_H
+
+#define LASAT_K_MAGIC0_VAL 0xfedeabba
+#define LASAT_K_MAGIC1_VAL 0x00bedead
+
+#ifndef _LANGUAGE_ASSEMBLY
+#include <linux/types.h>
+struct bootloader_header {
+ u32 magic[2];
+ u32 version;
+ u32 image_start;
+ u32 image_size;
+ u32 kernel_start;
+ u32 kernel_entry;
+};
+#endif
+
+#endif /* _HEAD_H */
diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h
new file mode 100644
index 0000000..ea04d92
--- /dev/null
+++ b/include/asm-mips/lasat/lasat.h
@@ -0,0 +1,256 @@
+/*
+ * lasat.h
+ *
+ * Thomas Horsten <thh@lasat.com>
+ * Copyright (C) 2000 LASAT Networks A/S.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Configuration for LASAT boards, loads the appropriate include files.
+ */
+#ifndef _LASAT_H
+#define _LASAT_H
+
+#ifndef _LANGUAGE_ASSEMBLY
+
+extern struct lasat_misc {
+ volatile u32 *reset_reg;
+ volatile u32 *flash_wp_reg;
+ u32 flash_wp_bit;
+} *lasat_misc;
+
+enum lasat_mtdparts {
+ LASAT_MTD_BOOTLOADER,
+ LASAT_MTD_SERVICE,
+ LASAT_MTD_NORMAL,
+ LASAT_MTD_CONFIG,
+ LASAT_MTD_FS,
+ LASAT_MTD_LAST
+};
+
+/*
+ * The format of the data record in the EEPROM.
+ * See Documentation/LASAT/eeprom.txt for a detailed description
+ * of the fields in this struct, and the LASAT Hardware Configuration
+ * field specification for a detailed description of the config
+ * field.
+ */
+#include <linux/types.h>
+
+#define LASAT_EEPROM_VERSION 7
+struct lasat_eeprom_struct {
+ unsigned int version;
+ unsigned int cfg[3];
+ unsigned char hwaddr[6];
+ unsigned char print_partno[12];
+ unsigned char term0;
+ unsigned char print_serial[14];
+ unsigned char term1;
+ unsigned char prod_partno[12];
+ unsigned char term2;
+ unsigned char prod_serial[14];
+ unsigned char term3;
+ unsigned char passwd_hash[16];
+ unsigned char pwdnull;
+ unsigned char vendid;
+ unsigned char ts_ref;
+ unsigned char ts_signoff;
+ unsigned char reserved[11];
+ unsigned char debugaccess;
+ unsigned short prid;
+ unsigned int serviceflag;
+ unsigned int ipaddr;
+ unsigned int netmask;
+ unsigned int crc32;
+};
+
+struct lasat_eeprom_struct_pre7 {
+ unsigned int version;
+ unsigned int flags[3];
+ unsigned char hwaddr0[6];
+ unsigned char hwaddr1[6];
+ unsigned char print_partno[9];
+ unsigned char term0;
+ unsigned char print_serial[14];
+ unsigned char term1;
+ unsigned char prod_partno[9];
+ unsigned char term2;
+ unsigned char prod_serial[14];
+ unsigned char term3;
+ unsigned char passwd_hash[24];
+ unsigned char pwdnull;
+ unsigned char vendor;
+ unsigned char ts_ref;
+ unsigned char ts_signoff;
+ unsigned char reserved[6];
+ unsigned int writecount;
+ unsigned int ipaddr;
+ unsigned int netmask;
+ unsigned int crc32;
+};
+
+/* Configuration descriptor encoding - see the doc for details */
+
+#define LASAT_W0_DSCTYPE(v) (((v)) & 0xf)
+#define LASAT_W0_BMID(v) (((v) >> 0x04) & 0xf)
+#define LASAT_W0_CPUTYPE(v) (((v) >> 0x08) & 0xf)
+#define LASAT_W0_BUSSPEED(v) (((v) >> 0x0c) & 0xf)
+#define LASAT_W0_CPUCLK(v) (((v) >> 0x10) & 0xf)
+#define LASAT_W0_SDRAMBANKSZ(v) (((v) >> 0x14) & 0xf)
+#define LASAT_W0_SDRAMBANKS(v) (((v) >> 0x18) & 0xf)
+#define LASAT_W0_L2CACHE(v) (((v) >> 0x1c) & 0xf)
+
+#define LASAT_W1_EDHAC(v) (((v)) & 0xf)
+#define LASAT_W1_HIFN(v) (((v) >> 0x04) & 0x1)
+#define LASAT_W1_ISDN(v) (((v) >> 0x05) & 0x1)
+#define LASAT_W1_IDE(v) (((v) >> 0x06) & 0x1)
+#define LASAT_W1_HDLC(v) (((v) >> 0x07) & 0x1)
+#define LASAT_W1_USVERSION(v) (((v) >> 0x08) & 0x1)
+#define LASAT_W1_4MACS(v) (((v) >> 0x09) & 0x1)
+#define LASAT_W1_EXTSERIAL(v) (((v) >> 0x0a) & 0x1)
+#define LASAT_W1_FLASHSIZE(v) (((v) >> 0x0c) & 0xf)
+#define LASAT_W1_PCISLOTS(v) (((v) >> 0x10) & 0xf)
+#define LASAT_W1_PCI1OPT(v) (((v) >> 0x14) & 0xf)
+#define LASAT_W1_PCI2OPT(v) (((v) >> 0x18) & 0xf)
+#define LASAT_W1_PCI3OPT(v) (((v) >> 0x1c) & 0xf)
+
+/* Routines specific to LASAT boards */
+
+#define LASAT_BMID_MASQUERADE2 0
+#define LASAT_BMID_MASQUERADEPRO 1
+#define LASAT_BMID_SAFEPIPE25 2
+#define LASAT_BMID_SAFEPIPE50 3
+#define LASAT_BMID_SAFEPIPE100 4
+#define LASAT_BMID_SAFEPIPE5000 5
+#define LASAT_BMID_SAFEPIPE7000 6
+#define LASAT_BMID_SAFEPIPE1000 7
+#if 0
+#define LASAT_BMID_SAFEPIPE30 7
+#define LASAT_BMID_SAFEPIPE5100 8
+#define LASAT_BMID_SAFEPIPE7100 9
+#endif
+#define LASAT_BMID_UNKNOWN 0xf
+#define LASAT_MAX_BMID_NAMES 9 /* no larger than 15! */
+
+#define LASAT_HAS_EDHAC (1 << 0)
+#define LASAT_EDHAC_FAST (1 << 1)
+#define LASAT_HAS_EADI (1 << 2)
+#define LASAT_HAS_HIFN (1 << 3)
+#define LASAT_HAS_ISDN (1 << 4)
+#define LASAT_HAS_LEASEDLINE_IF (1 << 5)
+#define LASAT_HAS_HDC (1 << 6)
+
+#define LASAT_PRID_MASQUERADE2 0
+#define LASAT_PRID_MASQUERADEPRO 1
+#define LASAT_PRID_SAFEPIPE25 2
+#define LASAT_PRID_SAFEPIPE50 3
+#define LASAT_PRID_SAFEPIPE100 4
+#define LASAT_PRID_SAFEPIPE5000 5
+#define LASAT_PRID_SAFEPIPE7000 6
+#define LASAT_PRID_SAFEPIPE30 7
+#define LASAT_PRID_SAFEPIPE5100 8
+#define LASAT_PRID_SAFEPIPE7100 9
+
+#define LASAT_PRID_SAFEPIPE1110 10
+#define LASAT_PRID_SAFEPIPE3020 11
+#define LASAT_PRID_SAFEPIPE3030 12
+#define LASAT_PRID_SAFEPIPE5020 13
+#define LASAT_PRID_SAFEPIPE5030 14
+#define LASAT_PRID_SAFEPIPE1120 15
+#define LASAT_PRID_SAFEPIPE1130 16
+#define LASAT_PRID_SAFEPIPE6010 17
+#define LASAT_PRID_SAFEPIPE6110 18
+#define LASAT_PRID_SAFEPIPE6210 19
+#define LASAT_PRID_SAFEPIPE1020 20
+#define LASAT_PRID_SAFEPIPE1040 21
+#define LASAT_PRID_SAFEPIPE1060 22
+
+struct lasat_info {
+ unsigned int li_cpu_hz;
+ unsigned int li_bus_hz;
+ unsigned int li_bmid;
+ unsigned int li_memsize;
+ unsigned int li_flash_size;
+ unsigned int li_prid;
+ unsigned char li_bmstr[16];
+ unsigned char li_namestr[32];
+ unsigned char li_typestr[16];
+ /* Info on the Flash layout */
+ unsigned int li_flash_base;
+ unsigned long li_flashpart_base[LASAT_MTD_LAST];
+ unsigned long li_flashpart_size[LASAT_MTD_LAST];
+ struct lasat_eeprom_struct li_eeprom_info;
+ unsigned int li_eeprom_upgrade_version;
+ unsigned int li_debugaccess;
+};
+
+extern struct lasat_info lasat_board_info;
+
+static inline unsigned long lasat_flash_partition_start(int partno)
+{
+ if (partno < 0 || partno >= LASAT_MTD_LAST)
+ return 0;
+
+ return lasat_board_info.li_flashpart_base[partno];
+}
+
+static inline unsigned long lasat_flash_partition_size(int partno)
+{
+ if (partno < 0 || partno >= LASAT_MTD_LAST)
+ return 0;
+
+ return lasat_board_info.li_flashpart_size[partno];
+}
+
+/* Called from setup() to initialize the global board_info struct */
+extern int lasat_init_board_info(void);
+
+/* Write the modified EEPROM info struct */
+extern void lasat_write_eeprom_info(void);
+
+#define N_MACHTYPES 2
+/* for calibration of delays */
+
+/* the lasat_ndelay function is necessary because it is used at an
+ * early stage of the boot process where ndelay is not calibrated.
+ * It is used for the bit-banging rtc and eeprom drivers */
+
+#include <linux/delay.h>
+
+/* calculating with the slowest board with 100 MHz clock */
+#define LASAT_100_DIVIDER 20
+/* All 200's run at 250 MHz clock */
+#define LASAT_200_DIVIDER 8
+
+extern unsigned int lasat_ndelay_divider;
+
+static inline void lasat_ndelay(unsigned int ns)
+{
+ __delay(ns / lasat_ndelay_divider);
+}
+
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
+
+#define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef
+#define LASAT_SERVICEMODE_MAGIC_2 0xfedeabba
+
+/* Lasat 100 boards */
+#define LASAT_GT_BASE (KSEG1ADDR(0x14000000))
+
+/* Lasat 200 boards */
+#define Vrc5074_PHYS_BASE 0x1fa00000
+#define Vrc5074_BASE (KSEG1ADDR(Vrc5074_PHYS_BASE))
+#define PCI_WINDOW1 0x1a000000
+
+#endif /* _LASAT_H */
diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h
new file mode 100644
index 0000000..065474f
--- /dev/null
+++ b/include/asm-mips/lasat/lasatint.h
@@ -0,0 +1,12 @@
+#define LASATINT_END 16
+
+/* lasat 100 */
+#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000))
+#define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000))
+#define LASATINT_MASK_SHIFT_100 0
+
+/* lasat 200 */
+#define LASAT_INT_STATUS_REG_200 (KSEG1ADDR(0x1104003c))
+#define LASAT_INT_MASK_REG_200 (KSEG1ADDR(0x1104003c))
+#define LASATINT_MASK_SHIFT_200 16
+
diff --git a/include/asm-mips/lasat/picvue.h b/include/asm-mips/lasat/picvue.h
new file mode 100644
index 0000000..42a492e
--- /dev/null
+++ b/include/asm-mips/lasat/picvue.h
@@ -0,0 +1,15 @@
+/* Lasat 100 */
+#define PVC_REG_100 KSEG1ADDR(0x1c820000)
+#define PVC_DATA_SHIFT_100 0
+#define PVC_DATA_M_100 0xFF
+#define PVC_E_100 (1 << 8)
+#define PVC_RW_100 (1 << 9)
+#define PVC_RS_100 (1 << 10)
+
+/* Lasat 200 */
+#define PVC_REG_200 KSEG1ADDR(0x11000000)
+#define PVC_DATA_SHIFT_200 24
+#define PVC_DATA_M_200 (0xFF << PVC_DATA_SHIFT_200)
+#define PVC_E_200 (1 << 16)
+#define PVC_RW_200 (1 << 17)
+#define PVC_RS_200 (1 << 18)
diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h
new file mode 100644
index 0000000..bafe68b
--- /dev/null
+++ b/include/asm-mips/lasat/serial.h
@@ -0,0 +1,13 @@
+#include <asm/lasat/lasat.h>
+
+/* Lasat 100 boards serial configuration */
+#define LASAT_BASE_BAUD_100 (7372800 / 16)
+#define LASAT_UART_REGS_BASE_100 0x1c8b0000
+#define LASAT_UART_REGS_SHIFT_100 2
+#define LASATINT_UART_100 8
+
+/* * LASAT 200 boards serial configuration */
+#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12)
+#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300)
+#define LASAT_UART_REGS_SHIFT_200 3
+#define LASATINT_UART_200 13
diff --git a/include/asm-mips/mach-lasat/mach-gt64120.h b/include/asm-mips/mach-lasat/mach-gt64120.h
new file mode 100644
index 0000000..1a9ad45
--- /dev/null
+++ b/include/asm-mips/mach-lasat/mach-gt64120.h
@@ -0,0 +1,27 @@
+/*
+ * This is a direct copy of the ev96100.h file, with a global
+ * search and replace. The numbers are the same.
+ *
+ * The reason I'm duplicating this is so that the 64120/96100
+ * defines won't be confusing in the source code.
+ */
+#ifndef _ASM_GT64120_LASAT_GT64120_DEP_H
+#define _ASM_GT64120_LASAT_GT64120_DEP_H
+
+/*
+ * GT64120 config space base address on Lasat 100
+ */
+#define GT64120_BASE (KSEG1ADDR(0x14000000))
+
+/*
+ * PCI Bus allocation
+ *
+ * (Guessing ...)
+ */
+#define GT_PCI_MEM_BASE 0x12000000UL
+#define GT_PCI_MEM_SIZE 0x02000000UL
+#define GT_PCI_IO_BASE 0x10000000UL
+#define GT_PCI_IO_SIZE 0x02000000UL
+#define GT_ISA_IO_BASE PCI_IO_BASE
+
+#endif /* _ASM_GT64120_LASAT_GT64120_DEP_H */
diff --git a/include/asm-mips/nile4.h b/include/asm-mips/nile4.h
new file mode 100644
index 0000000..c3ca959
--- /dev/null
+++ b/include/asm-mips/nile4.h
@@ -0,0 +1,310 @@
+/*
+ * asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions
+ *
+ * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
+ * Sony Software Development Center Europe (SDCE), Brussels
+ *
+ * This file is based on the following documentation:
+ *
+ * NEC Vrc 5074 System Controller Data Sheet, June 1998
+ */
+
+#ifndef _ASM_NILE4_H
+#define _ASM_NILE4_H
+
+#define NILE4_BASE 0xbfa00000
+#define NILE4_SIZE 0x00200000 /* 2 MB */
+
+
+ /*
+ * Physical Device Address Registers (PDARs)
+ */
+
+#define NILE4_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */
+#define NILE4_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */
+#define NILE4_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */
+#define NILE4_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */
+#define NILE4_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */
+#define NILE4_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */
+#define NILE4_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */
+#define NILE4_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */
+#define NILE4_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */
+#define NILE4_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */
+#define NILE4_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */
+#define NILE4_INTCS 0x0070 /* Controller Internal Registers and Devices */
+ /* [R/W] */
+#define NILE4_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */
+
+
+ /*
+ * CPU Interface Registers
+ */
+
+#define NILE4_CPUSTAT 0x0080 /* CPU Status [R/W] */
+#define NILE4_INTCTRL 0x0088 /* Interrupt Control [R/W] */
+#define NILE4_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */
+#define NILE4_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */
+ /* Enable [R/W] */
+#define NILE4_INTCLR 0x00A0 /* Interrupt Clear [R/W] */
+#define NILE4_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */
+
+
+ /*
+ * Memory-Interface Registers
+ */
+
+#define NILE4_MEMCTRL 0x00C0 /* Memory Control */
+#define NILE4_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */
+#define NILE4_CHKERR 0x00D0 /* Memory Check Error Status [R] */
+
+
+ /*
+ * PCI-Bus Registers
+ */
+
+#define NILE4_PCICTRL 0x00E0 /* PCI Control [R/W] */
+#define NILE4_PCIARB 0x00E8 /* PCI Arbiter [R/W] */
+#define NILE4_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */
+#define NILE4_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */
+#define NILE4_PCIERR 0x00B8 /* PCI Error [R/W] */
+
+
+ /*
+ * Local-Bus Registers
+ */
+
+#define NILE4_LCNFG 0x0100 /* Local Bus Configuration [R/W] */
+#define NILE4_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */
+#define NILE4_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */
+#define NILE4_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */
+#define NILE4_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */
+#define NILE4_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */
+#define NILE4_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */
+#define NILE4_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */
+#define NILE4_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */
+ /* Enables [R/W] */
+#define NILE4_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */
+#define NILE4_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */
+
+
+ /*
+ * DMA Registers
+ */
+
+#define NILE4_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */
+#define NILE4_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */
+#define NILE4_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */
+#define NILE4_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */
+#define NILE4_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */
+#define NILE4_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */
+
+
+ /*
+ * Timer Registers
+ */
+
+#define NILE4_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */
+#define NILE4_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */
+#define NILE4_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */
+#define NILE4_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */
+#define NILE4_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */
+#define NILE4_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */
+#define NILE4_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */
+#define NILE4_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */
+
+
+ /*
+ * PCI Configuration Space Registers
+ */
+
+#define NILE4_PCI_BASE 0x0200
+
+#define NILE4_VID 0x0200 /* PCI Vendor ID [R] */
+#define NILE4_DID 0x0202 /* PCI Device ID [R] */
+#define NILE4_PCICMD 0x0204 /* PCI Command [R/W] */
+#define NILE4_PCISTS 0x0206 /* PCI Status [R/W] */
+#define NILE4_REVID 0x0208 /* PCI Revision ID [R] */
+#define NILE4_CLASS 0x0209 /* PCI Class Code [R] */
+#define NILE4_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */
+#define NILE4_MLTIM 0x020D /* PCI Latency Timer [R/W] */
+#define NILE4_HTYPE 0x020E /* PCI Header Type [R] */
+#define NILE4_BIST 0x020F /* BIST [R] (unimplemented) */
+#define NILE4_BARC 0x0210 /* PCI Base Address Register Control [R/W] */
+#define NILE4_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */
+#define NILE4_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */
+#define NILE4_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */
+ /* (unimplemented) */
+#define NILE4_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */
+#define NILE4_SSID 0x022E /* PCI Sub-System ID [R/W] */
+#define NILE4_ROM 0x0230 /* Expansion ROM Base Address [R] */
+ /* (unimplemented) */
+#define NILE4_INTLIN 0x023C /* PCI Interrupt Line [R/W] */
+#define NILE4_INTPIN 0x023D /* PCI Interrupt Pin [R] */
+#define NILE4_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */
+#define NILE4_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */
+#define NILE4_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */
+#define NILE4_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */
+#define NILE4_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */
+#define NILE4_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */
+#define NILE4_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */
+#define NILE4_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */
+#define NILE4_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */
+#define NILE4_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */
+
+
+ /*
+ * Serial-Port Registers
+ */
+
+#define NILE4_UART_BASE 0x0300
+
+#define NILE4_UARTRBR 0x0300 /* UART Receiver Data Buffer [R] */
+#define NILE4_UARTTHR 0x0300 /* UART Transmitter Data Holding [W] */
+#define NILE4_UARTIER 0x0308 /* UART Interrupt Enable [R/W] */
+#define NILE4_UARTDLL 0x0300 /* UART Divisor Latch LSB [R/W] */
+#define NILE4_UARTDLM 0x0308 /* UART Divisor Latch MSB [R/W] */
+#define NILE4_UARTIIR 0x0310 /* UART Interrupt ID [R] */
+#define NILE4_UARTFCR 0x0310 /* UART FIFO Control [W] */
+#define NILE4_UARTLCR 0x0318 /* UART Line Control [R/W] */
+#define NILE4_UARTMCR 0x0320 /* UART Modem Control [R/W] */
+#define NILE4_UARTLSR 0x0328 /* UART Line Status [R/W] */
+#define NILE4_UARTMSR 0x0330 /* UART Modem Status [R/W] */
+#define NILE4_UARTSCR 0x0338 /* UART Scratch [R/W] */
+
+#define NILE4_UART_BASE_BAUD 520833 /* 100 MHz / 12 / 16 */
+
+
+ /*
+ * Interrupt Lines
+ */
+
+#define NILE4_INT_CPCE 0 /* CPU-Interface Parity-Error Interrupt */
+#define NILE4_INT_CNTD 1 /* CPU No-Target Decode Interrupt */
+#define NILE4_INT_MCE 2 /* Memory-Check Error Interrupt */
+#define NILE4_INT_DMA 3 /* DMA Controller Interrupt */
+#define NILE4_INT_UART 4 /* UART Interrupt */
+#define NILE4_INT_WDOG 5 /* Watchdog Timer Interrupt */
+#define NILE4_INT_GPT 6 /* General-Purpose Timer Interrupt */
+#define NILE4_INT_LBRTD 7 /* Local-Bus Ready Timer Interrupt */
+#define NILE4_INT_INTA 8 /* PCI Interrupt Signal INTA# */
+#define NILE4_INT_INTB 9 /* PCI Interrupt Signal INTB# */
+#define NILE4_INT_INTC 10 /* PCI Interrupt Signal INTC# */
+#define NILE4_INT_INTD 11 /* PCI Interrupt Signal INTD# */
+#define NILE4_INT_INTE 12 /* PCI Interrupt Signal INTE# (ISA cascade) */
+#define NILE4_INT_RESV 13 /* Reserved */
+#define NILE4_INT_PCIS 14 /* PCI SERR# Interrupt */
+#define NILE4_INT_PCIE 15 /* PCI Internal Error Interrupt */
+
+
+ /*
+ * Nile 4 Register Access
+ */
+
+static inline void nile4_sync(void)
+{
+ volatile u32 *p = (volatile u32 *)0xbfc00000;
+ (void)(*p);
+}
+
+static inline void nile4_out32(u32 offset, u32 val)
+{
+ *(volatile u32 *)(NILE4_BASE+offset) = val;
+ nile4_sync();
+}
+
+static inline u32 nile4_in32(u32 offset)
+{
+ u32 val = *(volatile u32 *)(NILE4_BASE+offset);
+ nile4_sync();
+ return val;
+}
+
+static inline void nile4_out16(u32 offset, u16 val)
+{
+ *(volatile u16 *)(NILE4_BASE+offset) = val;
+ nile4_sync();
+}
+
+static inline u16 nile4_in16(u32 offset)
+{
+ u16 val = *(volatile u16 *)(NILE4_BASE+offset);
+ nile4_sync();
+ return val;
+}
+
+static inline void nile4_out8(u32 offset, u8 val)
+{
+ *(volatile u8 *)(NILE4_BASE+offset) = val;
+ nile4_sync();
+}
+
+static inline u8 nile4_in8(u32 offset)
+{
+ u8 val = *(volatile u8 *)(NILE4_BASE+offset);
+ nile4_sync();
+ return val;
+}
+
+
+ /*
+ * Physical Device Address Registers
+ */
+
+extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,
+ int on_memory_bus, int visible);
+
+
+ /*
+ * PCI Master Registers
+ */
+
+#define NILE4_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */
+#define NILE4_PCICMD_IO 1 /* PCI I/O Space */
+#define NILE4_PCICMD_MEM 3 /* PCI Memory Space */
+#define NILE4_PCICMD_CFG 5 /* PCI Configuration Space */
+
+
+ /*
+ * PCI Address Spaces
+ *
+ * Note that these are multiplexed using PCIINIT[01]!
+ */
+
+#define NILE4_PCI_IO_BASE 0xa6000000
+#define NILE4_PCI_MEM_BASE 0xa8000000
+#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE
+#define NILE4_PCI_IACK_BASE NILE4_PCI_IO_BASE
+
+
+extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr);
+
+
+ /*
+ * Interrupt Programming
+ */
+
+#define NUM_I8259_INTERRUPTS 16
+#define NUM_NILE4_INTERRUPTS 16
+
+#define IRQ_I8259_CASCADE NILE4_INT_INTE
+#define is_i8259_irq(irq) ((irq) < NUM_I8259_INTERRUPTS)
+#define nile4_to_irq(n) ((n)+NUM_I8259_INTERRUPTS)
+#define irq_to_nile4(n) ((n)-NUM_I8259_INTERRUPTS)
+
+extern void nile4_map_irq(int nile4_irq, int cpu_irq);
+extern void nile4_map_irq_all(int cpu_irq);
+extern void nile4_enable_irq(unsigned int nile4_irq);
+extern void nile4_disable_irq(unsigned int nile4_irq);
+extern void nile4_disable_irq_all(void);
+extern u16 nile4_get_irq_stat(int cpu_irq);
+extern void nile4_enable_irq_output(int cpu_irq);
+extern void nile4_disable_irq_output(int cpu_irq);
+extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
+extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
+extern void nile4_clear_irq(int nile4_irq);
+extern void nile4_clear_irq_mask(u32 mask);
+extern u8 nile4_i8259_iack(void);
+extern void nile4_dump_irq_status(void); /* Debug */
+
+#endif
+
