tree 330bd3eff26a1915e86b5e896cdee4db2c909896
parent 4080e99b8341f81c4ed1e17d8ef44d171c473a1b
author Thierry Reding <treding@nvidia.com> 1438863631 +0200
committer Thierry Reding <treding@nvidia.com> 1439478328 +0200

iommu/tegra-smmu: Parameterize number of TLB lines

The number of TLB lines was increased from 16 on Tegra30 to 32 on
Tegra114 and later. Parameterize the value so that the initial default
can be set accordingly.

On Tegra30, initializing the value to 32 would effectively disable the
TLB and hence cause massive latencies for memory accesses translated
through the SMMU. This is especially noticeable for isochronuous clients
such as display, whose FIFOs would continuously underrun.

Fixes: 891846516317 ("memory: Add NVIDIA Tegra memory controller support")
Signed-off-by: Thierry Reding <treding@nvidia.com>